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ME1010 RF Circuit Design (Agilent Genesys)

Lab 7
RF Oscillator Design

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Objectives
i)
To design a fixed frequency oscillator circuit based on negative resistance approach
ii)
To perform small-signal verification of the oscillator circuit in frequency domain
iii)
To perform large-signal computer simulation of the oscillator circuit in time and frequency
domains

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1.

Background

In this lab we will be designing a single transistor fixed frequency oscillator at 470 MHz. We will use an
approach known as negative-resistance oscillator (NRO) method. Please refer to the lecture slides of
ME1000 for detailed theoretical treatment on this subject. Here we will split the transistor oscillator circuit
into a destabilized amplifier and a resonator portion, as shown in Figure 1. We need to come up with a
small-signal amplifier circuit with the impedance looking towards the input given by Z1=R1+jX1 at
fo= 470 MHz. Positive feedback is applied to the amplifier circuit, destabilizing it such that R1 is negative
at fo, hence the name NRO. We then proceed to design a reactive circuit, called the resonator. The
resistance and reactance of the resonator must be such that R1+Rres < 0 and X1 + Xres = 0 at f o. In this
way when the resonator is connected to the destabilized amplifier input, the circuit will (note: not all the
time, see discussion in notes) begin to oscillate near fo when power is supplied to the circuit. Tuning of the
resonator component will bring the oscillation frequency to f o. A large-signal analysis using Harmonic
Balanced method can then be applied to check the steady-state oscillator waveforms, frequency stability,
phase noise, load and supply pulling characteristics and harmonics.
Z1 = R1 + jX1

Resonator

Destabilized
amplifier

Load

Necessary small-signal
conditions for oscillation:
R1 + Rres < 0 at fo
X1 + Xres = 0 at fo

Zres = Rres + jXres

Figure 1 Block Diagram of Negative Resistance Oscillator

The transistor we will be using for this lab is BFR92A, a wideband NPN transistor from NXP
Semiconductors with nominal fT of 5 GHz. This will be more than sufficient for oscillation in the vicinity of
500 MHz.
NOTE: In this lab we will assume that you are already familiar with Genesys user interface, so we will not
show the procedures explicitly as in previous labs but will only show the required schematics and other
windows.
Visit the following YouTube video link to learn more about Genesys:
http://www.youtube.com/user/AgilentEEsof#g/c/20B8D0B20980AA06
Recommended videos for this lab:
1. Genesys Cayenne Nonlinear Time-Domain Transient Circuit Simulator

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2.

RF Oscillator

2.1 DC Biasing Circuit Design for the Destabilized Amplifier

1. As usual run Genesys from Windows desktop.
2. Create a new workspace, add a schematic and insert the transistor BFR92A. Use the Part
Selector A window to find the transistor as shown in Figure 2.
3. Complete the schematic; here we are using a degenerated common-emitter topology for the
transistor. The complete schematic is illustrated in
Figure 3. Use a
supply voltage of 3.3 V. Save the schematic giving it a meaningful name, say Amp_DC.
4. Add a DC analysis into your Workspace (use all the default settings in the DC analysis). Run it
and the DC voltages and current will be displayed in the voltage test points and current probe in
the schematic. Verify that the transistor Q1 is in the active region. See
Figure 3 for the sample results.

Figure 2 Searching and Inserting a Commercial Spice Model (BFR92A)

ME1010 RF Circuit Design (Agilent Genesys)

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SG1
VDC=3.3V

You can also use the DC

voltage source from Part
Selector A

LC
L=220nH

Current probe

IC
IDC=3.665e-3A
RB1
R=47000
VC
VDC=3.3V

VB
VDC=1.165V

Voltage test
point

Q1 {BFR92A@Philips_Wideband}

RE
R=220

Figure 3 The DC Bias Circuit

2.2 Destabilized Amplifier Circuit and AC Analysis

1. Modify your DC biasing schematic as shown in Figure 4. Here series-shunt feedback is used to
make the amplifier unstable. Save your new schematic as DestabAmp_AC.

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Tune these

Standard
Input Port

Load
resistor

Z1 = R1 + jX1

Figure 4 Destabilized Amplifier Circuit and the Linear Analysis Settings

2. Insert a Linear Analysis (or small-signal AC analysis) into your design and refer it to the
DestabAmp_AC schematic. The settings are shown in Figure 4. Lets call this Linear 1.
3. Now run the Linear Analysis. Our aim is to examine the input impedance as a function of
frequency. Open the simulated data for Linear Analysis, insert the necessary plots to show real
and imaginary parts of Z1 (see Figure 5 and Figure 6).
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Plot real and

imaginary parts of Zin

Figure 5 Plotting R1 and X1 Versus Frequency

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ZIN1

100
40
-20
-80

470 MHz, -115.241

re(ZIN1)

-140
-200
-260
-320
-380
-440
-500
100

290

480

670

860

1050
Frequency (MHz)

1240

1430

1620

1810

2000

1240

1430

1620

1810

2000

re(ZIN1)

ZIN1

470 MHz, -98.232

-150
-300
-450

im(ZIN1)

-600
-750
-900

-1050
-1200
-1350
-1500
100

290

480

670

860

1050
Frequency (MHz)
im(ZIN1)

Figure 6 Results of Linear Analysis

4. You need to make sure R1 is negative at 470 MHz. Try tuning capacitors C 1 and C2, and inductor
LC. This will change R1 and X1. Of course, changing the biasing Q1 and loading will have the same
effect. Experiment on your own and refer to the lecture notes and other literature for the details
and mathematical analysis. Typically R1 of 15 or smaller is sufficient to ensure oscillation start up
in the real physical circuit. See lecture notes or books on the effect of R 1 on the steady-state
waveforms.
5. Put a marker at 470 MHz to read out R1 and X1 at 470 MHz. Here R1@470 MHz = 115.24 and X1@470
MHz = 98.23. You need to scale the X and Y axis of the graph to see the waveform as shown in
Figure 6.

2.3 Resonator Design and Time-Domain Verification

1. From the results of last section (2.2), the resonator needs to produce a reactance X res of +98.23 in
order for the final oscillator circuit to oscillate near 470 MHz. This can be realized by an inductor
with inductance of 33 nH. The complete oscillator circuit is shown in Figure 7. Save this
schematic as Osc_Tran. Rres is to model the loss in the inductor by deliberate addition of series
resistor.
2. In order to start-up the oscillation process, a seed signal is needed. In real life this seed signal is
provided by the noise signal in the circuit or transient when we power up the oscillator circuit. This
being a virtual model, we need to artificially provide the seed signal. This is done using a pulse as
shown in Figure 7, connected in series with the DC voltage source. The position of the pulse
source is not crucial. Note that the source frequency is almost zero. This means that within our
normal duration of analysis, we only see a pulse at the start of simulation. After that, this source is
effectively shorted (V = 0).

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VS1
V1=0V
V2=0.1V
TD=0ns
TR=1ns
PW=1ns
TF=1ns
F0=0.00001MHz

SG1
VDC=3.3V

To inject artificial
transient into the
circuit to start the
oscillation process

LC
L=220nH
RB1
R=47000

Resonator

VC
VDC=3.3V

VB
VDC=1.481V

Cc1
C=47pF
Rres
R=5

VL
VDC=0V

Cc2
C=47pF

Destabilized
Amplifier

RL
R=50

Q1 {BFR92A@Philips_Wideband}

C1
C=4.7pF

RE
R=220

Lres
L=33nH
C2
C=6.8pF

Figure 7 Complete Oscillator Circuit

3. Insert a Transient Analysis module with the settings as shown in Figure 8.

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Figure 8 Transient Analysis Settings

4. Now run the Transient Analysis. Plot the voltage at the transistors Collector and Load of the
oscillator. The results are shown in Figure 9. Try changing the value of Rres and see how it affects
the duration of start-up and the steady-state waveforms. Also change L res value and see its effect
on the steady-state oscillation frequency (you can work out the frequency from the voltage
waveforms by first finding the period).
5. Is the steady-state oscillation frequency fosc 470 MHz? Tune Lres so that foscillation is within
0.2 MHz of 470 MHz.

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Voltage

3.2

2.4

1.6

Start-up

Steady-state

V8, V13 (V)

0.8

-0.8

-1.6

-2.4

-3.2

-4
0

10

20

30

40

50
Time (ns)

V8

60

70

80
V13

90
100 of
Note the
number
each connection or net

Figure 9 Voltage Waveforms at Collector and Load from Transient Analysis

2.4 Frequency-Domain Verification

1. We can also perform a frequency domain analysis of the steady-state response of the oscillator
using Harmonic Balance (HB) method. Read up on this by referring to sources from books and
the Internet. Unlike the Transient Analysis which provides the start-up and steady-state view
information, the HB analysis uses optimization method to predict the steady-state voltages and
currents in the circuit. It does this by estimating the magnitude and phase (e.g., the phasor) of
each Fourier component of the voltages and currents.
2. Oscillator analysis using HB approach needs to know the approximate steady-state frequency,
and also whether the circuit is stable or not (if the circuit is not stable, then it wont oscillate and
HB analysis will fail). This is achieved by performing a small-signal or linear analysis of the circuit,
basically a reverse of the procedures that we use in Section 2.2 (note that there are many
approaches to analyse stability of a system). The small-signal analysis will tell the HB analysis
engine the estimated oscillation frequency, and the HB engine will use this information to predict
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the large-signal (or steady-state) voltage and current phasors. The small-signal analysis is done
automatically in Genesys, in the form of Oscillator Port. Modify the Osc_Tran schematic of
Section 2.3 to the circuit shown in Figure 10. Save this as Osc_HB.

Initially use
information from
Section 2.2

SG1
VDC=3.3V

LC
L=220nH

OSCPORT_OSCPORT_1
FOSC=470MHz
VPROBE=0V

Cc2
C=47pF

RB1
R=47000
VC
VDC=3.3V

VB
VDC=1.481V

Cc1
C=47pF
R1
R=10

RL
R=50

Q1 {BFR92A@Philips_Wideband}

C1
C=4.7pF

RE
R=220

L1
L=33nH
C2
C=6.8pF

Figure 10 The Schematic for Harmonic Balance (HB) Analysis of Oscillator

3. Insert a Harmonic Balance Oscillator Analysis module into your Workspace, call this HBOSC1.
Set it as shown in Figure 11. Run the analysis.
4. Open the data from HBOSC1. You can see a variety of data, those that show the voltage or
current phasors and the time-domain waveforms. See Figure 12. The time-domain waveforms are
obtained by performing summing of all the Fourier components of a voltage or current. For
instance, the voltage at transistors Collector terminal in time and frequency domain is shown in
Figure 12. Observe the voltage phasor at the load. Tune the components in the circuit to see if
you can reduce the harmonics at the load.

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The highest Fourier

component to consider
(The larger the more
accurate but takes more
computational time)

Figure 11 Settings for HB Analysis of Oscillator

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This is frequency domain data,

e.g., voltage phasor.

W indicates time-domain, e.g.,

waveform. You can also see the
time-domain waveform of other
voltages and currents. Explore for
yourself or seek out Genesyss
help to see how this is done.

W_VVC

3.7

VVC

3.58

3.46

3.34

VVC (V)

W_VVC (V)

3.22

3.1

2.98

2.86

0.1

2.74

2.62

2.5
0

0.431

0.861

1.292

1.723

2.153
Time (ns)

2.584

3.014

3.445

3.876

4.306

240

480

720

960

W_VVC

1200
Frequency (MHz)

1440

1680

1920

2160

2400

VVC

Figure 12 The Results of HB Analysis

3.

Review Questions

1. If we require that the oscillation frequency be 500 MHz instead of 470 MHz, should we increase
or decrease the inductance of L1?
2. What will happen if the capacitance CC1 is too small?
3. Modify your schematicby replacing L1 with a series LC network, with the C tunableinto a
variable frequency oscillator. Suggest an approach to implement a voltage-controlled variable
capacitor, and with this, modify your circuit into a voltage-controlled oscillator (VCO).

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Appendix Screenshot of the Complete Workspace

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