Content

1.PLL
2.Controlled Oscillators
3.Frequency Synthesizers
4.Frequency Dividers

Chapter 7 Phase Lock Loops

and Frequency Synthesizer

Phase-Locked Loop (Contd.)

1. Phase-Locked Loop (PLL)

1) Architecture
Xc(t)

Phase Detector

ed(t)

eo(t)

1. Analog Phase-locked Loop

1) Good frequency resolution
2) Long settling time
3) Requires careful designing of the
components in PLL to maintain the
damping characteristics.

Loop Filter
F(s)

ev(t)

Divider by m/m+1

Voltage-controlled
Oscillator

2. All Digital Phase-locked Loop

1) Good programmability
2) Fast settling
3) Poor frequency resolution

Output

2.Basic PLL architecture:

If the phase detector is of analog-multiplier
type, its output voltage Vpd can be written as

Low-pass

Vpd=KMVinVosc=KM Ein Eoscsin(t)cos(t-d)

where d is the phase difference between
the input signal Vin and the output Vosc of
the VCO.
Vpd=KM(EINEOSC/2)[sin(d)+sin(2t-d]

Since the lowpass filter is to remove the highfrequency (2) term, the signal Vcntl is given by

where in is the frequency of the input signal,

which is equal to the frequency of VCO output when
the PLL is in the locked state.

The frequency of VCO can be expressed as

osc=KoscVcntl+fr
where fr is the free-running frequency of the
VCO with its control voltage Vcntl=0.

3.Linearized small-signal analysis

When a PLL is in lock, its dynamic response (,f) can
be well approximated by a linear model, with slow
and small about their operating point.
A signal-flow graph for the linearized small-signal
model of a PLL when in lock:

General transfer function applicable to almost

every PLL.
* Different PLLs => Different Hlp(s), Kpd, Kosc.

10

If a lead-lag lowpass filter is used in Hlp(s), we have

The above second-order s-domain transfer functions

have o and Q as
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12

In most cases, when o<<fr, we have

The transient time constant pll of the complete loop

for small phase or frequency changes can be as

good settling behavior

maximally flat group delay
maximally flat amplitude response
* Usually Q=1/2 is recommended in PLLs

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Design considerations:

4. Capture range and acquisition time

1)Choose Kpd and Kosc based on

practical considerations
2)Choose p to achieve the desired
loop settling time
3)Choose Z to obtain the desired Q
of the loop

Capture range:
The maximum difference between the input
signals frequency and the VCO free-running
frequency where lock can eventually be
attained.
The capture range is on the order of the pole
frequency of the lowpass filter.
Acquisition time:
The time required to attain lock If the initial
difference between the input signal's frequency and
the VCO frequency is moderately large, the
acquisition time tacq is

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If a PLL is designed to have a narrow loop

bandwidth o, tacq can be quite large and lock is too
slowly.
Solution:
1) To add a frequency detector that detect when
in- osc is large. Then drive the loop toward lock
much more quickly. When in-osc is small, the
frequency detector and the driver are disabled.
2) To design the lowpass filter with a programmable
pole frequency o.
Initial acquisition: o speed up acquisition.
Lock :
o increase noise rejection.
3) To sweep the VCO's frequency range during
acquisition with the PLL disabled. When oscin,
sweeping is disabled and PLL is activated.

5. Lock range
Lock range: Once lock is attained, the PLL remains
in lock over a range as long as the input signal's
freq. in changes only slowly. This range is the lock
range, which is much larger than the capture range.

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II. Phase Detectors in PLLs

18

II.1 Multiplier PD

Three categories:
1) Analog phase detectors (PDs) or multipliers:
Rely on the DC component when multiplying two
sinusoidal waveforms of the same frequency.

At phase lock, 1=2

2) Sequential circuits (e.g. EXOR and Flip-Flop PDs):

Operate on the information contained in the zerocrossings of the input signal to aid acquisition
when the loop is out of lock. Also a sequential
circuit actually.

After the lowpass filter, we have

3) Phase-frequency detector:
Provide a frequency sensitive signal to aid
acquisition when the loop is out of lock. Also a
sequential circuits actually.
19

* The multiplier PD is especially useful in applications where the

reference frequency is too high and where the loop bandwidth is
sufficiently narrow so that the filtering of the undesired components
can be effective.
* The loop could lock to harmonics of the input signal. =>False
lock
* 1=2 is required.

20

II.2 EXOR PD

II.3 Flip-Flop PD

* when A(Vin) and B(Vosc) are 90 out of phase, the

output Vpd(c ) has =2in and 50% duty cycle.
This is a reference point. Vpd d for 0o<d<180.
* False lock could occur
* 1=2 is required.
21

* The average value of Vpd or C has the shape of a

saw tooth, with a linear range of a full cycle.
* At the center of the linear range of Vpd average,
the most important harmonic is situated at the
fundamental of the reference frequency as
compared to the twice of reference frequency in
the EXOR PD.

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II.4 Charge-pump PD

1. Desirable features:

23

1) It does not exhibit false lock.

2) Vin and Vosc are exactly in phase when the loops in lock.
3) The PLL attains lock quickly even when in is quite
different from fr.

24

Some typical waveforms of a charge-pump PD

2.Small-signal analysis of a charge-pump PLL:

The average charge flow into the lowpass filter is

For the lowpass filter R, C1 has a transfer function

Hlp(s) as
Substituting Hlp(s) and Kpd into the transfer function
we have
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3. Design Considerations:
(1) Choose Ich based on practical consideration like
power dissipation and speed.
(2) o is chosen according to the desired transient
settling-time constant pll as o=1/pll
(3) C1 is chosen from the equation of o whereas R
is chosen using the equation of Q. The chosen
Q value is slightly less than what is eventually
desired.
R => Q
(4) Add C2 to minimize glitches.
C2 => Q => chosen Q value is smaller => Exact Q.

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4. Phase/Frequency detector (PFD)

* Basic operating principle:

* The most common sequential phase detector is the PFD.

* Asynchronous sequential logic circuit.
* 4 NOR-type RS flip-flops.
* Can also be realized in NAND gates.

Assume the PLL is in lock with Vin leading Vosc

Initial conditions: Pu=0, Pd=0, Pu-dsbl=0,
Pd-dsbl=0, Reset=0 Vin=0, Vosc=0
inputs: 1001
Vin1
Vosc1
=> Pu=1 => Charge pumping starts and Vlp => osc
=> Reset nor gate inputs: 00010000 => Reset 01
=> Pu=0 and Pd=0 after one gate-delay ; Pd 010
Pu-dsbl=1 and Pd-dsbl=1 after two gate-delays.
=> Reset 10 after one gate-delay of Pu-dsbl1 and
Pd-dsbl1 or after three gate-delays of Vosc1.
=> Keeping Pu=0 and Pd=0 => No charge pumping.

29

* The waveforms of a PFD when Vin is at a higher

frequency than Vosc.

It is only when Vin 10 => FF3 is reset and Pu-dsbl=0

Vosc 10 => FF4 is reset and Pd-dsbl=0

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* Transfer characteristic of a charge-pumping PFD

in>osc => Pu=1 => Charge pumping to increase

osc until lock is achieved.
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III. Loop Filters and Loop Gains

III.1 First-order PLL with zero-order loop filter
Loop gain of the feedback structure with in(s) and Vcntl(s)

Loop gain=GH(s)=Kpd Klp KoscHlp(s)/s

Zero-order loop filter: Hlp(s)=1
=> GH(S)=KpdKlpKosc/s

Bode plots of GH(s)

PLL with zeroorder loop filter

=> First-order type-1 PLL

33

III.2 Second-order PLL with first-order loop-filter

close-loop transfer function

34

III.3 Third-order PLL with second-order loop filter

To improve the transient characteristics of the PLL, a
low-frequency pole a is introduced in the loop filter.
=> Extra phase shift of 90.
To compensate the extra phase shift, a compensating
zero z must be introduced in order to keep the
phase margin high enough.

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36

Bode plots of GH(s)

III.4 Third-order type-2 charge-pump PLL

37

VI. Voltage-Controlled Oscillators (VCOs)

Basic VCO specifications/requirements:
1) phase stability:
The output spectrum of the VCO should approximate
as good as possible the theoretical Dirac-impulse of
a single sine wave, i.e. low phase noise.
The definition of phase noise:

38

2) Electrical tuning range

The VCO must be able to cover the complete
required frequency band of the application,
including initial frequency offsets due to process
variations.
3) Tuning linearity
To simplify the design of the PLL, the VCO gain
Kosc should be constant.
4) Frequency pushing (MHz/V)
The dependency of the center frequency on the
power supply voltage
5) Frequency pulling
The dependence of the center
frequency
6) Low cost

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10

VI.1 Relaxation oscillator as VCO

VI.2 Ring oscillator as VCO

* Tosc=2nTd n: number of inverters; Td: one inverter
delay.
* Tuning: varying the current of the inverters.
* High phase noise: switching action introduces a
lot of disturbances.
* Power consumption linearly => phase noise
* Typical phase noise:
-94dBc/Hz at 1 MHz offset from a 2.2GHz carrier.
-83dBc/Hz at 100 KHz offset from a 900MHz carrier.
* Circuit structure

* Multivibrator-based nonlinear oscillator.

* fosc~in the order of a few 100 MHz
* In CMOS, phase noise value of -90dBc/Hz at
500KHz offset.
Ref.: IEEE JSSC, vol.23, pp.1386-1393, Dec. 1988.

41

1) Three-stage ring oscillator

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3) 1-stage-delay ring oscillator

2) Differential two-stage ring oscillator

* fosc MHz ~ GHz

Ref.: 1. Proc. of IEEE 1995 Custom Integrated
Circuits Conference (CICC), pp.331-334.
2. IEEE JSSC, vol.31, pp.331-334, March 1996.
43

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11

VI.3 LC-oscillator as VCO

Design example: 0.7m CMOS planar-LC VCO.

* Typically a 20dB better phase noise obtained over

ring and relaxation oscillators.
* High-speed operation is possible due to the
simple working principle.
* The realization of the inductor is the key point.

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Measurement results:
* Constant current => To limit
power dissipation
* M1 and M2: To provide a
negative resistance for
oscillation
* L1=L2=3.2nH planar spiral
inductors
* p+ n-well junction
diodes C1 and C2 as
varactors for frequency
tuning by Vc. C1=C21pF
* Different output voltage.
Chip photograph of the VCO.
(Die size 750750 m2)

1) Measured output spectrum for a carrier frequency

of 1.81 GHz.

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48

12

2) Measured phase noise w.r.t. frequency offset

Phase noise: -116dBc/Hz at 600 KHz offset

3) Measured frequency tuning characteristics

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* At Vc=0.5V, the diode varactors C1 and C2 have a

larger leakage current => Phase noise 3dB.

50

VI.4 Comparisons of Integrated VCOs

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13

V. The Dead Zone of the charge-pump PLL

1. Charge-pump PLL

TG

: the phase difference between in and out

T: the time of phase difference between QA and QB
TG: Gate delay of the reset path in PFD
Assume the current source of the charge pump need a time TI to turn on.
When 0, T+TG<TI, where 0 is a constant phase difference.
Vcontrol will not change, and can not be detected.
53

Charge pump current v.s.

54

2. Solution
Increasing TG by delay chain to eliminate dead zone

+ 0

The dead zone causes the additional jitter in time domain.

The jitter in frequency domain is called phase noise.

55

If the TG >TI, =>T+TG>TI, even when the

input phase difference is zero, the charge pump
current I1 and I2 turn on for a narrow pulse.

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14

3. Disadvantage of charge-pump PLL with delay chain in PFD

Because of the channel length modulation effect, the

current of the charge pump (I1,I2) may not the same.
When the PLL is locked, this mismatch current
causes a small ripple on Vcontrol.
Q1
Q2
I1
I2
Mismatch

(I1-I2)
57

Vcontrol

58

VI. Application of PLL on Clock Generator

1. Block diagram of the clock generator

The ripple amplitude is Vm and ripple frequency is

in. This ripple causes spurious tones at the output
spectrum of VCO.
Ripple of input frequency
and amplitude Vm

Desired
tone

Frequency
Spurious
tone

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60

15

2. Circuit diagram of each block

(2) Charge pump and Loop filter

(1) PFD

Iup

Ref Clock

UP

UP

UP

Vctrl
Vctrl

Delay elements

Vtrace
DN

DN

R2
C3
C1

IDN

VCO_OUT

DOWN
61

(3) VCO

Complementary switch to prevent current source

IUP, IDN from turning off.
Voltage equalization Vctrl Vtrace

62

Ex. 2: Differential delay element VCO

Ex. 1: voltage controlled ring oscillator.

Vctrl

Vref

VCO_OUT

START

StartReset the VCO, or shunt-down the VCO.

Frequency is varied by adjusting Vctrl.
63

Vctrl_coarseCoarse tuning, by adjusting variable resistor, Rvar.

Vctrl_fineFine tuning, by adjusting the bias current of each
delay stage.
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16

(4) Divider, (1/2N)

VII. Application of PLL on Frequency Synthesizer

1. Block diagram of the frequency synthesizer
fout

fref
fin
fout= fin/2N

N-stage D Flip-Flop

Channel Select
Change the dividing ratio of the frequency divider to
get different fout.
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66

2. Pulse-swallow frequency divider

Advantage:
The prescaler uses 2 modulus (N, (N+1)).
(1). Decrease power consumption.
(2). Easy to design

1) A dual modulus prescaler to scale down the high

frequency output of VCO.
2) When the swallow counter is overflow, the prescaler
change modulus from (N+1) to N.
3) The overall dividing ratio is (N+1)S+N(P-S)=NP+S
4) controlling S can control the overall dividing ratio

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68

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3. Circuit diagram of each block

(3) Block diagram of 2N / 2N +1dual-modulus frequency
divider

(1) Block diagram of dividing-by-2 frequency divider

(2) Block diagram of 2/3 dual-modulus frequency divider

MC : modulus control

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(1) Use the Current-match charge pump to reduce the spur level.

4. Example A 2.4GHz Low Spurious and Quadrature

Output Frequency Synthesizer [1]
Technology: Standard TSMC 0.25um 1P5M CMOS
process
Architecture: Integer-N Frequency Synthesizer
Power supply: 2.5 V
Dividing modulus: 2402~2480
Power consumption: 33 mW
Spurious tones: 65dBc @ 1MHz offset
Phase noise: -101.27 dBc/Hz @ 600 kHz offset

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72

18

(2) Die photo:

1) M14, M15 and M16 provide M12 the same VGS as M10.
2) M17, M18 and M19 provide M13 the same VGS as M11.
3) The error-amp, M17, M18, M19 and M13 form a feed
back loop.
4) Use the feedback loop to make Vtrace =Vc (when loop
is locked).
5) When Vtrace=Vc the current of IM12 =I1 and IM13=I2.
6) IM12=IM13=Iref => I1=I2 =>the current is matched.

73

(3) Measurement spurious tones = 65dBc @ 1MHz offset

74

Phase-Frequency Detector (PFD)

1. Tri-State PFD
REF

REF
REF

UP=1
DN=0

UP=0
DN=0
INT

UP=0
DN=1

INT

INT

(UP,DN) = (0,0) No lead/lag information

(UP,DN) = (1,0) REF leads INT in phase
(UP,DN) = (0,1) REF lags behind INT in phase
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19

Tri-State PFD

Tri-State PFD
1. Timing Diagram:

1. Circuit

REF

REF

INT

INT

UP

INT

UP

Phase lead

RST

DN

DN

Spike due to time

delay of RST

B
REF

REF

INT

INT

UP

UP

DN

RST

1. Consists of two D-flip-flops and on AND gate.

2. Spurious signal occurs due to delay of reset signal

DN

Phase lag

77

Charge-Pump Loop Filter

III.2 Controlled Oscillators

1. Charge or discharge the loop filter capacitor.

3-state
PD

78

1. Voltage-Controlled Oscillators (VCO)

2. Digital-Controlled Oscillators (DCO)
3. Numerical-Controlled Oscillators (NCO)

RD

V3

79

80

20

Voltage-Controlled Oscillator
1. Output frequency depends on input voltage.

Stops oscillating
beyond here

LC-based Oscillator
( harmonic oscillator )

1V

2V

Vc

81

82

Digital-Controlled Oscillator (DCO) (Cont.)

Digital-Controlled Oscillator (DCO)

8-cell DCO with control bits DCW[15:5]

1. Basic DCO cell

DCW
IN

Two energy storage

elements operating in
resonance
High quality and low
jitter
usually off-chip , onchip version has been
reported

OUT IN

OUT

1XW-5
1XW-6

9
DCW

1XW-15:7
1XW-15:7
83

Enable

84

21

Numerical Controlled Oscillator (NCO)

Numerical Controlled Oscillator (Cont.)

1. Architecture

1. Properties
High switching speed
Fast programmability
Good phase continuity

Addr.
Select
Logic

-phase
Buffer
Register

-phase
Register

48-bit
Phase
Accumulator

Sin/Cos
Lookup
Table SINE(11-0)
or COS(11-0)

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D/A

Digital Synthesizer

3 Frequency Synthesizers

1. Similar to NCO

1) Digital Synthesizer
2) Direct Frequency Synthesizer
3) Phase-Locked Frequency Synthesizer

Accumulator

Memory
cos

D/A

Low pass
filter

Shift
out

D/A
Output
Accumulator
Output
Waveform
87

From Goldberg

88

22

Successively finer approximation of the target frequency

30.6

27

24MHz
(3.0ba)

(30.a)MHz (3.0a) 27.0a (30.ba)

27MHz

10

(3.a)

10

+3.6

3.06

10

27.06 30.56 3.056

+24

+3.5

10

Phase-locked Frequency Synthesizer

1. Incorporate frequency dividers in a PLL
Reference
Oscillator

(27.0ba)

3.056

27.056 30.456 3.0456 27.0456

+24

(3.b)

+3.4

10

+24

3.0MHz
30.3456 3.03456 27.03456
27.0456

+3.3

3.8
3.9MHz
Switch

10

+24

+3.2

30.123456
Switch

+3.1

-23
7.123456
89

III.4 Frequency Dividers

90

Dual-Modulus Frequency Divider

1. Architecture

1. Dual-modulus frequency divider

2. Fractional-N frequency divider
Reference
Frequency
Fref

91

Fout

92

23

Dual-Modulus Frequency Divider

Fractional-N Frequency Divider

1. Count P+1 for A times and count P for M A

times, thus divide by A(P+1) + (MA)P = MP+A
2. fout = (MP+A)fref

Pulse
Remover

3. Phase detector operates once every Tref, thus

slow settling.
1/M

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Phase-locked loops (PLLs)

Fractional-N Frequency Divider

1. M is the number of pulses removed ever TRM.
2. fY = fout MfRM, fout = fref + MfRM
3. Large phase jitter due to unstable VCO input.
4. Use delta-sigma technique to shape the phase
noise to outside the loop band.

Phase-locked loop is a feedback

arrangement capable to synchronize
itself to a noisy external reference
The output signals of the loop can
be used to produce for instance
multitude of locked frequencies
PLL application areas include...

95

modulators
demodulators
frequency synthesis
multiplexers
signal processors
96

24

PLL based frequency synthesizer

Reference signal
fin is locked for
instance to the
fundamental
frequency of a
crystal oscillator

fin
Phase
Phase
detector
detector

Divide
Divideby
by
10
10
By adjusting the divider
different frequencies
can be produced whose
phase is locked into fin

Filt.
Filt.

_
Analysis and Design of
Phase-Locked Loops

VCO
VCO

fout =10 fin

97

Block diagram of a phase-locked loop

98

Linear model of a phase-locked loop

99

100

25

Loop Filter (2nd Order)

Opened-Loop Response

101

Opened-Loop Response

102

Closed-Loop Response

Third-order system

103

104

26

Design Strategy

Design Strategy

Close loop considerations

Open loop considerations

Set C2 >20 C1 for 65 phase margin
Set c < ref / 5
Set phase margin to at least 65 or at maximum

105

106

Reference Spur Attenuation

Design of the 3rd-order filter

Current switching noise in the dividers and the

charge pump circuit at the reference rate, Fref,
may cause unwanted FM sidebands at RF output.

The added attenuation from the lowpass filter is

The spurious sidebands can cause noise in

adjacent channels.
Additional attenuation from the added passive
loop filter is required.

In terms of the attenuation of the reference

spurs added by the lowpass pole, one have

3rd-order filter
Recommended value of T3 is

107

108

27

Design of the 3rd-order filter

Design Example

The new open loop unity gain frequency (loop

bandwidth) can be approximated to be

As a rule of thumb:

The value of C3 must include the input capacitance

of VCO.

The approximation for c can be used up to 1/5fref.

109

Design Example

110

PLL Behavior Simulation by Simulink

111

112

28

Phase Noise

Phase Noise

A typical sinusoidal signal,

If (t) << 1radian,based on the narrowband

FM approximation,

Neglecting amplitude noise,

The approximated RF spectrum is
the instantaneous frquency for Vout(t),

The Single-Sideband Phase Noise Referenced to

Carrier, L(f)

113

114

Typical VCO Phase Noise

Noise Response

IEEE JSSC-33, pp.179-,Feb. 1998. & IEEE JSSC-33,pp.828,June 1998.

115

116

29

Typical PLL Phase Noise

Phase Frequency Detector

To reduce the dead zone, the delay can be inserted at the output of
the 4-input NAND.

fPLL is the opened-loop unity-gain bandwidth(~c)

117

Phase Frequency Detector

118

Phase Frequency Detector

Phase frequency comparator with equal short duration

output pulses for in-phase inputs.
IEEE JSSC, SC-31, pp. 1723-, Nov. 1996.

Increasing the delay will reduce the maximal frequency of the PFD. IEEE
JSSC-25, pp.1019-,Aug. 1990

Precharge-type phase frequency detector (ptPFD)

119

IEICE Trans. Electronics, E78-C, pp.381-,April 1995.

120

30

Phase Frequency Detector

Phase Frequency Detector

Conventional phase
frequency detector
(a)The ptPFD in zero degree phase offset version. (b) Modified version
with rad phase offset. IEEE JSSC, SC-33, pp. 295-, Feb. 1998.

121

Phase Frequency Detector

Implemented phase
frequency detector

IEEE JSSC, SC-32, pp. 691-, May 1997.

122

Current-Pump Circuit
Problems:
1. Charge Sharing
2. Charge Injection

Qcp=CpV=50fF*500mV
Q=I* t=10uA* t
t=2.5ns static

phase offset for PFDs

input

IEE E.L., Vol.-34, pp.2121-, Oct. 1998.

123

124

31

Current-Pump Circuit

Oscillator

Problems:
1. Offset of OP AMP
2. Equal delay for
UP and DN

IEEE JSSC, SC-27, pp. 1599-, Nov. 1992.

Small-Signal Model

Conditions of Oscillation
* Unity-gain at fo
*Zero Total Phase Shift at fo

125

Basic Noise Mechanism

126

Noise in Control Path

For sinusoidal disturbance:

127

Mechanism is similar to FM
Up-converts noise spectrum from LF to the band
around carrier
Flicker noise is important
All the sources of FM should be considered

128

32

Jitter, Phase Noise, and Sidebands

Types of Jitter
Long-Term Jitter: the maximum change in a clocks
output transition from its ideal position over many
cycles
Cycle-to-Cycle Jitter

Jitter
Jitter may result from phase noise or sidebands
Random jitter and phase noise originate from:
- Supply and substrate noise
- Device noise (e.g. Flicker and Thermal noise)
Sidebands usually result from periodic
disturbance of control path

Period (Cycle) Jitter

129

Sources of Jitter

130

Sources of Jitter

1. Device Noise (Thermal, Flicker)

Flicker noise varies the oscillation
frequency slowly; It can be suppressed by
the wide-BW of PLLs.
Thermal noise generates white frequency
noise. Relationship between phase noise
and cycle-to-cycle jitter

131

2. Supply Noise
Supply and substrate noise varies voltagedependent capacitances.==> modulating the
oscillation frequency
Can view the circuit as a VCO with the supply or
substrate acting as control line.
3. Substrate Noise
Vth modulation

132

33

Jitter Due to Supply Noise

Simulation Results
Single-end Ring

Differential Ring

133

134

Jitter Due to Substrate Noise

Jitter Due to Supply Noise

Substrate noise sensitivities can be minimized by

Supply noise sensitivities can be minimized by

isolating the delay elements from supply.
Use buffered control voltage as supply voltage
Use buffered control voltage to generate a bias
current ==> Current source isolation
Simple Current Source ==>5%/V sensitivity
Cascode Current Source ==>0.5%/V
sensitivity (2Vds needed)
Replica current source ==> 0.5%/V sensitivity

135

Using well-type devices for current sources

Using well-type devices for loop filter capacitor
Using well-tap voltage as control voltage
reference
Only connecting control voltage to well-type
devices
Dont connect control voltage to pad directly

136

34

Voltage-Controlled Oscillators

Variable Delay Elements

1. Ring Oscillators
2. Multivibrators
3. LC tank Oscillators

(a) Clamped-load (b) Symmetric-load (c) Cross-coupled-load

137

Variable Delay Using Local Feedback

138

Ring Oscillator

Monolithic PLLs and Clock Recovery Circuits, IEEE Press, pp. 1, 1996
139

140

35

CMOS Ring Oscillator ( cont. )

Vdd
Oscillator loop

Icont

CMOS Ring Oscillator ( cont. )

Three-stage ring Osc.

Fout

Measurement
Prescaler

Icont

Fout

Fig. 6 VCO3 (a) fully differential oscillator using double flip-flops, (b) the implemented
circuit, (c) redrawn with different ring structure and regenerative circuits.

Delay cell

Biasing Circuit

141

VCOs Phase Noise Calculation

142

Current Controlled Oscillator

IEEE JSSC, SC-27, pp. 1599-, Nov. 1992.

143

144

36

Symmetric Load Amplifier

Multivibrator

(a)

(b)

Differential buffer delay stage with symmetric loads.

IEEE JSSC, SC-31, pp.1723-, Nov. 1996.

145

Multivibrator

146

LC Tank Oscillator

(b)

(a)

f
147

148

37

Current Reuse

5-satge Ring Oscillator

149

5-satge Ring Oscillator

150

Multivibrator

151

152

38

LC Tank Oscillator

Comparisons of three kinds of Osc.

153

Frequency Divider

154

Divide-by-Two Circuits

Divide-by-Two

IEEE JSSC, SC-31, pp.

890-, July 1996.
155

156

39

Q1
D

Q2
D

Fig. Logic
implementation
of a 4/5 dualmodulus counter
(dual-modulus
counter whose
state diagram
has two paths)

Q3
D

D Q

D Q

D Q

Q1

Q2

Q3

f4/5

Q4
D

157

TSPC Dynamic Circuit

158

Functional block diagram of the dual modulus prescaler

IEEE JSSC, SC-31, pp. 749-, May 1996.

159

160

40

High frequency CMOS dual-modulus prescaler

Divide-by3/4

TSMC 0.8-mm SPDM CMOS process

VDD=5V, Max. operating freq. :1 GHz
161

Timing diagram
Waveform on the divided-by-4
circuit (MC=0)

A High-Speed Divide-by-4/5 Counter for a

Dual-Modulus Prescaler

TSMC 0.6-m SPDM CMOS process

Max. operating freq. : 1.1 GHz , Power : 19.2 mW@
VDD=3V

162

3 V 4 GHz Prescaler with improved DFF

Waveform on the divided-by-5
circuit (MC=1)
Preamplifier

163

CHIP Features
Technology : 0.35m SHARP SPDM
Core area : 570!N100 m2
Supply voltage : 3V
Power : 90.3 mW
Max. operating freq.: !a4000 MHz

164

41

Improved TSPC ratioed DFF

TSPC DFF by Yuan and Svensson

165

Input Preamplifer Design

166

Measured waveforms of the prescaler

167

168

42

Measured waveforms of the prescaler

Measured maximum operating

frequency and power dissipation

169

170

Circuit Implementation

Regenerative Frequency Divider

Mixer

Amplifier

Fin - Fout=Fout => Fout=Fin/2

Low frequency operation limitation

LPF is realized by the low-pass
characteristic of amplifiers

Gilberts cell
171

Gain=gmMBN2/gmMBN3
172

43

The principle of injection locking

The phenomenon of injection locking

Without injection

With injection

Finj=1408MHz -2.3dBm(165mv)
173

174

Measured max. operating freq. and power

versus supply voltage

Proposed Dynamic Back Gate Forward Bias DFF and LFF

Maximum operating
frequency of BGFB
prescaler
Maximum operating
frequency of TSPC
prescaler
Power dissipation of
BGFB prescaler
Power dissipation of
TSPC prescaler

175

176

44

1V CMOS Synthesizer
CHIP Features
Technology : 0.35m Sharp DPDM
Supply voltage : 1V & 3V
Power : 10 mW

Max. operating freq.: 160 MHz PLL noise@100KHz : -100 dBc/Hz

A Fully Integrated Variable

Frequency Synthesizer for GSM

177

Outline

178

Wideband IF Receiver Arch.

Design specifications
Comparison of possible approaches
- PLL, DLL, DDFS
Implementation of synthesizer with DLL
-Architecture
-Phase bank generation with DLL
-Phase sampler
-Control bit stream generator
-Power estimation
Conclusion

Fixed LO1 is used to mix the entire RF band to IF

Variable LO2 is used to tune the desired channel
from IF to baseband
179

180

45

Alternate Approaches

Comparison of possible approaches

PLL, DLL, DDFS => PLL Approach

DDFS (Direct Digital Frequency Synthesis)

-Too much power ~ 1W
DLL (Delay-Locked-Loop)
-Key idea: VCD (Voltage Controlled Delay
Line)
-VCD phase noise inherently lower than
VCO
-Much lower power than DDFS

fo = N x fref

Phase noise depends on performance of

integrated VCO.
LC tuned oscillator: Q of on-chip L is too
low at 200MHz
Ring oscillator: Phase noise is too high for
GSM

181

182

DLL Approach
The DLL includes a voltage controlled delay line
(VCDL), a phase detector , a charge pump and a
firstfirst-order loop filter.

PLL
PLLs
Channel
Select
codeword

and DLL
DLLs are employed in microprocessor and
memory IC
ICs in order to cancel the buffering delays
and improve the I/O timing margins.

183

184

46

Sample Output Waveform

Characteristics of DLL
Multistandard capable
-Easily adaptable to DECT and other
standards
No noise accumulation from one cycle to
the next
-10dB-20dB reduction in phase noise
Low power solution is possible
Easier to design than PLL

185

Implementation of synthesizer with DLL

186

Synthesizer Architecture

Challenges in Implementation
Phase noise is limited by tap resolution
Long DLL chain length N is needed
tref = 5ns, tp = 100ps, --> N = tref/tp = 50
Mismatch accumulates in the chain
worst case at the center of the chain
Phase sampling is variable rate --> Complicated
Selection logic needed
Need to generate control bit stream
Possible solution: Sigma-Delta

187

188

47

Phase bank generation with DLL

Phase Bank Requirements

Simulation Results

Minimum delay achieved in 0.35m CMOS is ~50ps

Phase noise (f) depends on tap resolution
f = peak freq deviation = 1/tref - 1/(tref+tp)
tp/tref2
fm = modulation freq
(f) ( f/2fm)2 tp2
Tap resolution (tp) of 10ps is required to
meet the specs (-129dbc to -146dbc)

189

Phase Interpolation

190

Phase Interpolation w/ DLL Array

Need phase interpolation to improve tap

resolution
Existing technique for phase interpolation
requires too much power. (see T. Knotts, 1994 ISSCC)
# of delay cells = N(1+2+4+...+2k) where
k = level of interpolation, N = delay chain length
Power # of delay cells
New technique (DLL array) is developed to achieve
linear dependence of power on the level of
interpolation

191

192

48

-Interpolation with DLL Array (2)

Mismatch Tones

Number of delay cells interpolation level

Power number of cells
Need phase detector with zero static phase
error
Mismatch of cells creates spurious tones if
the control bit stream has fixed pattern
tone height (n /2k)2 for the kth
tone away from carrier
n = delay chain length
2 = variance of mismatch

193

Phase sampler

194

256 to 1 Phase Selector (2)

256 to 1 Phase Selector

Use tree structure to:
minimize delay
reduce the complexity of 8-256 decoder,
only two 4-16 decoder are required
increase decoding speed
reduce power in decoder
reduce the fanout at the output

195

196

49

Phase Latch

Phase interpolator
The phase interpolator receives two clocks ,and
generates the main clock
clock whose phase is weighted sum
of the two input phases. (1(1-/16)
/16) + (
(/16)
/16) ;
(-)=30o or -30o
The phase interpolator converts a digital weight code
generated form the FSM to the phase of clock
clock.

197

Phase interpolator(cont.)

198

Finite State Machine Design

typeII

Example on next page

Due to the gaingain-toto-drain capacitance of input transistor

in type I , the design (tpye
(tpye I) doesn
doesnt completely satisfy
the seamless boundary switching requirement.
199

60
30

90

120
180
240
300
150
210
270
330
200

50

S-R Latch-Based Phase Detector

Finite State Machine Design (Cont.)

Ex.The reference phase is in 80 degrees.

Initial condition :
Early = 1, Weight=ffff
Weight=ffff
Interpolation boundary :
As weight decreases to 0000 , Early toggle to 0.

60
30

90

120
180
240
300
150
210
270
330

Lock Point
The
201

One-shot Delay Generator

SS-R latch ensures a 180o phase shift between the rising edges of
its inputs only when the duty cycle of the two input clocks is identical.
identical. 202

Control Bit Stream Generator

Digital is used at this stage

Interpolative may improve noise

shaping

203

204

51

Power estimation
System Power Estimation
DLL
Phase Selector
Fix delay
Phase Latch
Digital
Total

30-50mW
1-3mW
5-8mW
1mW
8mW
45-70mW

Assumptions:
current density in DLL : I/W =30A/m
500fF/8bits for adders, f = 250MHz

Fig. 1 Parallel-coupled LC QVCO

205

206

Four-phase VCO

Fig. 2 Cascode-coupling LC QVCO

207

208

52

TSPC (True Single-Phase Clock) Divided-by 2

Reference
slave:Uphight

Precharge-type PFD

209

210

Modified Charge Pump Circuit

Charge Pump Circuit

1.
2.

211

charge sharing

212

53

(Loop Filter)

1/40

Fig. 4 180
213

214

215

216

Buffer_I

Fig. 5 QVCO

54

References
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[Ali ISSCC96] A. Ali and L. Tham, "A 900-MHz frequency synthesizer with integrated LC
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55