BUS INTERFACE UNIT(BUI):

The bus interface unit is used to organize all the bus activities of the processor.
The address driver is connected with the internal 32 bit address o/p of the cache and the system
bus. The data bus transceivers are interconnected between the internal 32-bit data bus and the
system bus. The write data buffer is queue of four 80 bit registers and is able to hold the 80 bit
data which will be the written to the memory. Due to pipelined execution of the write operation,
data must be available in advance. To control the bus access and operations, the following bus
control and the request sequencers ADS#, W/R# ,D/C#, M/IO#, PCD, PWT, RDY@, LOCK#,
PLOCK#,BOFF#,A20M#,BREQ,HOLD,HLDA,RESET,INTR,NMI,FERR#,and IGNNE# are
used.
EXECUTION UNIT (EU) AND CONTROL UNIT (CU):
The burst control signal updates the processor that the burst is ready. T his
signal works as a ready signal in the burst cycle. The BLAST# output shows that previous burst
cycle is over. The bus size control signals BS16# and BS8# indicates dynamic bus sizing. The
cache control signals KEN@,FLUSH,AHOLD and EADS# are used to control the cache control
unit.
The parity generation and control unit generates the parity and carries out the
checking during the processor operation. The boundary scan control unit of the processor
performs boundary scan tests operation to ensure the correct operation of all components of the
circuit on the mother board.
The prefetcher unit fetches the codes from the memory and arranges them in a
32 byte code queue. The function of the instruction decoder is to receive the code from the code
queue and then decodes the instruction code sequentially. The output of the decoder is fed to
the control unit to derive the control signals, which are used for execution of the decoded
instructions. Before execution, the protection units check all the protection norms. If there is any
violation, an appropriate execution is generated.
The control ROM stores a micro program to generate control signal for
execution of instructions. The register bank and ALU are used for their usual operation just like
they perform in 80286. The barrier shifter is used to perform the shift and rotate algorithms. The
segmentation unit, description registers, paging unit, translation look aside buffer and limit and
attribute PLA are worked together for the virtual memory management. These units also provide
protection to the op-codes or operand in the physical memory.
FLOATING-POINT UNIT(FPU):
The floating point unit and register bank of FPU communicate with tha bus
interface unit (BIU) under the control of memory management unit (MMU), through a 64-bit
internal data bus. Generally the FPU is used for mathematical data processing at very high
speed of compare to the ALU.

BUS CYCLE DEFINTION GROUP:

Bus control group:
ADS#: The ADS# (address data strobe) output pin indicates that the address
bus contains a valid memory address.
RDY#: The RDY# (ready) input pin acts as a ready signal and this signal is
used for the current nonburst cycle.
Burst control group:
BRDY#: The BRDY# (burst ready) input indicate the burst mode of memory
read or memory operation. During the burst mode, the speed of memory access may be
doubled compared to the normal memory read/write operation.
BLAST#: When the BLAST# (burst last) output signa is hgh, it indicates the
CPU initiates the burst mode of memory access. If this signal is low, it indicates that the burst
bus cycle is completed and the BRDY# signal is next asserted for starting the next memory
access operation.
Bus arbitration group:
HOLD: The HOLD pin act as a local bus hold input. This pin may be activated
by another bus master like DMA controller. This pin is functionally similar to tha BREQ pin.
HLDA: The HLDA output signal is used to acknowledge the receipt of a valid
a HOLD request.
BREQ: When the BREQ (bus request) output signal is active high, it indicates
that the 80486 CPU has generated a internal bus request.
BOFF#: When the BOFF# (back off) input pin is at logical level1,80486 CPU
places its buffer at hold state. The active high back-off input signal forces the current bus master
of 80486 CPU release the bus in the next clock cycle.
Cache control group:
KEN#: The KEN# (cache enable) input pin is used to decide whether the
current cycle is cacheable or not.
FLUSH#: The FLUSH# is a cache flush input signal. When this pin is
activated, it clears the cache contents and validity bits.

CODE AND DATA CACHE:

There are separate code and data caches, and the cache line size is 32 bits
just like the 80486 processor. Each cache is connected with its own translation look-aside buffer
(TLB).Therefore, the paging unit of a memory management unit (MMU) can rapidly convert
linear code or data addresses into physical addresses. Due to two separate caches, the prefetches cannot conflict with data access cycles.
BRANCH PREDICTION:
Branch prediction consists of control unit (CU) and a Branch Trace Buffer
(BTB). The function of control unit and branch trace buffer is as follows:
Branch Trace Buffer: The BTB is used to store the target address and statistical information
about the branch operation. Hence, the branch prediction is able to predict branches and cause
the Pentium to use the most likely target address for instruction fetching. Pipeline freeze up
caused by pipeline flushes and the subsequent fetching operations are reduced and the
program execution is accelerated.
Control Unit:
The control unit controls the five-stage integer pipelines U and V, and the
eight-stage floating-point pipeline. In the Pentium processor, the integer pipelines are used for
all instructions which are not involved in any floating-point operations. Therefore, the Pentium
can transmit two integer instructions in the same clock cycle and the performance of the
processor is improved. This method is called superscalar architecture.
The first four stages of floating- point pipeline overlap with the Pipeline and
the parallel operation of the integer and the floating-point pipeline is possible only under some
specified conditions. If the operating clock frequency of Pentium is as same as 80486, the
Pentium floating-point unit is able to execute floating-point instructions 3 to 5 times faster than
80486.This is possible as a hardware mulitiplier,divider and quicker algorithms are incorporates
in the microcode floating-point unit.
The Pentium has a microcode support unit to support complex function. The
support unit controls the pipelines with the microcode. Actually, this unit uses both pipelines
together. Therefore, complex microcode instructions run very fast on a Pentium than on a
80486.
INTEGER PIPELINES U AND V:
The Pentium is a superscalar processor and it has two integer pipelines, called
u and v. The process is issuing two instructions in parallel is known as paring.
The U-pipeline is able to handle the full instruction set of the Pentium but the Vpipeline has limited handling capability .The V-pipeline is able to handle only simple instructions
without any microcode support. The V-pipeline is used to execute simple integer instruction
such as load/store type instructions and the FPU instruction FXCH, but the U-pipeline executes

any legitimate Pentium instruction. Actually , Pentium processor use a set of pairing rules to
select a simple instruction which can go through the V-pipeline . When instructions are paired,
initially the instruction is issued to the V-pipeline.
There are two integer pipelines and a floating-point unit in the Pentium
processor.

PREFETCH (PF)
DECODE-1 (D1)
DECODE-2 (D2)
EXECUTE (E)
WRITE BACK (WB)