1st Power Electronic & Drive Systems & Technologies Conference

Transformerless DVR Topology Based on Multilevel

Inverter with Reduced Number of Switches
M. Farhadi Kangarlu, Student Member, IEEE, S. H. Hosseini, Member, IEEE, E. Babaei, A. Khoshkbar Sadigh
Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz 51664, Iran
Email: Farhadi87@ms.tabrizu.ac.ir, hosseini@tabrizu.ac.ir, e-babaei@tabrizu.ac.ir, a.khoshkbar.sadigh@gmail.com

Abstract- In this paper, a transformerless dynamic voltage

restorer (DVR) based on the multilevel inverter is proposed. This
multilevel inverter uses reduced number of switches. As a result,
the proposed DVR has lower number of switches in comparison
with other multilevel inverter based DVR topologies. Also, it has
lower loss and cost due to no need for injection transformers. As
simulation results using PSCAD software will show, the proposed
DVR can compensate for voltage sags, swells and flickers.

Different topologies and control strategies have been

presented for DVR in the literature [11],[12]. The inverter
used in the DVR structure also has many different topologies.
The two-level PWM inverter is the dominant type of the
inverters used in a DVR. On the other hand, the multilevel
inverters have good harmonic characteristic and can operate in
higher voltage levels. Therefore, application of these types of
inverters in DVR structures has been highlighted over last
years. In [13] a high voltage DVR based on the cascade Hbridge inverters has been studied. In [14] a DVR based on the
multilevel inverter for extremely distorted source has been
presented. In [6] transformer coupled H-bridge inverters have
been used in the DVR structure. This topology requires only
one independent dc source in the cost of a transformer for
each H-bridge inverter. In [15] and [16] DVRs based on the
flying capacitor and diode-clamped multilevel inverter have
been presented, respectively. In [17] a DVR based on the
stacked multicell converter has been presented.
The main disadvantage of the above-mentioned DVR
topologies is high number of switches. Higher number of
switches results in higher cost, higher losses and more
complicated control system requirement.
In this paper, a transformerless DVR based on the
multilevel inverter is proposed. The employed multilevel
inverter uses reduced number of switches in comparison with
other multilevel inverter topologies. Firstly power circuit
configuration of the proposed DVR is presented, and then the
control strategy is described. Finally, simulation results using
PSCAD/EMTDC software will be presented to verify the
ability of the proposed DVR in voltage restoration.

Keywords: voltage sags/swells, DVR, multilevel inverter.

I.

INTRODUCTION

Voltage magnitude, waveform, and frequency are the major

factors that dictate the quality of a power supply [1]. Voltage
disturbance is the common power quality problem in industrial
distribution systems. The voltage disturbance mainly
encompasses voltage sags, voltage swells, voltage harmonics,
voltage flicker and voltage unbalance [2]. Voltage sags are
now one of the most important power quality problems in the
distribution system. A voltage sag is a momentary decrease in
the RMS ac voltage (10%90% of the nominal voltage), at the
power frequency, of duration from 0.5 cycles to a few seconds
[3]. Voltage sags are normally caused by short-circuit faults
such as a single-line-to-ground fault in the power system or by
the starting up of induction motors of large rating [4-6]
Voltage sags may cause the malfunction of voltage-sensitive
loads in factories, buildings, and hospitals [7]. Voltage swell is
defined as a short duration increasing in RMS supply with
increase in voltage ranging from 1.1pu to 1.8pu of nominal
supply [8]. The main causes for voltage swell are switching of
large capacitors or removal of heavy loads [9].
DVR is a power electronic converter-based device, designed
to protect critical loads from supply-side voltage disturbances
[1, 10].
The basic operating principle of a DVR is to inject a voltage
of required magnitude, phase angle and frequency in series
with a distribution feeder to maintain a desired amplitude and
waveform for the load voltage even when the source voltage is
distorted.

978-1-4244-5971-1/10/$26.00 2010 IEEE

II. PROPOSED DVR

Nowadays, multilevel inverters are widely used in power
systems. Improved harmonic characteristics and the ability of
these inverters for handling high voltage and high power are
the major factors for developing of these types of inverters.
Moreover, multilevel inverters have not only low switching
stresses but also high flexibility. There are several topologies

371

Fig. 2 compares the switches number of a conventional

symmetric cascade multilevel inverter and the multilevel
inverter shown in Fig. 1. As Fig. 2 shows, the number of the
switches is considerably reduced using multilevel inverter
shown in Fig. 1.
Fig. 3 shows the proposed DVR topology using the
multilevel inverter presented in Fig. 1. As this figure shows,
the proposed DVR does not use injection transformer and this
is because of the fact that the multilevel inverter with isolated
dc sources has been used to generate the required voltage. The
multilevel inverter is controlled using PWM technique and so
the output voltage of the inverter ( vo ) contains high order
harmonics. To attenuate the high order harmonics a low pass
LC filter is used. The values of filter components are
determined in such a way that the resonant frequency of the
filter components be very higher than fundamental frequency
(e.g. ten times) and also be considerably lower than switching
frequency. This results in an effective attenuation of high
order harmonics and at the same time minimum effect in the
fundamental frequency component. The series filter resistance
refers to the dc resistance of the filter inductance.
It is clear that the proposed DVR can be extended to threephase systems and as a result of independent operation of the
different phases, it can compensate unbalanced voltage sags
and swells as well as balanced.

for multilevel inverters. Three well-known types of the

multilevel inverters are cascade H-bridge multilevel inverters,
flying capacitor multilevel inverters and diode clamped
multilevel inverters. But also some other innovative
topologies have been proposed for multilevel inverters which
use reduced number of switches [14], [18-19].
Fig. 1 shows an n-level inverter with reduced number of
switches. This multilevel inverter topology has been presented
in [19]. However, application of this multilevel inverter for
series voltage compensation (e.g. DVR) has not been studied
yet. Moreover, the fundamental frequency modulation method
that has been applied in [19] is not suitable for DVR
application because of considerable low order harmonic
components in the output voltage. So, this paper highlights the
application of this multilevel inverter in a transformerless
DVR topology and its multicarrier-based modulation
technique. As the figure shows, the multilevel inverter is
composed of (n 1) / 2 cells. Each cell has two switches and
an isolated dc source. Each switch is constructed by an IGBT
with an ant-parallel diode. It is obvious that two switches of a
specified cell cannot be on simultaneously. Otherwise, the dc
source will encounter a short circuit. The inverter produces a
unipolar voltage at its dc bus. In order to change the polarity
of the output voltage in positive and negative half cycles, an
H-bridge inverter is used. It is important to note that though
the switches of this H-bridge must have higher voltage ratings
in comparison with switches of the cells, they operate at
fundamental frequency. Therefore, they do not suffer from
high dv/dt stresses.
The inverter shown in Fig. 1, utilizes (n + 3) IGBTs and
(n 1) / 2 independent dc voltage sources to produce an nlevel output voltage. The dc sources can be provided from the
main grid using isolation transformers or by distributed energy
resources, e.g. photovoltaic and fuel cells.

120

Switch number

100

Conventional cascade symmetric

multilevel inverter

80

60

40

Multilevel inverter shown in Fig .1

20

S5

Vdc

10

20

iS

S8

35

40

45

50

55

ZS

S9
S10
cell 3

S1

S3

Vdc
Vdc

+ vo

Vdc

S (n+ 2)

S4

Cf iC

vS

cell 2

Vdc

30

Figure 2. Switch number versus level number.

S7

Vdc

25

Level number

cell 1

Vdc

15

S6

S5

S7

S9

vC +
S6

Rf
S8

S10

S1

S3

S4

S2

vo +

iL

Lf

if

+
ZL

S2

S ( n + 3)

Vdc

cell (n 1) / 2

S (n + 2)

S ( n + 3)

Figure 3. Proposed DVR circuit configuration.

Figure 1. n-level inverter [19].

372

vL

i f = iL + iC

One of the important problems about DVR is to determine

the compensation range of the DVR. Here the mathematical
approach that presented in [12] is used to determine the
compensation range of the proposed DVR. It is supposed that
all the waveforms are sinusoidal and also the voltage drop on
the filter resistance and inductance is negligible.
Voltage sags and swells are defined as follows [12]:
S=

V L , m VS , m

for sag , + for swell

VL , m

Using (5)-(8) and applying the Laplace transform, the

injected voltage can be expressed as follows:

VC ( s ) =

(1)

In the above-mentioned equation, VL, m and VS , m denote

the source and the load voltages peak values, respectively. In
presence of DVR, VL, m is always constant equal to 1pu.
Considering Fig. 3, in the case of voltage sags, the
following equation can be written:
VL, m = VS , m VC , m + for sag , for swell

(n 1)
Vdc
2

(4)

VS

*
V L* V C +

vo = vC + r f i f + L f

(10)

Kp

+V +
I

Lf S

IL

1
CfS

VC

DVR Model

Figure 4. DVR model and control circuit block diagram.

Considering Fig. 3, the following equations can be written:

(5)

v L = v S + vC

IL

rf

III. CONTROL STRATEGY

dvC
dt

(9)

where, VL* and VS denote the reference load voltage and the
measured source voltage, respectively.
To generate the trigger pulses, the amplitude shifted carrier
PWM technique has been used. In this method, for an n-level
inverter, (n 1) / 2 carrier waveforms and a rectified
sinusoidal waveform as reference waveform, are compared
together to generate the required gate signals. This method is
illustrated in Fig. 5. In this figure, m is the modulation index
and is related to the amount of voltage sags/swells. Also
and o show the phase angle and angular frequency of the
reference waveform respectively.
As mentioned, in this method there are (n 1) / 2 carrier
waveforms. These carriers are shifted along the vertical vector.
The first carrier varies between 0 and 2 /(n 1) , the second
one varies between 2 /(n 1) and 4 /(n 1) . Finally, the last
carrier varies between 1 2 /( n 1) and 1. Fig. 6 shows the
reference and carrier waveforms for a 7-level inverter.

In the above-mentioned equation, n is the level number of

the output voltage of multilevel inverter that is an odd number
greater than or equal to three.
As (4) shows, the voltage sags/swells compensation range
can vary by varying of n and Vdc . As an example, with n = 7
and Vdc = 0.2 pu the voltage sag/swell up to 0.6pu can be
completely compensated.

iC = C f

L f C f s2 + rf C f s + 1

VI ( s )

VC* = VL* VS

(3)

(n 1) Vdc

2
VL , m

L f C f s + rf C f s + 1
(r f + L f s )

(2)

Using (1)-(3), the maximum value of voltage sags/swells

that can be compensated is expressed as follows:
S max =

1
2

Fig. 4 shows the control block diagram of the proposed

DVR. In this figure, VC* is the reference injected voltage. This
voltage is defined as follows:

where, VC , m is the peak value of the injected voltage.

In a multilevel inverter, the maximum possible magnitude
of the output voltage is approximately equal to sum of the dc
voltage of the different cells. A multilevel inverter with
(n 1) / 2 cells can produce maximum output voltage
expressed by the following equation:

VC , m =

(8)

Carrier k th

S ( 2 k + 3)

S (2k + 4)

Comparator

(6)
di f
dt

m sin(ot + )

(7)

k = 1, ..., ( n 1) / 2

Figure 5. Generating the trigger pulses for an n-level inverter using amplitude
shifted carrier PWM technique.

373

reference

1.00

400
200
0
-200
-400

carrier3

0.67

carrier 2

0.33

carrier1

0.00

400
200
0
-200
-400

Figure 6. Reference and carrier waveforms for the 7-level inverter.

IV. SIMULATION RESULTS

In this section the simulation results using PSCAD/EMTDC
are presented to prove the ability of the proposed DVR in
voltage sags/swells and flicker compensation.
For simulation purpose, the 7-level inverter is used. Table I
shows the simulated system parameters. Moreover, the
switching frequency is 2.5 kHz and Vdc is 0.2pu. With this
value of Vdc the DVR can compensate up to 0.6pu voltage
sags/swells.
Fig. 7 shows the results of voltage sags and swells
compensation. As this figure shows, up to 0.045 seconds the
source voltage is in its nominal condition and therefore the
injected voltage is zero. Then from 0.045 seconds to 0.1
seconds 0.5pu voltage sag occurs in the source voltage.
During this time interval, the DVR produces the required
voltage and injects it to the grid to maintain the load voltage in
desired level. From 0.1 seconds to 0.15 seconds, 0.4pu voltage
swell happens. The DVR again produces the necessary voltage
to decrease the load voltage to the desired value. As a result,
the load voltage remains in the pre-specified desired level. The
small transient on the load voltage is as a result of transient
response of the LC filter that has been used at the output of the
inverter. This transient response can be improved using multiloop current and voltage control. The total harmonic distortion
(THD) of the load voltage in the sag and swell condition is
1.24 and 0.85, respectively.
The second case study is about voltage flicker compensation.
Voltage flicker is the variation of rms voltage between two
limits with a low frequency. The voltage flicker can be
considered as continuous sag and swell events and therefore
the DVR can compensate it. Fig. 8 shows the results of
voltage flicker compensation. The source voltage amplitude
varies between 0.5pu and 1.25pu with the frequency of 10Hz.
As the figure shows, the voltage flicker is completely
compensated.

V Sm = 220 2 = 1 pu
f S = 50 Hz

Load

Filter

R L = 20

L f = 1 mH

L L = 40 mH

C f = 40 F

f L = 50 Hz

r f = 0.1

400
200
0
-200
-400

Vi [V]

Vc [V]

VL [V]

0.000

0.040

0.080

0.120

Figure 7. Voltage sag and swell compensation; from top to bottom, source
voltage, DVR output voltage before filtering, filtered injection voltage and
compensated load voltage.

400
200
0
-200
-400
400
200
0
-200
-400
400
200
0
-200
-400
400
200
0
-200
-400

TABLE I
SIMULATED SYSTEM PARAMETERS

Source

400
200
0
-200
-400

Vs [V]

0.000

Vs [V]

Vi [V]

Vc [V]

VL [V]

0.040

0.080

0.120

0.160

Figure 8. Voltage flicker compensation; from top to bottom, source voltage,

DVR output voltage before filtering, filtered injection voltage and
compensated load voltage.

374

V. CONCLUSIONS

[8]

In this paper, a transformerless DVR based on the

multilevel inverter was proposed. As a result of employing
this inverter, the proposed DVR has lower number of switches
in comparison with other multilevel DVR topologies.
Operating principles and the power circuit of the proposed
DVR was explained. The DVR was modeled and also control
and switching strategy was discussed in details. Finally,
simulation results proved the DVR abilities in compensating
voltage sags, swells and flicker.

[9]
[10]

[11]
[12]

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