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Research Article
The Design and Thermal Reliability Analysis of
a High-Efficiency K-Band MMIC Medium-Power Amplifier with
Multiharmonic Matching
Y. Shang,1 H. Xu,1 J. Mo,1 Z. Wang,1 X. Xu,1 Z. Tu,1 X. Zhang,2
H. Zheng,1 W. Chen,1 and F. Yu1
1
School of Aeronautics and Astronautics, Zhejiang University, No. 38 Zheda Road, Hangzhou 310027, China
Hangzhou College of Commerce, Zhejiang Gongshang University, No. 18, Xuezheng Street, Hangzhou 310018, China
1. Introduction
GaAs monolithic microwave integrated circuit (MMIC)
power amplifier (PA) design is a cutting-edge technology,
which is widely used in the fields of communication [13],
point-to-point network [4, 5], phased array radar system [6],
and so forth. The trend of GaAs MMIC PA development
is aiming at small size, high efficiency, and high reliability
[710]. Especially, in the area of space application, due to
the strict limitation of payload power supply and the high
difficulty of payload repairing, the efficiency and reliability
become two of the most important factors which have to be
considered at the beginning of GaAs MMIC PA designs.
Recently, high-efficiency GaAs MMIC medium-power
amplifier design has attracted increasing attentions. The
authors in [11] have introduced a 4-stage broadband PA using
GaAs pHEMT process with 24 dBm 1 dB-compression-point
output power (P-1dB), 15% power added efficiency (PAE), and
3.36 mm2 chip size, over the frequency band from 17 GHz
to 26 GHz. A K-band driver amplifier and a K-band PA are
introduced in [12]. The 6-stage power amplifier delivered
2 20 m
RF_IN
Input
matching
VG
Stage 1
VD
VD
VD
2 50 m
Interstage 1
matching
Stage 2
VG
4 65 m
Interstage 2
matching
Output
matching
Stage 3
RF_OUT
VG
2. PA Circuit Design
The proposed PA is fabricated by using the 0.15 m GaAs
pHEMT technology. The typical parameters of the technology are illustrated in Table 1.
The designed circuit consists of three stages as illustrated
in Figure 1. The first stage is 2 20 m pHEMT structure;
the main purpose of this stage is to provide high linear gain
for the whole circuit. The second stage is 2 50 m pHEMT
structure; it provides enough power to the input of the third
Typical value
1.3 V
16 V
465 mA/mm
620 mA/mm
460 mS/mm
90 GHz
(1)
1
V () D () ,
0 DS
1
= fund + cos ( ) .
2 =2
(2)
out diss in
100%.
DC
(3)
3
350
300
300
50
100 150 200 250 300
Phase (2nd_Harmonic_Freq) (deg.)
PAE (%)
350
41.25
40.88
350
41.70
39.68
37.65
35.63
33.60
31.58
29.55
35.80
0
0
25.50
50
40.15
50
100
39.43
100
150
38.70
150
200
37.98
200
250
37.25
250
36.53
350
27.52
PAE (%)
(a)
(b)
Figure 2: The source (a) and load (b) pull PAE contour of harmonics for the 4 65 m pHEMT.
C2
TLd
TLa
TLb
TLc
C1
28
27
15
20
80Au20Sn
25
Molybdenum copper
Thermal grease
23
30
Test platform
22
35
21
40
45
Au
26
24
25
GaAs
S21 (dB)
10
Layout pattern
24
25
26
27
Frequency (GHz)
28
20
3. Thermal Analysis
4. Discussion
Sim. S22
Meas. S21
Sim. S21
Meas. S11
Sim. S11
Meas. S22
21.5
42.0
21.0
38.0
20.0
PAE (%)
Pout (dBm)
40.0
20.5
36.0
19.5
19.0
24.0
34.0
25.0
26.0
27.0
Frequency (GHz)
Sim. power
Sim. PAE (%)
28.0
32.0
Meas. power
Meas. PAE (%)
107.69
97.354
76.681
66.345
56.009
Temperature ( C)
87.017
45.672
35.336
25.000
97.8573
79.6430
70.5358
61.4286
52.3215
43.2143
Temperature ( C)
88.7501
34.1072
25.0000
Reference
[11]
Process/topology
GaAs pHEMT/4 stages
GaAs pHEMT/4 stages
[12]
GaAs pHEMT/6 stages
[13]
[14]
[15]
This work
Frequency
1726 GHz
1835 GHz
3540 GHz
1736 GHz
3640 GHz
2428 GHz
1735 GHz
2030 GHz
2527 GHz
1 dB
24 dBm
23.5 dBm
22 dBm
23 dBm
22.5 dBm
19.8 dBm
22 dBm
22 dBm
20 dBm
PAE
15%
11%
8%
8%
14%
19.8%
30%
21%
40%
Chip size
4.20 mm 1.80 mm
4.70 mm 1.90 mm
NA
1.44 mm 2.45 mm
1.50 mm 1.00 mm
1.44 mm 2.45 mm
2.20 mm 1.20 mm
5. Conclusion
Competing Interests
The authors declare that they have no competing interests.
Acknowledgments
This work was supported by the National Science Foundation
of China under Grant 61401395 and the Scientific Research
Fund of Zhejiang Provincial Education Department under
Grant Y201533913.
Figure 11: The example GUI window from ICEPAK.
References
output power, the higher output efficiency will lead to a
lower dissipated power on its pHEMT and, further, lead to a
longer device life time. Therefore, the thermal design is one of
important design factors during the PA design. In this
paper, the working temperature range for the proposed PA
is designed between 40 C and 85 C. The final thermal test
result has shown 97.86 C under normal bias condition at
room temperature and the PAE at the same condition is not
7
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