MasterPinout 4x5

TE0710
FPGA PIN
Signal Name
TE0711
FPGA PIN
Signal Name
3.3V FIX
C11
C10
A10
A9
C9
B9
F13
F14
H14
G14
B18
A18
B17
B16
J14
H15
A16
A15
G16
H16
F16
F15
A14
A13
C15
D15
VIN_DCDC
VIN_DCDC
VIN_DCDC
NOSEQ
VCCIO_B15_IN
VCCIO_B15_IN
VIN_3.3
VIN_3.3
B16_L13_P
B16_L13_N
B16_L14_P
B16_L14_N
B16_L11_P
B16_L11_N
GND
B15_L5_P
B15_L5_N
B15_L15_P
B15_L15_N
1.8V_OUT
B15_L10_P
B15_L10_N
B15_L7_N
B15_L7_P
B15_L19_P
B15_L19_N
GND
B15_L8_N
B15_L8_P
B15_L13_N
B15_L13_P
GND
B15_L14_N
B15_L14_P
B15_L9_N
B15_L9_P
GND
B15_L12_N
B15_L12_P
C11
C10
A10
A9
C9
B9
F13
F14
H14
G14
B18
A18
B17
B16
D12
D13
A16
A15
G16
H16
F16
F15
A14
A13
C15
D15
VIN_DCDC
VIN_DCDC
VIN_DCDC
NOSEQ
VCCIO_B15_IN
VCCIO_B15_IN
VIN_3.3
VIN_3.3
B16_L13_P
B16_L13_N
B16_L14_P
B16_L14_N
B16_L11_P
B16_L11_N
GND
B15_L5_P
B15_L5_N
B15_L15_P
B15_L15_N
1.8V_OUT
B15_L10_P
B15_L10_N
B15_L7_N
B15_L7_P
B15_L6_P
B15_L6_N
GND
B15_L8_N
B15_L8_P
B15_L13_N
B15_L13_P
GND
B15_L14_N
B15_L14_P
B15_L9_N
B15_L9_P
GND
B15_L12_N
B15_L12_P
A11
B11
B8
R13
R12
L18
R10
M18
T11
not connected
B15_L4_N
B15_L4_P
B14_IO0(B16)
B14_IO1
JTAGSEL
B14_IO5
B14_IO6
B14_IO2
B14_IO3
B14_IO7
A11
B11
R10
R13
R12
L18
M13
M18
R16
not connected
B15_L4_N
B15_L4_P
B14_IO0
B14_IO1
JTAGSEL
B14_IO5
B14_IO6
B14_IO2
B14_IO3
B14_IO7
E18
D18
J18
J17
G18
F18
C12
B12
K13
J13
K15
J15
E16
GND
ETH_TD_P
ETH_TD_N
GND
ETH_RD_P
ETH_RD_N
3.3V_CTREF
ETH2_TD_P
ETH2_TD_N
GND
ETH2_RD_P
ETH2_RD_N
GND
EN1
PGOOD
MODE
GND
B15_L21_P
B15_L21_N
B15_L23_N
B15_L23_P
GND
B15_L22_P
B15_L22_N
B15_L3_P
B15_L3_N
GND
B15_L17_P
B15_L17_N
B15_L24_P
B15_L24_N
GND
B15_L11_N
L4
K5
N6
M6
T8
R8
L6
L5
E18
D18
J18
J17
G18
F18
J14
H15
K13
J13
K15
J15
E16
GND
B34_L5_N
B34_L5_P
GND
B34_L18_N
B34_L18_P
not connected
B34_L24_N
B34_L24_P
GND
B34_L6_P
B34_L6_N
GND
EN
STAT
MODE
GND
B15_L21_P
B15_L21_N
B15_L23_N
B15_L23_P
GND
B15_L22_P
B15_L22_N
B15_L19_P
B15_L19_N
GND
B15_L17_P
B15_L17_N
B15_L24_P
B15_L24_N
GND
B15_L11_N
E15
H17
G17
E17
D17
C17
C16
D14
C14
A8
B14
B13
D13
D12
B15_L11_P
B15_L18_P
B15_L18_N
GND
B15_L16_P
B15_L16_N
B15_L20_N
B15_L20_P
GND
B15_L1_P
B15_L1_N
GND
B14_IO4(B16)
B15_L2_N
B15_L2_P
B15_L6_N
B15_L6_P
E15
H17
G17
E17
D17
C17
C16
D14
C14
N17
B14
B13
C12
B12
B15_L11_P
B15_L18_P
B15_L18_N
GND
B15_L16_P
B15_L16_N
B15_L20_N
B15_L20_P
GND
B15_L1_P
B15_L1_N
GND
B14_IO4
B15_L2_N
B15_L2_P
B15_L3_P
B15_L3_N
R8
T8
U7
U6
P4
P3
not connected
not connected
not connected
VCCIO_B34_IN
VCCIO_B34_IN
not connected
not connected
not connected
not connected
1.5V_OUT
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
GND
B34_L24_P
B34_L24_N
B34_L22_P
B34_L22_N
GND
B34_L14_P
B34_L14_N
U12
V12
N14
P14
T14
T15
P15
R15
T11
U11
T10
T9
H6
H5
J4
H4
E2
D2
VCCIO_B34_IN
VCCIO_B34_IN
not connected
VCCIO_B35_IN
VCCIO_B35_IN
B14_L20_P
B14_L20_N
B14_L8_P
B14_L8_N
not connected
B14_L14_P
B14_L14_N
B14_L13_P
B14_L13_N
not connected
B14_L19_P
B14_L19_N
B14_L24_N
B14_L24_P
GND
B35_L24_P
B35_L24_N
B35_L21_P
B35_L21_N
GND
B35_L14_P
B35_L14_N
M3
M2
L3
K3
K5
L4
M4
N4
T1
R1
L5
L6
N1
N2
U8
-
B34_L4_P
B34_L4_N
GND
B34_L2_N
B34_L2_P
B34_L5_P
B34_L5_N
GND
B34_L16_P
B34_L16_N
B34_L17_N
B34_L17_P
GND
B34_L6_N
B34_L6_P
B34_L3_N
B34_L3_P
B34_25
JTAG_VREF
TMS
TDI
TDO
TCK
G4
G3
H2
G2
G6
F6
E7
D7
C4
B4
C5
C6
C7
D8
F5
-
B35_L20_P
B35_L20_N
GND
B35_L15_P
B35_L15_N
B35_L19_P
B35_L19_N
GND
B35_L6_P
B35_L6_N
B35_L7_P
B35_L7_N
GND
B35_L1_N
B35_L1_P
B35_L4_N
B35_L4_P
B35_0
JTAG_VREF
TMS
TDI
TDO
TCK
V9
U9
N6
M6
V7
VIN_DCDC
VIN_DCDC
VIN_DCDC
VIN_DCDC
3.3V_OUT
3.3V_OUT
not connected
not connected
nRST
GND
not connected
not connected
not connected
not connected
GND
B34_L21_N
B34_L21_P
B34_L18_N
B34_L18_P
GND
B34_L20_P
V11
V10
N15
N16
M16
M17
E6
E5
K2
K1
J2
VIN_DCDC
VIN_DCDC
VIN_DCDC
VIN_DCDC
3.3V_OUT
3.3V_OUT
B14_L21_N
B14_L21_P
nRST
GND
B14_L11_P
B14_L11_N
B14_L10_P
B14_L10_N
GND
B35_L5_P
B35_L5_N
B35_L23_P
B35_L23_N
GND
B35_L22_N
V6
T5
T4
R3
T3
N5
P5
V5
V4
R7
T6
U4
U3
V1
U1
V2
U2
R2
P2
R6
R5
M1
L1
K6
B34_L20_N
B34_L12_P
B34_L12_N
GND
B34_L11_P
B34_L11_N
B34_L13_P
B34_L13_N
GND
B34_L10_P
B34_L10_N
B34_L23_P
B34_L23_N
GND
B34_L8_P
B34_L8_N
B34_L7_N
B34_L7_P
GND
B34_L9_N
B34_L9_P
B34_L15_N
B34_L15_P
GND
B34_L19_P
B34_L19_N
B34_L1_N
B34_L1_P
B34_0
J3
F4
F3
D5
D4
E3
D3
H1
G1
F1
E1
C1
C2
B1
A1
B2
B3
A3
A4
A5
A6
B6
B7
J5
B35_L22_P
B35_L13_P
B35_L13_N
GND
B35_L11_P
B35_L11_N
B35_L12_P
B35_L12_N
GND
B35_L17_P
B35_L17_N
B35_L18_P
B35_L18_N
GND
B35_L16_N
B35_L16_P
B35_L9_P
B35_L9_N
GND
B35_L10_N
B35_L10_P
B35_L8_N
B35_L8_P
GND
B35_L3_N
B35_L3_P
B35_L2_N
B35_L2_P
B35_25
M4
N4
R6
R5
R7
T6
V9
U9
V5
V4
-
B34_L16_P
B34_L16_N
GND
B34_L19_P
B34_L19_N
GND
B34_L23_P
B34_L23_N
GND
B34_L21_N
B34_L21_P
GND
B34_L10_P
B34_L10_N
GND
N5
P5
K3
L3
V2
U2
M1
L1
B34_L13_P
B34_L13_N
GND
B34_L2_P
B34_L2_N
B34_L9_N
B34_L9_P
GND
OTG-D_P
OTG-D_N
not connected
not connected
not connected
B34_L1_N
B34_L1_P
T3
R3
U7
U6
R2
P2
V7
V6
U4
U3
T5
T4
V1
U1
T1
R1
M3
M2
N2
N1
P4
B34_L11_N
B34_L11_P
GND
B34_L22_P
B34_L22_N
GND
B34_L15_N
B34_L15_P
GND
B34_L20_P
B34_L20_N
GND
B34_L8_P
B34_L8_N
GND
B34_L12_P
B34_L12_N
GND
B34_L7_N
B34_L7_P
B34_L17_N
B34_L17_P
GND
B34_L4_P
B34_L4_N
B34_L3_P
B34_L3_N
not connected
B34_L14_P
P3
L13
K17
K18
L14
M14
F4
spi_ss
spi_io_0
spi_io_1
spi_io_2
spi_io_3
sys_clk
sys_led
L13
K17
K18
L14
M14
P17
A8
B34_L14_N
spi_ss
spi_io_0
spi_io_1
spi_io_2
spi_io_3
sys_clk
sys_led
-
TE0712
FPGA PIN
AA13
AB13
Y12
Y11
AA11
AA10
E22
D22
G22
G21
E21
D21
F18
E18
C22
B22
B21
A21
C18
C19
E19
D19
C15
C14
D17
C17
Signal Name
VIN_DCDC
VIN_DCDC
VIN_DCDC
NOSEQ
VCCIO_B16_IN
VCCIO_B16_IN
VIN_3.3
VIN_3.3
B13_L3_P
B13_L3_N
B13_L11_N
B13_L11_P
B13_L9_N
B13_L9_P
GND
B16_L22_P
B16_L22_N
B16_L24_N
B16_L24_P
1.8V_OUT
B16_L23_P
B16_L23_N
B16_L15_P
B16_L15_N
B16_L20_P
B16_L20_N
GND
B16_L21_P
B16_L21_N
B16_L13_P
B16_L13_N
GND
B16_L14_P
B16_L14_N
B16_L3_N
B16_L3_P
GND
B16_L12_P
B16_L12_N
TE0713
FPGA PIN
N15
N16
M18
L18
M16
M17
J14
H15
H14
G14
B18
A18
B17
B16
D14
C14
A16
A15
G16
H16
F16
F15
A14
A13
C15
D15
Signal Name
VIN_DCDC
VIN_DCDC
VIN_DCDC
NOSEQ
VCCIO_B15_IN
VCCIO_B15_IN
VIN_3.3
VIN_3.3
B14_L11_P
B14_L11_N
B14_L4_N
B14_L4_P
B14_L10_P
B14_L10_N
GND
B15_L19_P
B15_L19_N
B15_L15_P
B15_L15_N
1.8V_OUT
B15_L10_P
B15_L10_N
B15_L7_N
B15_L7_P
B15_L1_P
B15_L1_N
GND
B15_L8_N
B15_L8_P
B15_L13_N
B15_L13_P
GND
B15_L14_N
B15_L14_P
B15_L9_N
B15_L9_P
GND
B15_L12_N
B15_L12_P
TE0715
FPGA PIN
1.8V FIX
3.3V FIX
W12
W13
U11
U12
V15
W15
R17
T17
V13
V14
AB13
AB14
Y15
Y14
AA15
AA14
AB16
AB17
Y19
Y18
B13
C13
U18
U17
Y21
Y22
T21
U21
R17
not connected
B16_L8_N
B16_L8_P
B14_L18_N
B14_L18_P
JTAGSEL
B14_L9_P
B14_L9_N
B14_L4_P
B14_L4_N
B14_L24_N
A11
B11
C11
C10
C9
A9
B9
A8
B8
not connected
B15_L4_N
B15_L4_P
B16_IO0
B16_IO1
JTAGSEL
B16_IO5
B16_IO6
B16_IO2
B16_IO3
B16_IO7
AB18
AB19
Y14
W14
AA14
Y13
B20
A20
C20
D20
A19
A18
F20
F19
A16
A15
B16
B15
B17
GND
ETH_TD_P
ETH_TD_N
GND
ETH_RD_P
ETH_RD_N
3.3V_CTREF
B13_L6_N
B13_L6_P
GND
B13_L5_N
B13_L5_P
GND
EN1
PGOOD
MODE
GND
B16_L16_P
B16_L16_N
B16_L19_N
B16_L19_P
GND
B16_L17_N
B16_L17_P
B16_L18_N
B16_L18_P
GND
B16_L9_N
B16_L9_P
B16_L7_N
B16_L7_P
GND
B16_L11_P
T9
T10
R12
R13
N14
P14
P18
N17
E18
D18
J18
J17
G18
F18
F13
F14
K13
J13
K15
J15
E16
GND
B14_L24_P
B14_L24_N
GND
B14_L5_P
B14_L5_N
3.3V_CTREF
B14_L8_P
B14_L8_N
GND
B14_L9_N
B14_L9_P
GND
EN
STAT
MODE
GND
B15_L21_P
B15_L21_N
B16_L23_N
B15_L23_P
GND
B15_L22_P
B15_L22_N
B15_L5_P
B15_L5_N
GND
B15_L17_P
B15_L17_N
B15_L24_P
B15_L24_N
GND
B15_L11_N
U13
U14
V11
W11
AA11
AB11
AA12
AB12
Y12
Y13
V16
W16
AA17
B18
A14
A13
D16
E16
E17
F16
D15
D14
P16
E14
E13
F14
F13
B16_L11_N
B16_L10_N
B16_L10_P
GND
B16_L5_N
B16_L5_P
B16_L2_N
B16_L2_P
GND
B16_L6_N
B16_L6_P
GND
B14_L24_P
B16_L4_N
B16_L4_P
B16_L1_N
B16_L1_P
E15
H17
G17
E17
D17
C17
C16
C12
B12
A10
B14
B13
D13
D12
B15_L11_P
B15_L18_P
B15_L18_N
GND
B15_L16_P
B15_L16_N
B15_L20_N
B15_L20_P
GND
B15_L3_P
B15_L3_N
GND
B16_IO4
B15_L2_N
B15_L2_P
B15_L6_N
B15_L6_P
AA16
Y17
W17
AA19
AA20
W18
V18
V19
U19
-
AA21
AA20
AB18
AA18
V18
V19
Y18
Y19
V17
W17
AA19
AB20
L16
K16
K13
K14
J20
J21
VCCIO_B13_IN
VCCIO_B13_IN
not connected
VCCIO_B15_IN
VCCIO_B15_IN
B14_L8_N
B14_L8_P
B14_L17_N
B14_L17_P
1.5V_OUT
B14_L14_P
B14_L14_N
B14_L13_P
B14_L13_N
not connected
B14_L16_P
B14_L16_N
B14_L15_P
B14_L15_N
GND
B15_L23_P
B15_L23_N
B15_L19_P
B15_L19_N
GND
B15_L11_P
B15_L11_N
R8
U8
U7
U6
P4
P3
not connected
not connected
not connected
VCCIO_B34_IN
VCCIO_B34_IN
not connected
not connected
not connected
not connected
1.5V_OUT
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
GND
B34_L24_P
B34_L24_N
B34_L22_P
B34_L22_N
GND
B34_L14_P
B34_L14_N
R3
R2
P3
P2
K4
K3
L5
L4
J2
J1
J5
K5
E3
E4
B6
B7
C6
C5
AB21
AB22
U17
U18
J14
H14
N19
N18
M18
L18
H13
G13
G16
G15
G17
G18
H15
J15
J16
-
B15_L3_P
B15_L3_N
GND
B15_L17_N
B15_L17_P
B15_L16_P
B15_L16_N
GND
B15_L1_P
B15_L1_N
B15_L2_N
B15_L2_P
GND
B15_L4_P
B15_L4_N
B15_L5_N
B15_L5_P
B15_IO0
JTAG_VREF
TMS
TDI
TDO
TCK
M3
M2
L3
K3
K5
L4
M4
N4
T1
R1
L5
L6
N1
N2
U8
-
AB22
AB21
W19
W20
U20
V20
K22
K21
G20
H20
H22
VIN_DCDC
VIN_DCDC
VIN_DCDC
VIN_DCDC
3.3V_OUT
3.3V_OUT
B14_L10_N
B14_L10_P
nRST
GND
B14_L12_P
B14_L12_N
B14_L11_P
B14_L11_N
GND
B15_L9_N
B15_L9_P
B15_L8_N
B15_L8_P
GND
B15_L7_N
V9
U9
R7
T6
V7
B34_L4_P
B34_L4_N
GND
B34_L2_N
B34_L2_P
B34_L5_P
B34_L5_N
GND
B34_L16_P
B34_L16_N
B34_L17_N
B34_L17_P
GND
B34_L6_N
B34_L6_P
B34_L3_N
B34_L3_P
B34_IO25
JTAG_VREF
TMS
TDI
TDO
TCK
VIN_DCDC
VIN_DCDC
VIN_DCDC
VIN_DCDC
3.3V_OUT
3.3V_OUT
not connected
not connected
nRST
GND
not connected
not connected
not connected
not connected
GND
B34_L21_N
B34_L21_P
B34_L23_P
B34_L23_N
GND
B34_L20_P
E7
F7
D8
E8
C8
B8
G7
G8
H3
H4
E5
F5
F6
G6
H6
-
M1
M2
J7
J6
M7
M8
D1
C1
B1
B2
A1
J22
K18
K19
L19
L20
J19
H19
L21
M21
N20
M20
M13
L13
N22
M22
H18
H17
K17
J17
M16
M15
L15
L14
M17
B15_L7_P
B15_L13_P
B15_L13_N
GND
B15_L14_P
B15_L14_N
B15_L12_P
B15_L12_N
GND
B15_L10_N
B15_L10_P
B15_L18_P
B15_L18_N
GND
B15_L20_P
B15_L20_N
B15_L15_P
B15_L15_N
GND
B15_L6_N
B15_L6_P
B15_L21_P
B15_L21_N
GND
B15_L24_N
B15_L24_P
B15_L22_N
B15_L22_P
B15_IO25
T16
U16
A4
B4
C5
D5
A6
B6
C7
D7
-
B13_L17_P
B13_L17_N
GND
MGT_TX0_N
MGT_TX0_P
GND
MGT_TX1_N
MGT_TX1_P
GND
MGT_TX2_N
MGT_TX2_P
GND
MGT_TX3_N
MGT_TX3_P
GND
V6
T5
T4
R3
T3
N5
P5
V5
V4
N6
M6
U4
U3
V1
U1
V2
U2
R2
P2
R6
R5
M1
L1
K6
B34_L20_N
B34_L12_P
B34_L12_N
GND
B34_L11_P
B34_L11_N
B34_L13_P
B34_L13_N
GND
B34_L10_P
B34_L10_N
B34_L18_N
B34_L18_P
GND
B34_L8_P
B34_L8_N
B34_L7_N
B34_L7_P
GND
B34_L9_N
B34_L9_P
B34_L15_N
B34_L15_P
GND
B34_L19_P
B34_L19_N
B34_L1_N
B34_L1_P
B34_IO0
A2
B4
B3
D3
C3
D5
C4
F1
F2
D6
D7
E2
D2
H1
G1
A6
A7
G2
G3
A4
A5
F4
G4
H5
AB3
AA3
Y4
W4
AB5
AA5
Y2
W2
-
E10
F10
V10
W10
T14
T15
P19
R19
R18
T18
V13
V14
MGT_CLK1_N
MGT_CLK1_P
GND
B13_L10_P
B13_L10_N
B13_L15_P
B13_L15_N
GND
B14_L5_P
B14_L5_N
B14_L20_P
B14_L20_N
not connected
B13_L13_P
B13_L13_N
V9
U9
P6
P5
N4
N3
T2
T1
U15
V15
A8
B8
C11
D11
A10
B10
C9
D9
W15
W16
Y16
AA16
AA15
AB15
AB17
AB16
W11
B13_L14_P
B13_L14_N
GND
MGT_RX0_N
MGT_RX0_P
GND
MGT_RX1_N
MGT_RX1_P
GND
MGT_RX2_N
MGT_RX2_P
GND
MGT_RX3_N
MGT_RX3_P
GND
CLKIN2_N
CLKIN2_P
GND
B13_L16_P
B13_L16_N
B13_L1_P
B13_L1_N
GND
B13_L4_P
B13_L4_N
B13_L2_N
B13_L2_P
not connected
B13_L12_P
AB7
AA7
Y8
W8
AB9
AA9
Y6
W6
R5
R4
N1
P1
L2
L1
M4
M3
U2
W12
T19
P22
R22
P21
R21
U22
H4
G4
B13_L12_N
spi_ss_i_0
spi_io0_i
spi_io1_i
spi_io2_i
spi_io3_i
sys_led
sys_diff_clkp
sys_diff_clkn
U1
TE0715
Signal Name
VIN_DCDC
VIN_DCDC
VIN_DCDC
NOSEQ
VCCIO_B13_IN
VCCIO_B13_IN
VIN_3.3
VIN_3.3
MIO45
MIO44
MIO43
MIO42
MIO41
MIO40
GND
B13_L3_P
B13_L3_N
B13_L5_P
B13_L5_N
1.8V_OUT
B13_L2_P
B13_L2_N
B13_L19_P
B13_L19_N
B13_L1_P
B13_L1_N
GND
B13_L9_P
B13_L9_N
B13_L12_N
B13_L12_P
GND
B13_L11_N
B13_L11_P
B13_L17_P
B13_L17_N
GND
B13_L13_N
B13_L13_P
TE0720
FPGA PIN
1.8V FIX
3.3V FIX
C22
D22
G22
H22
B22
B21
A22
A21
G21
G20
D21
E21
B20
B19
C20
D20
G16
G15
C19
D18
Signal Name
VIN_DCDC
VIN_DCDC
VIN_DCDC
NOSEQ
VCCIO_B35_IN
VCCIO_B35_IN
VIN_3.3
VIN_3.3
MIO45
MIO44
MIO43
MIO42
MIO41
MIO40
GND
B35_L16_N
B35_L16_P
B35_L24_N
B35_L24_P
1.8V_OUT
B35_L18_N
B35_L18_P
B35_L15_N
B35_L15_P
B35_L22_N
B35_L22_P
GND
B35_L17_N
B35_L17_P
B35_L13_N
B35_L13_P
GND
B35_L14_N
B35_L14_P
B35_L4_N
B35_L4_P
GND
B35_L12_N
B35_L12_P
TE0741
FPGA PIN
M2
M1
N4
N3
K26
K25
M26
N26
L25
M25
P26
R26
N24
P24
T25
T24
N22
N21
N23
P23
R16
R17
P21
R21
JMx
Signal Name
VIN_DCDC
VIN_DCDC
VIN_DCDC
not connected
VCCIO_B13_IN
VCCIO_B13_IN
VIN_3.3
VIN_3.3
MGT_TX5_P
MGT_TX5_N
GND
GND
MGT_RX5_P
MGT_RX5_N
GND
B13_L1_N
B13_L1_P
B13_L5_N
B13_L5_P
not connected
B13_L3_N
B13_L3_P
B13_L2_N
B13_L2_P
B13_L4_N
B13_L4_P
GND
B13_L15_N
B13_L15_P
B13_L12_N
B13_L12_P
GND
B13_L11_N
B13_L11_P
B13_L21_P
B13_L21_N
GND
B13_L13_N
B13_L13_P
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
VBAT_IN
B13_L16_P
B13_L16_N
MIO15
MIO0
JTAGSEL
MIO9
MIO11
MIO10
MIO13
MIO12
F19
G19
VBAT_IN
B35_L20_N
B35_L20_P
MIO15
MIO0
JTAGSEL
MIO9
MIO11
MIO10
MIO13
MIO12
T17
U17
G24
H21
G21
K21
L22
K22
H23
not connected
B13_L23_N
B13_L23_P
MIO15
MIO0
JTAGSEL
MIO9
MIO11
MIO10
MIO13
MIO12
79
81
83
85
87
89
91
93
95
97
99
GND
PHY_MDI0_P
PHY_MDI0_N
GND
PHY_MDI1_P
PHY_MDI1_N
not connected
PHY_MDI2_P
PHY_MDI2_N
GND
PHY_MDI3_P
PHY_MDI3_N
GND
EN1
PGOOD
MODE
GND
B13_L6_P
B13_L6_N
B13_L4_P
B13_L4_N
GND
B13_L7_P
B13_L7_N
B13_L8_P
B13_L8_N
GND
B13_L10_P
B13_L10_N
B13_L23_P
B13_L23_N
GND
B13_L14_N
A19
A18
A17
A16
B15
C15
D17
D16
B17
B16
E20
E19
C18
GND
PHY_MDI0_P
PHY_MDI0_N
GND
PHY_MDI1_P
PHY_MDI1_N
not connected
PHY_MDI2_P
PHY_MDI2_N
GND
PHY_MDI3_P
PHY_MDI3_N
GND
EN1
PGOOD
MODE
GND
B35_L10_N
B35_L10_P
B35_L9_N
B35_L9_P
GND
B35_L7_N
B35_L7_P
B35_L2_N
B35_L2_P
GND
B35_L8_N
B35_L8_P
B35_L21_N
B35_L21_P
GND
B35_L11_N
H2
H1
J4
J3
K2
K1
L4
L3
P16
N17
L24
M24
M20
N19
M22
M21
P18
R18
M19
N18
R23
GND
MGT_TX7_P
MGT_TX7_N
GND
MGT_RX7_P
MGT_RX7_N
GND
MGT_TX6_P
MGT_TX6_N
GND
MGT_RX6_P
MGT_RX6_N
GND
EN1
PGOOD
MODE
GND
B13_L20_P
B13_L20_N
B13_L8_N
B13_L8_P
GND
B13_L7_N
B13_L7_P
B13_L10_N
B13_L10_P
GND
B13_L24_N
B13_L24_P
B13_L22_N
B13_L22_P
GND
B13_L14_N
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
B13_L14_P
B13_L24_N
B13_L24_P
GND
B13_L18_P
B13_L18_N
B13_L21_N
B13_L21_P
GND
B13_L20_N
B13_L20_P
GND
MIO14
B13_L15_P
B13_L15_N
B13_L22_P
B13_L22_N
C17
F22
F21
E18
F18
D15
E15
F17
G17
E16
F16
H20
H19
B35_L11_P
B35_L23_N
B35_L23_P
GND
B35_L5_N
B35_L5_P
B35_L3_N
B35_L3_P
GND
B35_L6_N
B35_L6_P
GND
MIO14
B35_L1_N
B35_L1_P
B35_L19_N
B35_L19_P
R22
R20
T20
U19
U20
P19
P20
T19
T18
J21
T22
T23
P25
R25
not connected
not connected
VCCIO_B34_IN
VCCIO_B35_IN
VCCIO_B35_IN
B34_L17_P
B34_L17_N
B34_L18_P
B34_L18_N
1.5V_OUT
B34_L11_P
B34_L11_N
B34_L12_P
B34_L12_N
not connected
B34_L8_P
B34_L8_N
B34_L7_P
B34_L7_N
GND
B35_L21_N
B35_L21_P
B35_L8_N
B35_L8_P
GND
B35_L11_P
B35_L11_N
AA22
AB22
AA21
AB21
Y19
AA19
Y18
AA18
V15 / V19
AA17
AB17
AA16
AB16
AA12
AB12
AA11
AB11
AA9
AA8
VCCIO_B34_IN
VCCIO_B34_IN
VCCIO_B33_IN
VCCIO_B13_IN
VCCIO_B13_IN
B33_L7_P
B33_L7_N
B33_L8_P
B33_L8_N
1.5V_OUT
B33_L11_P
B33_L11_N
B33_L12_P
B33_L12_N
B33_VREF
B33_L17_P
B33_L17_N
B33_L18_P
B33_L18_N
GND
B13_L7_P
B13_L7_N
B13_L8_P
B13_L8_N
GND
B13_L11_P
B13_L11_N
G16
H16
J18
J19
G17
F18
F17
E17
J20
L20
L19
L18
M17
U22
V22
U24
U25
AA23
AB24
B13_L14_P
B13_L16_N
B13_L16_P
GND
B13_L18_P
B13_L18_N
B13_L9_P
B13_L9_N
GND
B13_L19_N
B13_L19_P
GND
MIO14
B13_L17_P
B13_L17_N
B13_L6_N
B13_L6_P
VCCIO_B16_IN
VCCIO_B16_IN
VCCIO_B15_IN
VCCIO_B12_IN
VCCIO_B12_IN
B15_L7_N
B15_L7_P
B15_L20_P
B15_L20_N
not connected
B15_L11_P
B15_L11_N
B15_L12_P
B15_L12_N
B15_VREF
B15_L21_N
B15_L21_P
B15_L23_N
B15_L23_P
GND
B12_L1_P
B12_L1_N
B12_L2_P
B12_L2_N
GND
B12_L11_P
B12_L11_N
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
B35_L1_N
B35_L1_P
GND
B35_L3_N
B35_L3_P
B35_L7_P
B35_L7_N
GND
B35_L4_N
B35_L4_P
B35_L19_N
B35_L19_P
GND
B35_L5_N
B35_L5_P
B35_L6_N
B35_L6_P
B35_IO0
JTAG_VREF
TMS
TDI
TDO
TCK
AB10
AB9
T4
U4
AB7
AB6
AB5
AB4
Y4
AA4
AB2
AB1
V5
V4
U7
-
B13_L9_P
B13_L9_N
GND
B13_L20_P
B13_L20_N
B13_L17_P
B13_L17_N
GND
B13_L16_P
B13_L16_N
B13_L18_P
B13_L18_N
GND
B13_L15_P
B13_L15_N
B13_L21_P
B13_L21_N
B13_IO25
JTAG_VREF
TMS
TDI
TDO
TCK
V23
V24
W26
W25
W24
W23
AB26
AC26
AD25
AE25
AD26
AE26
AD24
AD23
U21
-
B12_L3_P
B12_L3_N
GND
B12_L5_N
B12_L5_P
B12_L8_N
B12_L8_P
GND
B12_L9_P
B12_L9_N
B12_L23_P
B12_L23_N
GND
B12_L21_P
B12_L21_N
B12_L16_N
B12_L16_P
B12_IO0
JTAG_VREF
TMS
TDI
TDO
TCK
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
VIN_DCDC
VIN_DCDC
VIN_DCDC
VIN_DCDC
3.3V_OUT
3.3V_OUT
B34_L15_N
B34_L15_P
nRST
GND
B34_L2_P
B34_L2_N
B34_L6_N
B34_L6_P
GND
B35_L16_P
B35_L16_N
B35_L18_N
B35_L18_P
GND
B35_L15_N
W20
W21
W17
W18
W16
Y16
U12
U11
U10
U9
V10
VIN_DCDC
VIN_DCDC
VIN_DCDC
VIN_DCDC
3.3V_OUT
3.3V_OUT
B33_L4_P
B33_L4_N
nRST
GND
B33_L13_P
B33_L13_N
B33_L14_P
B33_L14_N
GND
B13_L5_P
B13_L5_N
B13_L6_P
B13_L6_N
GND
B13_L1_P
C17
C18
E18
D18
H17
H18
W20
Y21
W21
V21
U26
VIN_DCDC
VIN_DCDC
VIN_DCDC
VIN_DCDC
3.3V_OUT
3.3V_OUT
B15_L5_P
B15_L5_N
nRST
GND
B15_L13_P
B15_L13_N
B15_L14_P
B15_L14_N
GND
B12_L15_P
B12_L15_N
B12_L6_N
B12_L6_P
GND
B12_L4_P
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
B35_L15_P
B35_L13_P
B35_L13_N
GND
B35_L14_P
B35_L14_N
B35_L12_P
B35_L12_N
GND
B35_L23_N
B35_L23_P
B35_L2_N
B35_L2_P
GND
B35_L17_P
B35_L17_N
B35_L24_P
B35_L24_N
GND
B35_L9_N
B35_L9_P
B35_L22_N
B35_L22_P
GND
B35_L10_N
B35_L10_P
B35_L20_N
B35_L20_P
B35_IO25
V9
Y9
Y8
AA7
AA6
Y6
Y5
V12
W12
W11
W10
Y11
Y10
V8
W8
V7
W7
W6
W5
R6
T6
U6
U5
R7
B13_L1_N
B13_L12_P
B13_L12_N
GND
B13_L14_P
B13_L14_N
B13_L13_P
B13_L13_N
GND
B13_L4_P
B13_L4_N
B13_L3_P
B13_L3_N
GND
B13_L10_P
B13_L10_N
B13_L2_P
B13_L2_N
GND
B13_L23_P
B13_L23_N
B13_L24_P
B13_L24_N
GND
B13_L19P
B13_L19N
B13_L22_P
B13_L22_N
B13_IO0
V26
Y23
AA24
AC23
AC24
Y22
AA22
Y26
Y25
AA25
AB25
AB22
AC22
AB21
AC21
AE23
AF23
AF24
AF25
AD21
AE21
AE22
AF22
Y20
SGMII_TX_N
SGMII_TX_P
GND
MGT_TX0_N
MGT_TX0_P
GND
MGT_TX1_N
MGT_TX1_P
GND
MGT_TX2_N
MGT_TX2_P
GND
MGT_TX3_N
MGT_TX3_P
GND
J18
K18
J16
J17
L17
M17
N17
N18
-
SGMII_TX_N
SGMII_TX_P
GND
B34_L7P
B34_L7N
GND
B34_L2_P
B34_L2_N
GND
B34_L4_P
B34_L4_N
GND
B34_L5_P
B34_L5_N
GND
P1
P2
F1
F23
D10
D2
B1
B2
A3
A4
-
B12_L4_N
B12_L12_P
B12_L12_N
GND
B12_L14_P
B12_L14_N
B12_L13_P
B12_L13_N
GND
B12_L10_N
B12_L10_P
B12_L7_P
B12_L7_N
GND
B12_L17_P
B12_L17_N
B12_L18_P
B12_L18_N
GND
B12_L22_P
B12_L22_N
B12_L20_P
B12_L20_N
GND
B12_L19_P
B12_L19_N
B12_L24_P
B12_L24_N
B12_IO25
MGT_TX4_N
MGT_TX4_P
GND
MGT_TX0_N
MGT_TX0_P
GND
MGT_TX1_N
MGT_TX1_P
GND
MGT_TX2_N
MGT_TX2_P
GND
MGT_TX3_N
MGT_TX3_P
GND
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
MGT_CLK0_N
MGT_CLK0_P
GND
B34_L20_P
B34_L20_N
B34_L21_P
B34_L21_N
GND
OTG-D_P
OTG-D_N
OTG-ID
VBUS_V_EN
USB-VBUS
B34_L13_P
B34_L13_N
L18
L19
J21
J22
J20
K21
R19
T19
B34_L12_P
B34_L12_N
GND
B34_L8_P
B34_L8_N
B34_L9_P
B34_L9_N
GND
OTG-D_P
OTG-D_N
OTG-ID
VBUS_V_EN
USB-VBUS
B34_L22_P
B34_L22_N
D5
D6
A14
B14
A15
B15
G22
F23
A23
A24
E10
D10
MGT_CLK0_N
MGT_CLK0_P
GND
B16_L21_N
B16_L21_P
B16_L23_N
B16_L23_P
GND
B14_L13_P
B14_L13_N
B14_L4_P
B14_L4_N
not connected
B16_L12_P
B16_L12_N
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
SGMII_RX_N
SGMII_RX_P
GND
MGT_RX0_N
MGT_RX0_P
GND
MGT_RX1_N
MGT_RX1_P
GND
MGT_RX2_N
MGT_RX2_P
GND
MGT_RX3_N
MGT_RX3_P
GND
CLKIN2_P
CLKIN2_N
GND
B34_L23_P
B34_L23_N
B34_L16_P
B34_L16_N
GND
B34_L10_P
B34_L10_N
B34_L22_P
B34_L22_N
not connected
B34_L14_P
J15
K15
P20
P21
P17
P18
L21
L22
M19
M20
T16
T17
M21
M22
R20
R21
R18
T18
M16 / P15
N19
SGMII_RX_N
SGMII_RX_P
GND
B34_L1_P
B34_L1_N
GND
B34_L18_P
B34_L18_N
GND
B34_L20_P
B34_L20_N
GND
B34_L10_P
B34_L10_N
GND
B34_L13_P
B34_L13_N
GND
B34_L21_P
B34_L21_N
B34_L15_P
B34_L15_N
GND
B34_L17_P
B34_L17_N
B34_L23_P
B34_L23_N
B34_VREF
B34_L14_P
R3
R4
G3
G4
E3
E4
C3
C4
B5
B6
H5
H6
G11
F10
E11
D11
E12
E13
D13
D14
H11 / C13
C12
MGT_RX4_N
MGT_RX4_P
GND
MGT_RX0_N
MGT_RX0_P
GND
MGT_RX1_N
MGT_RX1_P
GND
MGT_RX2_N
MGT_RX2_P
GND
MGT_RX3_N
MGT_RX3_P
GND
MGT_CLK2_N
MGT_CLK2_P
GND
B16_L11_P
B16_L11_N
B16_L14_P
B16_L14_N
GND
B16_L18_N
B16_L18_P
B16_L17_N
B16_L17_P
B16_VREF
B16_L13_P
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
B34_L14_N
N20
B34_L14_N
C11
C23
B24
A25
B22
A22
sys_clk_p
sys_clk_n
D26
F22
E23
B16_L13_N
spi_ss_i_0
spi_io0_i
spi_io1_i
spi_io2_i
spi_io3_i
sys_led
sys_diff_clkp
sys_diff_clkn
60
Jxx JBx TE0701-0x
TE0703
1.8V FIX
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
5.0V
5.0V
5.0V
CPLD 21
J21 VCC SELECT 2V5 / 3V3 / FMC vadj
J21 VCC SELECT 2V5 / 3V3 / FMC vadj
3.3V
3.3V
SD_DAT3
SD_DAT2
SD_DAT1
SD_DAT0
SD_CMD
SD_CLK
GND
J15_3_NTRST
J15_5_TDI
J15_7_TMS
J15_9_TCK
VCCIO_SDCARD_1V8
J15_11_RTCK
J15_13_TDO
FMC_LA5_N
FMC_LA5_P
FMC_LA6_N
FMC_LA6_P
GND
FMC_LA4_N
FMC_LA4_P
FMC_CLK0_N
FMC_CLK0_P
GND
FMC_LA1_N
FMC_LA1_P
FMC_LA3_N
FMC_LA3_P
GND
FMC_LA0_N
FMC_LA0_P
3.3V
3.3V
3.3V
SC
J1_B1
J1_B1
3.3V
3.3V
SD_DAT3
SD_DAT2
SD_DAT1
SD_DAT0
SD_CMD
SD_CLK
GND
J1_A19
J1_A18
J1_C17
J1_C16
VCCIO_SDCARD_1V8
J1_B16
J1_B15
J1_C15
J1_C14
J1_B14
J1_B13
GND
J1_A13
J1_A12
J1_A11
J1_A10
GND
J1_A9
J1_A8
J1_C9
J1_C8
GND
J1_A7
J1_A6
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
80
82
84
86
88
90
92
94
96
98
100
VBAT
FMC_LA2_N
FMC_LA2_P
PMOD J1_4 /
PMOD J1_1 /
GND
PMOD J1_2
PMOD J1_9 /
PMOD J1_8 /
PMOD J1_7 /
PMOD J1_10
J7_VBAT
J1_C7
J1_C6
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
GND
ETH_MDI0_P
ETH_MDI0_N
GND
ETH_MDI1_P
ETH_MDI1_N
not connected
ETH_MDI2_P
ETH_MDI2_N
GND
ETH_MDI3_P
ETH_MDI3_N
GND
CPLD 24
CPLD 25
CPLD 27
GND
FMC_LA15_N
FMC_LA15_P
FMC_LA16_N
FMC_LA16_P
GND
FMC_LA14_N
FMC_LA14_P
FMC_LA13_N
FMC_LA13_P
GND
FMC_LA11_N
FMC_LA11_P
FMC_LA12_N
FMC_LA12_P
GND
FMC_CLK1_P
CPLD 18
Switch S3D
SC_JTAGSEL
CPLD 19
CPLD 29
CPLD 30
/ CPLD 36
J1_A2
J1_A1
GND
ETH_MDI0_P
ETH_MDI0_N
GND
ETH_MDI1_P
ETH_MDI1_N
ETH_CTREF
ETH_MDI2_P
ETH_MDI2_N
GND
ETH_MDI3_P
ETH_MDI3_N
GND
J1_B18
J1_B17
J1_A17
J1_A16
GND
J1_A15
J1_A14
J1_C13
J1_C12
GND
J1_C13
J1_C12
J1_C11
J1_C10
GND
J1_B10
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
Jx1
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
FMC_CLK1_N
FMC_LA10_N
FMC_LA10_P
GND
FMC_LA9_N
FMC_LA9_P
FMC_LA7_N
FMC_LA7_P
GND
FMC_VREF
CPLD 63
GND
PMOD J1_3 / CPLD 37
FMC_LA8_N
FMC_LA8_P
FMC_VREF
J15_15_SRST
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
J17 VCC SELECT

J17 VCC SELECT
J17 VCC SELECT
J21 VCC SELECT
J21 VCC SELECT
J3_n_CL_TC_P
J3_n_CL_TC_N
J3_n_CL_TFG_P
J3_n_CL_TFG_N
not connected
PMOD J5_9
PMOD J5_10
PMOD J5_3
PMOD J5_4
not connected
HDMI_INT
HDMI_CT_HPD
HDMI_LS_OE
HDMI_CEC_CLK
GND
CPLD 75
CPLD 66
FMC_LA20_P
FMC_LA20_N
GND
FMC_LA18_P
FMC_LA18_N
2V5
2V5
2V5
2V5
2V5
J1_B9
J1_B8
J1_B7
GND
J1_B6
J1_B5
J1_C5
J1_C4
GND
J1_B4
J1_B3
GND
J1_C3
J1_C2
J1_A5
J1_A4
/
/
/
/
/
3V3
3V3
3V3
3V3 / FMC vadj
3V3 / FMC vadj
J1_B32
J1_B32
J2_B32
J2_B1
J2_B1
J2_A25
J2_A24
J2_B24
J2_B23
not connected
J2_A23
J2_A22
J2_C23
J2_C22
not connected
J2_C21
J2_C20
J2_C19
J2_C18
GND
J2_C17
J2_C16
J2_C15
J2_C14
GND
J2_C13
J2_C12
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
FMC_LA23_P
FMC_LA23_N
GND
FMC_LA19_P
FMC_LA19_N
FMC_LA22_P
FMC_LA22_N
GND
FMC_LA27_P
FMC_LA27_N
FMC_LA26_P
FMC_LA26_N
GND
FMC_LA21_P
FMC_LA21_N
FMC_LA25_P
FMC_LA25_N
CPLD 67
JTAG_VREF
CPLD 85
CPLD 84
CPLD 83
CPLD 81
J2_C11
J2_C10
GND
J2_C9
J2_C8
J2_C7
J2_C6
GND
J2_C5
J2_C4
J2_A5
J2_A4
GND
J2_C3
J2_C2
J2_B4
J2_B3
GLED
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
5.0V
5.0V
5.0V
5.0V
3.3V_OUT
3.3V_OUT
HDMI_SCL
HDMI_SDA
CPLD 13
GND
PMOD J5_8
PMOD J5_7
PMOD J5_2
PMOD J5_1
GND
PMOD J6_4
PMOD J6_3
CPLD 71
FMC_VREF
GND
PMOD J6_10
3.3V
3.3V
3.3V
3.3V
J2_C32
J2_C32
J2_B22
J2_B21
TMS
TDI
TDO
TCK
GND
J2_A21
J2_A20
J2_B20
J2_B19
GND
J2_A19
J2_A18
J2_B18
J2_B17
GND
J2_A17
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
Jx2
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
PMOD J6_9
PMOD J6_8
PMOD J6_7
GND
PMOD J6_1
PMOD J6_2
FMC_LA17_P
FMC_LA17_N
GND
FMC_LA32_N
FMC_LA32_P
FMC_LA33_N
FMC_LA33_P
GND
FMC_LA30_N
FMC_LA30_P
FMC_LA31_N
FMC_LA31_P
GND
FMC_LA28_N
FMC_LA28_P
FMC_LA29_N
FMC_LA29_P
GND
CPLD 70
FMC_VREF
FMC_LA24_N
FMC_LA24_P
CPLD 74
J2_A16
J2_B16
J2_B15
GND
J2_A15
J2_A14
J2_B14
J2_B13
GND
J2_A13
J2_A12
J2_B12
J2_B11
GND
J2_A11
J2_A10
J2_B10
J2_B9
GND
J2_A9
J2_A8
J2_B8
J2_B7
GND
J2_A7
J2_A6
J2_B6
J2_B5
RLED
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
not connected
not connected
GND
J3_n_CL_CC4_N
J3_n_CL_CC4_P
GND
J3_n_CL_CC3_N
J3_n_CL_CC3_P
GND
J3_n_CL_CC2_N
J3_n_CL_CC2_P
GND
J3_n_CL_CC1_N
J3_n_CL_CC1_P
GND
not connected
not connected
GND
J1_B22
J1_B21
GND
J1_C21
J1_c20
GND
J1_B20
J1_B19
GND
J1_A23
J1_A22
GND
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
not connected
not connected
GND
HDMI_D11
HDMI_D9
HDMI_D7
HDMI_D5
GND
USB_DP
USB_DN
OTG_ID
USB_VBUS_EN
USB_VBUS
HDMI_HS
HDMI_VS
J1_A21
J1_A20
GND
J1_C19
J1_C18
J1_C24
J1_C25
GND
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
Jx3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
not connected
not connected
GND
J3_n_CL_X3_P
J3_n_CL_X3_N
GND
J3_n_CL_X2_P
J3_n_CL_X2_N
GND
J3_n_CL_X1_P
J3_n_CL_X1_N
GND
J3_n_CL_X0_P
J3_n_CL_X0_N
GND
J3_n_CL_CLK_P
J3_n_CL_CLK_N
GND
HDMI_D10
HDMI_D8
HDMI_D6
HDMI_D4
GND
HDMI_D3
HDMI_D2
HDMI_D1
HDMI_D0
GND
HDMI_DE
not connected
not connected
GND
J1_B23
J1_B24
GND
J1_A24
J1_A25
GND
J1_B25
J1_B26
GND
J1_A26
J1_A27
GND
J1_B27
J1_B28
GND
J1_A28
J1_A29
J1_B29
J1_B30
GND
J1_A30
J1_A31
J1_C26
J1_C27
GND
J1_C28
J1_C22
J1_C23
Jx3 59
HDMI_CLK
J1_C29
TE0705
TE0706
5.0V
3.3V
5.0V
3.3V
5.0V
3.3V
NOSEQ
NOSEQ
J21 VCC SELECT 3V3/FMCVCCIO35
J21 VCC SELECT 3V3/FMCVCCIO35
3.3V
3.3V
3.3V
3.3V
SD_DAT3
SD_DAT3
SD_DAT2
SD_DAT2
SD_DAT1
SD_DAT1
SD_DAT0
SD_DAT0
SD_CMD
SD_CMD
SD_CLK
SD_CLK
GND
GND
X0
J6_B30
X1
J6_B29
X2
J6_A29
X3
J6_A28
VIOB
M1.8VOUT
IOA13
J6_C29
IOA1
J6_C28
IOA12
J6_A27
IOB16
J6_A26
IOB15
J5_47
IOB14
J5_48
GND
GND
IOB13
J5_43
IOB12
J5_44
not connected
J5_41
not connected
J5_42
GND
GND
not connected
J5_39
not connected
J5_40
IOB2
J5_37
X4
J5_38
GND
GND
not connected
J5_35
not connected
J5_36
TEB0710
not connected
X5
X6
MIO15
MIO0
JTAGMODE
MIO9
MIO11
MIO10
MIO13
MIO12
J9_VBAT
J5_33
J5_34
J5_31
J5_29
PROGMODE
J5_30
J5_27
J5_28
J5_25
J5_26
GND
PHY_MDI0_P
PHY_MDI0_N
GND
PHY_MDI1_P
PHY_MDI1_N
not connected
PHY_MDI2_P
PHY_MDI2_N
GND
PHY_MDI3_P
PHY_MDI3_N
GND
EN1
PGOOD
MODE
GND
IOA11
IOA10
IOB11
IOB10
GND
IOA9
IOA8
IOB9
IOB8
GND
IOA7
IOA6
IOB7
IOB6
GND
not connected
GND
ETH_MDI0_P
ETH_MDI0_N
GND
ETH_MDI1_P
ETH_MDI1_N
ETH_CTREF
ETH_MDI2_P
ETH_MDI2_N
GND
ETH_MDI3_P
ETH_MDI3_N
GND
EN1
PGOOD
MODE
GND
J6_A25
J6_A24
J6_A23
J6_A22
GND
J6_A21
J6_A20
J6_B28
J6_B27
GND
J6_C27
J6_C26
J6_B26
J6_B25
GND
J6_C25
GND
GND
ETH_CTREF
GND
GND
GND
GND
GND
GND
not connected
IOA5
IOA4
GND
IOB5
IOB4
IOB3
IOA3
GND
IOA2
GND
MIO14
IOB0
IOB1
not connected
IOA0
J21 VCC SELECT
J21 VCC SELECT
J21 VCC SELECT
J21 VCC SELECT
J21 VCC SELECT
IOB17
IOA14
IOA15
IOB18
not connected
PA3_P
PA3_N
PA2_P
PA2_N
not connected
IOA16
IOB28
IOA17
IOB24
GND
IOB25
IOB19
IOA24
IOA18
GND
IOA19
IOA25
J6_C24
J6_B24
J6_B23
GND
J6_C23
J6_C22
J6_B22
J6_B21
GND
J6_C21
J6_C20
GND
J5_32
J6_B20
J6_B19
J6_C19
J6_C18
3V3/FMC1.8V
3V3/FMC1.8V
3V3/FMCVCCIO33
3V3/FMCVCCIO13
3V3/FMCVCCIO13
J5_22
J5_21
J5_20
J5_19
not connected
J5_18
J5_17
J5_16
J5_15
GND
J5_14
J5_13
J5_12
J5_11
GND
J6_C17
J6_C16
J6_C15
J6_C14
GND
J6_C13
J6_C12
GND
GND
GND
GND
GND
IOB21
IOB22
GND
IOA22
IOA20
IOA21
IOB20
GND
IOB23
IOA23
Y0
Y1
GND
Y2
Y3
Y4
Y5
Y6
VCCJTAG
TMS_B
TDI_B
TDO_B
TCK_B
J6_C11
J6_C10
GND
J6_C9
J6_C8
J6_C7
J6_C6
GND
J6_C5
J6_C4
J6_A5
J6_A4
GND
J6_B4
J6_B3
J6_C3
J6_C2
ETH_LED1
VCCJTAG
TMS_B
TDI_B
TDO_B
TCK_B
5.0V
5.0V
5.0V
5.0V
3.3VOUT
3.3VOUT
not connected
not connected
RESIN
GND
PA0_N
PA0_P
PA1_N
PA1_P
GND
PB0_P
PB0_N
IOB26
not connected
GND
PB1_P
3.3V
3.3V
3.3V
3.3V
3.3VOUT
3.3VOUT
J5_10
J5_9
GND
J5_8
J5_7
J5_4
J5_3
GND
J6_A19
J6_A18
J6_B18
J6_B17
GND
J6_A17
GND
GND
GND
GND
PB1_N
PB3_P
PB3_N
GND
PB2_N
PB2_P
IOB34
IOB35
GND
IOA34
IOA35
IOB33
IOA32
GND
IOA33
IOB32
IOB31
IOA31
GND
IOA30
IOB30
IOA29
IOA28
GND
IOB29
IOA27
IOB27
IOA26
J6_A16
J6_B16
J6_B15
GND
J6_A15
J6_A14
J6_B14
J6_B13
GND
J6_A13
J6_A12
J6_B12
J6_B11
GND
J6_A11
J6_A10
J6_B10
J6_B9
GND
J6_A9
J6_A8
J6_B8
J6_B7
GND
J6_A7
J6_A6
J6_B6
J6_B5
ETH_LED2
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
not connected
not connected
GND
OTG-D_P
OTG-D_N
OTG-ID
VBUS_V_EN
USB-VBUS
not connected
not connected
CLK125
not connected
GND
ETH-TXD3
ETH-TXD2
ETH-TXD1
ETH-TXD0
GND
USB_DP
USB_DN
OTG_ID
USB_VBUS_EN
USB_VBUS
ETH_RXCK
CONFIG
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
IOC0
IOC1
GND
IOC2
IOC3
IOC4
IOC5
GND
IOC6
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
not connected
not connected
GND
ETH-RXCK
PHY_INT
GND
ETH-RXD3
ETH-RXD2
ETH-RXD1
ETH-RXD0
GND
ETH-RXCTL
ETH-MDC
ETH-MDIO
ETH-RST
GND
ETH-TXCK
IOC7
ETH-TXCTL
Function
Special Notes
HDMI Output
J3 as Cameralink Output
J3 as Cameralink Input
J3 as GTP/GTX
J3 as PL I/O
USB UART mini USB
USB JTAG (FTDI) mini USB
SD Card (on-board slot)
J1 PMOD
J5 PMOD
J6 PMOD
J14 as GbE Ethernet
J14 as 10/100MBit Ethernet
Micro USB
J3 as CL Frame Graber
CL_X0_P
CL_X0_N
CL_X1_P
CL_X1_N
CL_X2_P
CL_X2_N
CL_CLK_P
CL_CLK_N
CL_X3_P
CL_X3_N
CL_TC_N
CL_TC_P
CL_TFG_P
CL_TFG_N
CL_CC1_N
CL_CC1_P
CL_CC2_P
CL_CC2_N
CL_CC3_N
CL_CC3_P
J3 #
12
25
11
24
10
23
9
22
8
21
7
20
6
19
18
5
17
4
16
3
CL_CC4_P
CL_CC4_N
GND
GND
J3 as CL Camera
CL_CC4_P
CL_CC4_N
CL_CC3_N
CL_CC3_P
CL_CC2_P
CL_CC2_N
CL_CC1_N
CL_CC1_P
CL_TFG_N
CL_TFG_P
CL_TC_P
CL_TC_N
CL_X3_P
CL_X3_N
CL_CLK_P
CL_CLK_N
CL_X2_P
CL_X2_N
CL_X1_P
CL_X1_N
CL_X0_P
CL_X0_N
GND
GND
HDMI
HDMI_D0
HDMI_D1
HDMI_D2
HDMI_D3
HDMI_D4
HDMI_D5
HDMI_D6
HDMI_D7
HDMI_D8
HDMI_D9
HDMI_D10
HDMI_D11
15
2
13
14
1
26
J3 #
12
25
11
24
10
23
9
22
8
21
7
20
6
19
18
5
17
4
16
3
15
2
13
14
1
26
HDMI_CLK
HDMI_DE
HDMI_VS
HDMI_HS
TE0720
TE071-15
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes, Zynq bootable
MIO
PL
PL
Yes, PS ETH0
Yes
PS USB0
No
No
Yes
Yes
Yes
Yes
Yes, Zynq bootable
MIO
PL
PL
Yes, PS ETH0
Yes
PS USB0
L21_B34_L10P
L22_B35_L11N
P17_B34_L20P
P18_B34_L20N
P20_B34_L18P
P21_B34_L18N
M19_B34_L13P
M20_B34_L13N
J15_B34_L1P
K15_B34_L1N
AA22_B33_L7P
AB22_B33_L7N
AA21_B33_L8P
AB21_B33_L8N
N18_B34_L5
N17_B34_L5
M17_B34_L4
L17_B34_L4
J17_B34_L2
J16_B34_L2
K18_B34_L7
J18_B34_L7
L21_B34_L10P
L22_B35_L11N
P17_B34_L20P
P18_B34_L20N
P20_B34_L18P
P21_B34_L18N
M19_B34_L13P
M20_B34_L13N
J15_B34_L1P
K15_B34_L1N
AA22_B33_L7P
AB22_B33_L7N
AA21_B33_L8P
AB21_B33_L8N
N18_B34_L5
N17_B34_L5
M17_B34_L4
L17_B34_L4
J17_B34_L2
J16_B34_L2
K18_B34_L7
J18_B34_L7
B34_L22_N
B34_L22_P
B34_L10_N
B34_L10_P
B34_L16_N
B34_L21_N
B34_L16_P
B34_L21_P
B34_L23_N
B34_L20_N
B34_L23_P
B34_L20_P
B34_L14_N
B34_L14_P
B34_L13_N
B34_L13_P
TE0715-30
TE0710
PLEASE READ The Usage note for

TE0701 when using TE0715-30, there
are special jumper and CPLD
requirements! Failing to comply may
damage the module. All I/O banks must
be powered from 1.8V!
No
No
No
Yes
Yes
Yes
Yes
Yes, Zynq bootable
MIO
PL
PL
Yes, PS ETH0
Yes
PS USB0
No
No
No
No
No
Yes
Yes
PL
PL
PL
No
Yes*
No
TE0711
TE0712
TE0741
No
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
PL
PL
PL
No
No
FTDI
PL
PL
PL
No
Yes*
PL
No
No
Yes
Yes
Yes
Yes
No
PL
PL
PL
No
No
PL 3.3V*
Index
Name
0 RESET
1 spi_ss
2 spi_io_0
3 spi_io_1
4 spi_io_2
5 spi_io_3
6 sys_clk
7 PHY0_TXD0
8 PHY0_TXD1
9 PHY0_TXD2
10 PHY0_TXD3
11 PHY0_TXEN
12 PHY0_TXCLK
13 PHY0_COL
14 PHY0_RXD0
15 PHY0_RXD1
16 PHY0_RXD2
17 PHY0_RXD3
18 PHY0_RXER
19 PHY0_RXCLK
20 PHY0_CRS
21 PHY0_RXDV
22 PHY0_RESET
23 PHY0_MDIO
24 PHY0_MDC
25 PHY1_TXD0
26 PHY1_TXD1
27 PHY1_TXD2
28 PHY1_TXD3
29 PHY1_TXEN
30 PHY1_TXCLK
31 PHY1_COL
32 PHY1_RXD0
33 PHY1_RXD1
34 PHY1_RXD2
35 PHY1_RXD3
36 PHY1_RXER
37 PHY1_RXCLK
38 PHY1_CRS
39 PHY1_RXDV
40 PHY1_MDIO
41 PHY1_MDC
42 sys_gpio0
iostandard
loc
bank
LVCMOS15
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
SSTL15
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
F5
L13
K17
K18
L14
M14
F4
R16
U18
R18
R17
R15
T14
T9
U12
V12
U13
T15
V11
N15
U11
V10
U14
V14
T13
M13
M16
M17
L16
N16
P17
P14
V17
T16
U17
N17
U16
P15
V16
R11
P18
N14
L15
B35
B14
B14
B14
B14
B14
B35
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
43 sys_gpio1
44 sys_gpio2
45 sys_gpio3
46 sys_gpio4
47 sys_gpio5
48 J1_87
49 J1_91
50 J1_95
51 J1_93
52 J1_99
53 J1_97
54 J1_92
55 J1_85
56 J1_17
57 J1_19
58 J1_21
59 J1_23
60 J1_25
61 J1_27
62 J1_31
63 J1_33
64 J1_35
65 J1_37
66 J1_41
67 J1_43
68 J1_45
69 J1_47
70 J1_49
71 J1_51
72 J1_55
73 J1_57
74 J1_59
75 J1_61
76 J1_65
77 J1_67
78 J1_69
79 J1_71
80 J1_75
81 J1_77
82 J1_81
83 J1_83
84 J1_36
85 J1_38
86 J1_40
87 J1_42
LVCMOS33
LVCMOS15
LVCMOS15
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
D9
G3
J5
T18
D10
R13
R12
R10
L18
T11
M18
A8
B8
C11
C10
A10
A9
C9
B9
F13
F14
H14
G14
B18
A18
B17
B16
J14
H15
A16
A15
G16
H16
F16
F15
A14
A13
C15
D15
A11
B11
E18
D18
J18
J17
B16
B35
B35
B14
B16
B14
B14
B14
B14
B14
B14
B16
B16
B16
B16
B16
B16
B16
B16
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
88 J1_46
89 J1_48
90 J1_50
91 J1_52
92 J1_56
93 J1_58
94 J1_60
95 J1_62
96 J1_66
97 J1_68
98 J1_70
99 J1_72
100 J1_76
101 J1_78
102 J1_80
103 J1_82
104 J1_86
105 J1_88
106 J1_94
107 J1_96
108 J1_98
109 J1_100
110 J2_41
111 J2_43
112 J2_45
113 J2_47
114 J2_51
115 J2_53
116 J2_55
117 J2_57
118 J2_61
119 J2_63
120 J2_65
121 J2_67
122 J2_71
123 J2_73
124 J2_75
125 J2_77
126 J2_81
127 J2_83
128 J2_85
129 J2_87
130 J2_32
131 J2_34
132 J2_36
G18
F18
C12
B12
K13
J13
K15
J15
E16
E15
H17
G17
E17
D17
C17
C16
D14
C14
B14
B13
D13
D12
R8
T8
U7
U6
P4
P3
M3
M2
L3
K3
K5
L4
M4
N4
T1
R1
L5
L6
N1
N2
V9
U9
N6
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
133 J2_38
134 J2_42
135 J2_44
136 J2_46
137 J2_48
138 J2_52
139 J2_54
140 J2_56
141 J2_58
142 J2_62
143 J2_64
144 J2_66
145 J2_68
146 J2_72
147 J2_74
148 J2_76
149 J2_78
150 J2_82
151 J2_84
152 J2_86
153 J2_88
154 J2_92
155 J2_94
156 J2_96
157 J2_98
158 J2_100
159 J2_89
M6
V7
V6
T5
T4
R3
T3
N5
P5
V5
V4
R7
T6
U4
U3
V1
U1
V2
U2
R2
P2
R6
R5
M1
L1
K6
U8
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
87
91
95
93
99
97
92
85
17
19
21
23
25
27
31
33
35
37
41
43
45
47
49
51
55
57
59
61
65
67
69
71
75
77
81
83
36
38
40
42
{1,87,0},
{1,91,1},
{1,95,2},
{1,93,3},
{1,99,4},
{1,97,5},
{1,17,6},
{1,19,7},
{1,21,8},
{1,23,9},
{1,25,10},
{1,27,11},
{1,31,12},
{1,33,13},
{1,35,14},
{1,37,15},
{1,41,16},
{1,43,17},
{1,45,18},
{1,47,19},
{1,49,20},
{1,51,21},
{1,55,22},
{1,57,23},
{1,59,24},
{1,61,25},
{1,65,26},
{1,67,27},
{1,69,28},
{1,71,29},
{1,75,30},
{1,77,31},
{1,81,32},
{1,83,33},
{1,36,34},
{1,38,35},
{1,40,36},
{1,42,37},
0 #define
1 #define
2 #define
3 #define
4 #define
5 #define
PIN_J1_87
PIN_J1_91
PIN_J1_95
PIN_J1_93
PIN_J1_99
PIN_J1_97
0
1
2
3
4
5
6 #define
7 #define
8 #define
9 #define
10 #define
11 #define
12 #define
13 #define
14 #define
15 #define
16 #define
17 #define
18 #define
19 #define
20 #define
21 #define
22 #define
23 #define
24 #define
25 #define
26 #define
27 #define
28 #define
29 #define
30 #define
31 #define
32 #define
33 #define
34 #define
35 #define
36 #define
37 #define
PIN_J1_17
PIN_J1_19
PIN_J1_21
PIN_J1_23
PIN_J1_25
PIN_J1_27
PIN_J1_31
PIN_J1_33
PIN_J1_35
PIN_J1_37
PIN_J1_41
PIN_J1_43
PIN_J1_45
PIN_J1_47
PIN_J1_49
PIN_J1_51
PIN_J1_55
PIN_J1_57
PIN_J1_59
PIN_J1_61
PIN_J1_65
PIN_J1_67
PIN_J1_69
PIN_J1_71
PIN_J1_75
PIN_J1_77
PIN_J1_81
PIN_J1_83
PIN_J1_36
PIN_J1_38
PIN_J1_40
PIN_J1_42
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
46
48
50
52
56
58
60
62
66
68
70
72
76
78
80
82
86
88
94
96
98
100
41
43
45
47
51
53
55
57
61
63
65
67
71
73
75
77
81
83
85
87
32
34
36
{1,46,38},
{1,48,39},
{1,50,40},
{1,52,41},
{1,56,42},
{1,58,43},
{1,60,44},
{1,62,45},
{1,66,46},
{1,68,47},
{1,70,48},
{1,72,49},
{1,76,50},
{1,78,51},
{1,80,52},
{1,82,53},
{1,86,54},
{1,88,55},
{1,94,56},
{1,96,57},
{1,98,58},
{1,100,59
{2,41,60},
{2,43,61},
{2,45,62},
{2,47,63},
{2,51,64},
{2,53,65},
{2,55,66},
{2,57,67},
{2,61,68},
{2,63,69},
{2,65,70},
{2,67,71},
{2,71,72},
{2,73,73},
{2,75,74},
{2,77,75},
{2,81,76},
{2,83,77},
{2,85,78},
{2,87,79},
{2,32,80},
{2,34,81},
{2,36,82},
38 #define
39 #define
40 #define
41 #define
42 #define
43 #define
44 #define
45 #define
46 #define
47 #define
48 #define
49 #define
50 #define
51 #define
52 #define
53 #define
54 #define
55 #define
56 #define
57 #define
58 #define
59 #define
60 #define
61 #define
62 #define
63 #define
64 #define
65 #define
66 #define
67 #define
68 #define
69 #define
70 #define
71 #define
72 #define
73 #define
74 #define
75 #define
76 #define
77 #define
78 #define
79 #define
80 #define
81 #define
82 #define
PIN_J1_46 38
PIN_J1_48 39
PIN_J1_50 40
PIN_J1_52 41
PIN_J1_56 42
PIN_J1_58 43
PIN_J1_60 44
PIN_J1_62 45
PIN_J1_66 46
PIN_J1_68 47
PIN_J1_70 48
PIN_J1_72 49
PIN_J1_76 50
PIN_J1_78 51
PIN_J1_80 52
PIN_J1_82 53
PIN_J1_86 54
PIN_J1_88 55
PIN_J1_94 56
PIN_J1_96 57
PIN_J1_98 58
PIN_J1_100 59
PIN_J2_41 60
PIN_J2_43 61
PIN_J2_45 62
PIN_J2_47 63
PIN_J2_51 64
PIN_J2_53 65
PIN_J2_55 66
PIN_J2_57 67
PIN_J2_61 68
PIN_J2_63 69
PIN_J2_65 70
PIN_J2_67 71
PIN_J2_71 72
PIN_J2_73 73
PIN_J2_75 74
PIN_J2_77 75
PIN_J2_81 76
PIN_J2_83 77
PIN_J2_85 78
PIN_J2_87 79
PIN_J2_32 80
PIN_J2_34 81
PIN_J2_36 82
38
42
44
46
48
52
54
56
58
62
64
66
68
72
74
76
78
82
84
86
88
92
94
96
98
100
89
{2,38,83},
{2,42,84},
{2,44,85},
{2,46,86},
{2,48,87},
{2,52,88},
{2,54,89},
{2,56,90},
{2,58,91},
{2,62,92},
{2,64,93},
{2,66,94},
{2,68,95},
{2,72,96},
{2,74,97},
{2,76,98},
{2,78,99},
{2,82,100
{2,84,101
{2,86,102
{2,88,103
{2,92,104
{2,94,105
{2,96,106
{2,98,107
{2,100,10
{2,89,109
83 #define
84 #define
85 #define
86 #define
87 #define
88 #define
89 #define
90 #define
91 #define
92 #define
93 #define
94 #define
95 #define
96 #define
97 #define
98 #define
99 #define
100 #define
101 #define
102 #define
103 #define
104 #define
105 #define
106 #define
107 #define
108 #define
109 #define
PIN_J2_38 83
PIN_J2_42 84
PIN_J2_44 85
PIN_J2_46 86
PIN_J2_48 87
PIN_J2_52 88
PIN_J2_54 89
PIN_J2_56 90
PIN_J2_58 91
PIN_J2_62 92
PIN_J2_64 93
PIN_J2_66 94
PIN_J2_68 95
PIN_J2_72 96
PIN_J2_74 97
PIN_J2_76 98
PIN_J2_78 99
PIN_J2_82 100
PIN_J2_84 101
PIN_J2_86 102
PIN_J2_88 103
PIN_J2_92 104
PIN_J2_94 105
PIN_J2_96 106
PIN_J2_98 107
PIN_J2_100 108
PIN_J2_89 109
XDC
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
F5 [get_ports RESET]
L13 [get_ports spi_ss]
K17 [get_ports spi_io_0]
L14 [get_ports spi_io_2]
M14 [get_ports spi_io_3]
F4 [get_ports sys_clk]
R16 [get_ports PHY0_TXD0]
U18 [get_ports PHY0_TXD1]
R15 [get_ports PHY0_TXEN]
T14 [get_ports PHY0_TXCLK]
T9 [get_ports PHY0_COL]
U12 [get_ports PHY0_RXD0]
V12 [get_ports PHY0_RXD1]
T15 [get_ports PHY0_RXD3]
V11 [get_ports PHY0_RXER]
N15 [get_ports PHY0_RXCLK]
U11 [get_ports PHY0_CRS]
V10 [get_ports PHY0_RXDV]
U14 [get_ports PHY0_RESET]
V14 [get_ports PHY0_MDIO]
T13 [get_ports PHY0_MDC]
M13 [get_ports PHY1_TXD0]
L16 [get_ports PHY1_TXD3]
N16 [get_ports PHY1_TXEN]
P17 [get_ports PHY1_TXCLK]
P14 [get_ports PHY1_COL]
V17 [get_ports PHY1_RXD0]
T16 [get_ports PHY1_RXD1]
N17 [get_ports PHY1_RXD3]
U16 [get_ports PHY1_RXER]
P15 [get_ports PHY1_RXCLK]
V16 [get_ports PHY1_CRS]
R11 [get_ports PHY1_RXDV]
P18 [get_ports PHY1_MDIO]
N14 [get_ports PHY1_MDC]
L15 [get_ports sys_gpio0]
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
D9 [get_ports sys_gpio1]
G3 [get_ports sys_gpio2]
J5 [get_ports sys_gpio3]
T18 [get_ports sys_gpio4]
D10 [get_ports sys_gpio5]
R13 [get_ports J1_87]
L18 [get_ports J1_93]
T11 [get_ports J1_99]
M18 [get_ports J1_97]
A8 [get_ports J1_92]
B8 [get_ports J1_85]
C11 [get_ports J1_17]
F13 [get_ports J1_31]
H14 [get_ports J1_35]
G14 [get_ports J1_37]
J14 [get_ports J1_49]
D15 [get_ports J1_77]
E18 [get_ports J1_36]
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

K13 [get_ports J1_56]
U7 [get_ports J2_45]
P4 [get_ports J2_51]
N4 [get_ports J2_73]
V9 [get_ports J2_32]
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
part0_pins.xml
<?xml version="1.0" encoding="UTF-8" standalone="no"?><part_info part_name="xc7a100tfgg484<pin index="0" name="RESET" iostandard="LVCMOS15" loc="F5"/>
<pin index="1" name="spi_ss" iostandard="LVCMOS33" loc="L13"/>
<pin index="2" name="spi_io_0" iostandard="LVCMOS33" loc="K17"/>
<pin index="4" name="spi_io_2" iostandard="LVCMOS33" loc="L14"/>
<pin index="5" name="spi_io_3" iostandard="LVCMOS33" loc="M14"/>
<pin index="6" name="sys_clk" iostandard="SSTL15" loc="F4"/>
<pin index="7" name="PHY0_TXD0" iostandard="LVCMOS33" loc="R16"/>
<pin index="8" name="PHY0_TXD1" iostandard="LVCMOS33" loc="U18"/>
<pin index="11" name="PHY0_TXEN" iostandard="LVCMOS33" loc="R15"/>
<pin index="12" name="PHY0_TXCLK" iostandard="LVCMOS33" loc="T14"/>
<pin index="13" name="PHY0_COL" iostandard="LVCMOS33" loc="T9"/>
<pin index="14" name="PHY0_RXD0" iostandard="LVCMOS33" loc="U12"/>
<pin index="15" name="PHY0_RXD1" iostandard="LVCMOS33" loc="V12"/>
<pin index="17" name="PHY0_RXD3" iostandard="LVCMOS33" loc="T15"/>
<pin index="18" name="PHY0_RXER" iostandard="LVCMOS33" loc="V11"/>
<pin index="19" name="PHY0_RXCLK" iostandard="LVCMOS33" loc="N15"/>
<pin index="20" name="PHY0_CRS" iostandard="LVCMOS33" loc="U11"/>
<pin index="21" name="PHY0_RXDV" iostandard="LVCMOS33" loc="V10"/>
<pin index="22" name="PHY0_RESET" iostandard="LVCMOS33" loc="U14"/>
<pin index="23" name="PHY0_MDIO" iostandard="LVCMOS33" loc="V14"/>
<pin index="24" name="PHY0_MDC" iostandard="LVCMOS33" loc="T13"/>
<pin index="25" name="PHY1_TXD0" iostandard="LVCMOS33" loc="M13"/>
<pin index="28" name="PHY1_TXD3" iostandard="LVCMOS33" loc="L16"/>
<pin index="29" name="PHY1_TXEN" iostandard="LVCMOS33" loc="N16"/>
<pin index="30" name="PHY1_TXCLK" iostandard="LVCMOS33" loc="P17"/>
<pin index="31" name="PHY1_COL" iostandard="LVCMOS33" loc="P14"/>
<pin index="32" name="PHY1_RXD0" iostandard="LVCMOS33" loc="V17"/>
<pin index="33" name="PHY1_RXD1" iostandard="LVCMOS33" loc="T16"/>
<pin index="35" name="PHY1_RXD3" iostandard="LVCMOS33" loc="N17"/>
<pin index="36" name="PHY1_RXER" iostandard="LVCMOS33" loc="U16"/>
<pin index="37" name="PHY1_RXCLK" iostandard="LVCMOS33" loc="P15"/>
<pin index="38" name="PHY1_CRS" iostandard="LVCMOS33" loc="V16"/>
<pin index="39" name="PHY1_RXDV" iostandard="LVCMOS33" loc="R11"/>
<pin index="40" name="PHY1_MDIO" iostandard="LVCMOS33" loc="P18"/>
<pin index="41" name="PHY1_MDC" iostandard="LVCMOS33" loc="N14"/>
<pin index="42" name="sys_gpio0" iostandard="LVCMOS33" loc="L15"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="43"
index="44"
index="45"
index="46"
index="47"
index="48"
index="49"
index="50"
index="51"
index="52"
index="53"
index="54"
index="55"
index="56"
index="57"
index="58"
index="59"
index="60"
index="61"
index="62"
index="63"
index="64"
index="65"
index="66"
index="67"
index="68"
index="69"
index="70"
index="71"
index="72"
index="73"
index="74"
index="75"
index="76"
index="77"
index="78"
index="79"
index="80"
index="81"
index="82"
index="83"
index="84"
index="85"
index="86"
index="87"
name="sys_gpio1" iostandard="LVCMOS33" loc="D9"/>

name="sys_gpio2" iostandard="LVCMOS15" loc="G3"/>
name="sys_gpio3" iostandard="LVCMOS15" loc="J5"/>
name="sys_gpio4" iostandard="LVCMOS33" loc="T18"/>
name="sys_gpio5" iostandard="LVCMOS33" loc="D10"/>
name="J1_87" iostandard="LVCMOS33" loc="R13"/>
name="J1_93" iostandard="LVCMOS33" loc="L18"/>
name="J1_99" iostandard="LVCMOS33" loc="T11"/>
name="J1_97" iostandard="LVCMOS33" loc="M18"/>
name="J1_92" iostandard="LVCMOS33" loc="A8"/>
name="J1_85" iostandard="LVCMOS33" loc="B8"/>
name="J1_17" iostandard="LVCMOS33" loc="C11"/>
name="J1_31" loc="F13"/>
name="J1_33" loc="F14"/>
name="J1_35" loc="H14"/>
name="J1_37" loc="G14"/>
name="J1_41" loc="B18"/>
name="J1_43" loc="A18"/>
name="J1_45" loc="B17"/>
name="J1_47" loc="B16"/>
name="J1_49" loc="J14"/>
name="J1_51" loc="H15"/>
name="J1_55" loc="A16"/>
name="J1_57" loc="A15"/>
name="J1_59" loc="G16"/>
name="J1_61" loc="H16"/>
name="J1_65" loc="F16"/>
name="J1_67" loc="F15"/>
name="J1_69" loc="A14"/>
name="J1_71" loc="A13"/>
name="J1_75" loc="C15"/>
name="J1_77" loc="D15"/>
name="J1_81" loc="A11"/>
name="J1_83" loc="B11"/>
name="J1_36" loc="E18"/>
name="J1_38" loc="D18"/>
name="J1_40" loc="J18"/>
name="J1_42" loc="J17"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="88" name="J1_46" loc="G18"/>

index="89" name="J1_48" loc="F18"/>
index="90" name="J1_50" loc="C12"/>
index="91" name="J1_52" loc="B12"/>
index="92" name="J1_56" loc="K13"/>
index="93" name="J1_58" loc="J13"/>
index="95" name="J1_62" loc="J15"/>
index="96" name="J1_66" loc="E16"/>
index="98" name="J1_70" loc="H17"/>
index="100" name="J1_76" loc="E17"/>
index="101" name="J1_78" loc="D17"/>
index="102" name="J1_80" loc="C17"/>
index="103" name="J1_82" loc="C16"/>
index="104" name="J1_86" loc="D14"/>
index="105" name="J1_88" loc="C14"/>
index="106" name="J1_94" loc="B14"/>
index="107" name="J1_96" loc="B13"/>
index="108" name="J1_98" loc="D13"/>
index="109" name="J1_100" loc="D12"/>
index="110" name="J2_41" loc="R8"/>
index="111" name="J2_43" loc="T8"/>
index="112" name="J2_45" loc="U7"/>
index="114" name="J2_51" loc="P4"/>
index="115" name="J2_53" loc="P3"/>
index="116" name="J2_55" loc="M3"/>
index="118" name="J2_61" loc="L3"/>
index="123" name="J2_73" loc="N4"/>
index="124" name="J2_75" loc="T1"/>
index="125" name="J2_77" loc="R1"/>
index="130" name="J2_32" loc="V9"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="133"
index="134"
index="135"
index="136"
index="137"
index="138"
index="139"
index="140"
index="141"
index="142"
index="143"
index="144"
index="145"
index="146"
index="147"
index="148"
index="149"
index="150"
index="151"
index="152"
index="153"
index="154"
index="155"
index="156"
index="157"
index="158"
index="159"
name="J2_38" loc="M6"/>
name="J2_42" loc="V7"/>
name="J2_44" loc="V6"/>
name="J2_46" loc="T5"/>
name="J2_48" loc="T4"/>
name="J2_52" loc="R3"/>
name="J2_54" loc="T3"/>
name="J2_56" loc="N5"/>
name="J2_58" loc="P5"/>
name="J2_62" loc="V5"/>
name="J2_64" loc="V4"/>
name="J2_66" loc="R7"/>
name="J2_68" loc="T6"/>
name="J2_72" loc="U4"/>
name="J2_74" loc="U3"/>
name="J2_76" loc="V1"/>
name="J2_78" loc="U1"/>
name="J2_82" loc="V2"/>
name="J2_84" loc="U2"/>
name="J2_86" loc="R2"/>
name="J2_88" loc="P2"/>
name="J2_92" loc="R6"/>
name="J2_94" loc="R5"/>
name="J2_96" loc="M1"/>
name="J2_98" loc="L1"/>
name="J2_100" loc="K6"/>
name="J2_89" loc="U8"/>
name/first
width
reset
0
16
22
15
23
24
25
15
39
14
40
41
54
55
42
47
48
55
48
53
spi_flash
sys_clock
mii0
mdio_io0
mii1
mdio_io1
uart0
sys_gpio
p0
p0_6bits
p1a
56
28
83
27
84
26
109
25
110
20
129
19
130
30
159
29
p1b
p2a
p2b
<connections>
<connection name="part0_reset" component1="part0" component2="reset">

<connection_map name="part0_reset_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_
</connection>
<connection name="part0_spi_flash" component1="part0" component2="spi_flash">

<connection_map name="part0_spi_flash_1" c1_st_index="1" c1_end_index="5" c2_st_index="0"
</connection>
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">

<connection_map name="part0_sys_clock_1" c1_st_index="6" c1_end_index="6" c2_st_index="0
</connection>
<connection name="part0_mii0" component1="part0" component2="mii0">

<connection_map name="part0_mii0_1" c1_st_index="7" c1_end_index="22" c2_st_index="0" c2
</connection>
<connection name="part0_mdio_io0" component1="part0" component2="mdio_io0">

<connection_map name="part0_mdio_io0_1" c1_st_index="23" c1_end_index="24" c2_st_index=
</connection>
<connection name="part0_mii1" component1="part0" component2="mii1">

<connection_map name="part0_mii1_1" c1_st_index="25" c1_end_index="39" c2_st_index="0" c
</connection>

</connection>
<connection name="part0_uart0" component1="part0" component2="uart0">
<connection_map name="part0_uart0_1" c1_st_index="54" c1_end_index="55" c2_st_index="0"
</connection>
<connection name="part0_sys_gpio" component1="part0" component2="sys_gpio">

<connection_map name="part0_sys_gpio_1" c1_st_index="42" c1_end_index="47" c2_st_index="
</connection>
<connection name="part0_p0" component1="part0" component2="p0">

<connection_map name="part0_p0_1" c1_st_index="48" c1_end_index="55" c2_st_index="0" c2_
</connection>
<connection name="part0_p0_6bits" component1="part0" component2="p0_6bits">

<connection_map name="part0_p0_6bits_1" c1_st_index="48" c1_end_index="53" c2_st_index="
</connection>
<connection name="part0_p1a" component1="part0" component2="p1a">

<connection_map name="part0_p1a_1" c1_st_index="56" c1_end_index="83" c2_st_index="0" c2
</connection>
<connection name="part0_p1b" component1="part0" component2="p1b">

<connection_map name="part0_p1b_1" c1_st_index="84" c1_end_index="109" c2_st_index="0" c
</connection>

<connection_map name="part0_p2a_1" c1_st_index="110" c1_end_index="129" c2_st_index="0"
</connection>

<connection_map name="part0_p2b_1" c1_st_index="130" c1_end_index="159" c2_st_index="0"
</connection>
<connection name="part0_asio" component1="part0" component2="asio">

<connection_map name="part0_asio_1" c1_st_index="48" c1_end_index="53" c2_st_index="0" c2
<connection_map name="part0_asio_2" c1_st_index="56" c1_end_index="159" c2_st_index="6"
</connection>
sys_gpio
0
1
2
3
4
5
6
sys_gpio0
sys_gpio1
sys_gpio2
sys_gpio3
sys_gpio4
sys_gpio5
p0
0
8
J1_87
1
2
3
4
5
6
7
J1_91
J1_95
J1_93
J1_99
J1_97
J1_92
J1_85
p0_6bits
0
6
J1_87
1
2
3
4
5
J1_91
J1_95
J1_93
J1_99
J1_97
p1a
0
1
2
3
4
28
J1_17
J1_19
J1_21
J1_23
J1_25
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
J1_27
J1_31
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
J1_47
J1_49
J1_51
J1_55
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
J1_83
p1b
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
J1_36
J1_38
J1_40
J1_42
J1_46
J1_48
J1_50
J1_52
J1_56
J1_58
J1_60
J1_62
J1_66
J1_68
J1_70
J1_72
J1_76
J1_78
J1_80
J1_82
J1_86
J1_88
J1_94
J1_96
J1_98
J1_100
25
p2a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
J2_41
J2_43
J2_45
J2_47
J2_51
J2_53
J2_55
J2_57
J2_61
J2_63
J2_65
J2_67
J2_71
J2_73
J2_75
J2_77
J2_81
J2_83
J2_85
J2_87
19
p2b
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
30
J2_32
J2_34
J2_36
J2_38
J2_42
J2_44
J2_46
J2_48
J2_52
J2_54
J2_56
J2_58
J2_62
J2_64
J2_66
J2_68
J2_72
J2_74
J2_76
J2_78
J2_82
J2_84
J2_86
J2_88
J2_92
J2_94
J2_96
J2_98
29
28
29
J2_100
J2_89
asio
0
1
2
110
J1_87
J1_91
J1_95
109
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
J1_93
J1_99
J1_97
J1_17
J1_19
J1_21
J1_23
J1_25
J1_27
J1_31
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
J1_47
J1_49
J1_51
J1_55
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
J1_83
J1_36
J1_38
J1_40
J1_42
J1_46
J1_48
J1_50
J1_52
J1_56
J1_58
J1_60
J1_62
J1_66
J1_68
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
J1_70
J1_72
J1_76
J1_78
J1_80
J1_82
J1_86
J1_88
J1_94
J1_96
J1_98
J1_100
J2_41
J2_43
J2_45
J2_47
J2_51
J2_53
J2_55
J2_57
J2_61
J2_63
J2_65
J2_67
J2_71
J2_73
J2_75
J2_77
J2_81
J2_83
J2_85
J2_87
J2_32
J2_34
J2_36
J2_38
J2_42
J2_44
J2_46
J2_48
J2_52
J2_54
J2_56
J2_58
J2_62
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
J2_64
J2_66
J2_68
J2_72
J2_74
J2_76
J2_78
J2_82
J2_84
J2_86
J2_88
J2_92
J2_94
J2_96
J2_98
J2_100
J2_89
<interface mode="master" name="sys_gpio" type="xilinx.com:interface:gpio_rtl:1.0" of_comp

<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="sys_gpio_tri_o" dir="out" left="5" right="
<pin_maps>
<pin_map port_index="0" component_pin="sys_gpio0"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="sys_gpio_tri_t" dir="out" left="5" right="
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="sys_gpio_tri_i" dir="in" left="5" right="0">
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p0" type="xilinx.com:interface:gpio_rtl:1.0" of_component
<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p0_tri_o" dir="out" left="7" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="J1_87"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p0_tri_t" dir="out" left="7" right="0">
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="p0_tri_i" dir="in" left="7" right="0">
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p0_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_comp
<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p0_6bits_tri_o" dir="out" left="5" right="
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p0_6bits_tri_t" dir="out" left="5" right="
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="p0_6bits_tri_i" dir="in" left="5" right="0">
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p1a" type="xilinx.com:interface:gpio_rtl:1.0" of_componen

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p1a_tri_o" dir="out" left="27" right="0">

<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p1a_tri_t" dir="out" left="27" right="0">
<pin_maps>

</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="p1a_tri_i" dir="in" left="27" right="0">
<pin_maps>
<pin_map port_index="24"
</pin_maps>
</port_map>
</port_maps>
</interface>
component_pin="J1_75"/>
<interface mode="master" name="p1b" type="xilinx.com:interface:gpio_rtl:1.0" of_componen

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p1b_tri_o" dir="out" left="25" right="0">
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p1b_tri_t" dir="out" left="25" right="0">
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="p1b_tri_i" dir="in" left="25" right="0">
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>

<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="asio" type="xilinx.com:interface:gpio_rtl:1.0" of_componen

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="asio_tri_o" dir="out" left="109" right="0
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
port_index="82"
port_index="83"
port_index="84"
port_index="85"

</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="asio_tri_t" dir="out" left="109" right="0"
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="17"
port_index="18"
port_index="19"
port_index="20"
port_index="21"
port_index="22"
port_index="23"
port_index="24"
port_index="25"
port_index="26"
port_index="27"
port_index="28"
port_index="29"
port_index="30"
port_index="31"
port_index="32"
port_index="33"
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="62" component_pin="J2_45"/>

</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="asio_tri_i" dir="in" left="109" right="0">
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
port_index="82"

</pin_maps>
</port_map>
</port_maps>
</interface>
Index
Name
0 spi_ss
1 spi_io_0
2 spi_io_1
3 spi_io_2
4 spi_io_3
5 sys_clk
6 sys_led
7 led2
8 led3
9 dummy_pin
10 ftdi_ch_a_rxd
11 ftdi_ch_a_txd
12 ftdi_bdbus_0
13 ftdi_bdbus_1
14 ftdi_bdbus_2
15 ftdi_bdbus_3
16 ftdi_bdbus_4
17 ftdi_bdbus_5
18 ftdi_bdbus_6
19 ftdi_bdbus_7
20 ftdi_bcbus_0
21 ftdi_bcbus_1
22 ftdi_bcbus_2
23 ftdi_bcbus_3
24 ftdi_bcbus_4
25 ftdi_bcbus_7
26 J1_87
27 J1_91
28 J1_95
29 J1_93
30 J1_99
31 J1_97
32 J1_92
33 J1_85
34 J1_17
35 J1_19
36 J1_21
37 J1_23
38 J1_25
39 J1_27
40 J1_31
41 J1_33
42 J1_35
43 J1_37
44 J1_41
45 J1_43
iostandard
loc
bank
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS18
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
L13
K17
K18
L14
M14
P17
A8
R17
L15
K6
R11
L16
P18
R18
T18
U18
U17
T16
V17
U16
V16
U14
V15
T13
V14
U13
R13
R12
M13
L18
R16
M18
N17
R10
C11
C10
A10
A9
C9
B9
F13
F14
H14
G14
B18
A18
B14
B14
B14
B14
B14
B14
B16
B14
B14
B16
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B16
B16
B16
B16
B16
B16
B15
B15
B15
B15
B15
B15
46 J1_45
47 J1_47
48 J1_49
49 J1_51
50 J1_55
51 J1_57
52 J1_59
53 J1_61
54 J1_65
55 J1_67
56 J1_69
57 J1_71
58 J1_75
59 J1_77
60 J1_81
61 J1_83
62 J1_36
63 J1_38
64 J1_40
65 J1_42
66 J1_46
67 J1_48
68 J1_50
69 J1_52
70 J1_56
71 J1_58
72 J1_60
73 J1_62
74 J1_66
75 J1_68
76 J1_70
77 J1_72
78 J1_76
79 J1_78
80 J1_80
81 J1_82
82 J1_86
83 J1_88
84 J1_94
85 J1_96
86 J1_98
87 J1_100
88 J2_41
89 J2_43
90 J2_45
91 J2_47
92 J2_51
93 J2_53
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
B17
B16
D12
D13
A16
A15
G16
H16
F16
F15
A14
A13
C15
D15
A11
B11
E18
D18
J18
J17
G18
F18
J14
H15
K13
J13
K15
J15
E16
E15
H17
G17
E17
D17
C17
C16
D14
C14
B14
B13
C12
B12
H6
H5
J4
H4
E2
D2
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B35
B35
B35
B35
B35
B35
94 J2_55
95 J2_57
96 J2_61
97 J2_63
98 J2_65
99 J2_67
100 J2_71
101 J2_73
102 J2_75
103 J2_77
104 J2_81
105 J2_83
106 J2_85
107 J2_87
108 J2_32
109 J2_34
110 J2_36
111 J2_38
112 J2_42
113 J2_44
114 J2_46
115 J2_48
116 J2_52
117 J2_54
118 J2_56
119 J2_58
120 J2_62
121 J2_64
122 J2_66
123 J2_68
124 J2_72
125 J2_74
126 J2_76
127 J2_78
128 J2_82
129 J2_84
130 J2_86
131 J2_88
132 J2_92
133 J2_94
134 J2_96
135 J2_98
136 J2_100
137 J2_89
138 J2_11
139 J2_13
140 J2_15
141 J2_17
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
G4
G3
H2
G2
G6
F6
E7
D7
C4
B4
C5
C6
C7
D8
E6
E5
K2
K1
J2
J3
F4
F3
D5
D4
E3
D3
H1
G1
F1
E1
C1
C2
B1
A1
B2
B3
A3
A4
A5
A6
B6
B7
J5
F5
U12
V12
N14
P14
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B14
B14
B14
B14
142 J2_21
143 J2_23
144 J2_25
145 J2_27
146 J2_31
147 J2_33
148 J2_35
149 J2_37
150 J2_14
151 J2_16
152 J2_22
153 J2_24
154 J2_26
155 J2_28
156 J1_4
157 J1_6
158 J1_10
159 J1_12
160 J1_16
161 J1_18
162 J1_22
163 J1_24
164 J3_7
165 J3_9
166 J3_13
167 J3_15
168 J3_19
169 J3_21
170 J3_25
171 J3_27
172 J3_31
173 J3_33
174 J3_8
175 J3_10
176 J3_14
177 J3_16
178 J3_20
179 J3_22
180 J3_26
181 J3_28
182 J3_32
183 J3_34
184 J3_1
185 J3_3
186 J3_37
187 J3_39
188 J3_41
189 J3_43
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
T14
T15
P15
R15
T11
U11
T10
T9
V11
V10
N15
N16
M16
M17
L4
K5
N6
M6
T8
R8
L6
L5
R6
R5
R7
T6
V9
U9
V5
V4
N5
P5
U7
U6
R2
P2
V7
V6
U4
U3
T5
T4
M4
N4
K3
L3
V2
U2
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
190 J3_57
191 J3_59
192 J3_2
193 J3_4
194 J3_38
195 J3_40
196 J3_42
197 J3_44
198 J3_48
199 J3_50
200 J3_52
201 J3_54
202 J3_58
203 J3_60
204 dummy_rst
205
206
207
208
205
206
207
208
209
210
211
212
213
214
215
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS18
M1
L1
T3
R3
V1
U1
T1
R1
M3
M2
N2
N1
P4
P3
D9
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B16
iostandard="LVCMOS33"
87
91
95
93
99
97
92
85
17
19
21
23
25
27
31
33
35
37
41
43
{1,87,20},
{1,91,21},
{1,95,22},
{1,93,23},
{1,99,24},
{1,97,25},
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
{1,17,26},
{1,19,27},
{1,21,28},
{1,23,29},
{1,25,30},
{1,27,31},
{1,31,32},
{1,33,33},
{1,35,34},
{1,37,35},
{1,41,36},
{1,43,37},
26
27
28
29
30
31
32
33
34
35
36
37
45
47
49
51
55
57
59
61
65
67
69
71
75
77
81
83
36
38
40
42
46
48
50
52
56
58
60
62
66
68
70
72
76
78
80
82
86
88
94
96
98
100
41
43
45
47
51
53
{1,45,38},
{1,47,39},
{1,49,40},
{1,51,41},
{1,55,42},
{1,57,43},
{1,59,44},
{1,61,45},
{1,65,46},
{1,67,47},
{1,69,48},
{1,71,49},
{1,75,50},
{1,77,51},
{1,81,52},
{1,83,53},
{1,36,54},
{1,38,55},
{1,40,56},
{1,42,57},
{1,46,58},
{1,48,59},
{1,50,60},
{1,52,61},
{1,56,62},
{1,58,63},
{1,60,64},
{1,62,65},
{1,66,66},
{1,68,67},
{1,70,68},
{1,72,69},
{1,76,70},
{1,78,71},
{1,80,72},
{1,82,73},
{1,86,74},
{1,88,75},
{1,94,76},
{1,96,77},
{1,98,78},
{1,100,79},
{2,41,80},
{2,43,81},
{2,45,82},
{2,47,83},
{2,51,84},
{2,53,85},
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
55
57
61
63
65
67
71
73
75
77
81
83
85
87
32
34
36
38
42
44
46
48
52
54
56
58
62
64
66
68
72
74
76
78
82
84
86
88
92
94
96
98
100
89
11
13
15
17
{2,55,86},
{2,57,87},
{2,61,88},
{2,63,89},
{2,65,90},
{2,67,91},
{2,71,92},
{2,73,93},
{2,75,94},
{2,77,95},
{2,81,96},
{2,83,97},
{2,85,98},
{2,87,99},
{2,32,100},
{2,34,101},
{2,36,102},
{2,38,103},
{2,42,104},
{2,44,105},
{2,46,106},
{2,48,107},
{2,52,108},
{2,54,109},
{2,56,110},
{2,58,111},
{2,62,112},
{2,64,113},
{2,66,114},
{2,68,115},
{2,72,116},
{2,74,117},
{2,76,118},
{2,78,119},
{2,82,120},
{2,84,121},
{2,86,122},
{2,88,123},
{2,92,124},
{2,94,125},
{2,96,126},
{2,98,127},
{2,100,128},
{2,89,129},
{2,11,130},
{2,13,131},
{2,15,132},
{2,17,133},
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
21
23
25
27
31
33
35
37
14
16
22
24
26
28
4
6
10
12
16
18
22
24
7
9
13
15
19
21
25
27
31
33
8
10
14
16
20
22
26
28
32
34
1
3
37
39
41
43
{2,21,134},
{2,23,135},
{2,25,136},
{2,27,137},
{2,31,138},
{2,33,139},
{2,35,140},
{2,37,141},
{2,14,142},
{2,16,143},
{2,22,144},
{2,24,145},
{2,26,146},
{2,28,147},
{1,4,148},
{1,6,149},
{1,10,150},
{1,12,151},
{1,16,152},
{1,18,153},
{1,22,154},
{1,24,155},
{3,7,156},
{3,9,157},
{3,13,158},
{3,15,159},
{3,19,160},
{3,21,161},
{3,25,162},
{3,27,163},
{3,31,164},
{3,33,165},
{3,8,166},
{3,10,167},
{3,14,168},
{3,16,169},
{3,20,170},
{3,22,171},
{3,26,172},
{3,28,173},
{3,32,174},
{3,34,175},
{3,1,176},
{3,3,177},
{3,37,178},
{3,39,179},
{3,41,180},
{3,43,181},
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
57
59
2
4
38
40
42
44
48
50
52
54
58
60
{3,57,182},
{3,59,183},
{3,2,184},
{3,4,185},
{3,38,186},
{3,40,187},
{3,42,188},
{3,44,189},
{3,48,190},
{3,50,191},
{3,52,192},
{3,54,193},
{3,58,194},
{3,60,195},
182
183
184
185
186
187
188
189
190
191
192
193
194
195
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
PIN_sys_led 0
PIN_led2 1
PIN_led3 2
PIN_dummy_pin 3
PIN_ftdi_ch_a_rxd 4
PIN_ftdi_ch_a_txd 5
PIN_ftdi_bdbus_0 6
PIN_ftdi_bdbus_1 7
PIN_ftdi_bdbus_2 8
PIN_ftdi_bdbus_3 9
PIN_ftdi_bdbus_4 10
PIN_ftdi_bdbus_5 11
PIN_ftdi_bdbus_6 12
PIN_ftdi_bdbus_7 13
PIN_ftdi_bcbus_0 14
PIN_ftdi_bcbus_1 15
PIN_ftdi_bcbus_2 16
PIN_ftdi_bcbus_3 17
PIN_ftdi_bcbus_4 18
PIN_ftdi_bcbus_7 19
PIN_J1_87 20
PIN_J1_91 21
PIN_J1_95 22
PIN_J1_93 23
PIN_J1_99 24
PIN_J1_97 25
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
PIN_J1_17
PIN_J1_19
PIN_J1_21
PIN_J1_23
PIN_J1_25
PIN_J1_27
PIN_J1_31
PIN_J1_33
PIN_J1_35
PIN_J1_37
PIN_J1_41
PIN_J1_43
26
27
28
29
30
31
32
33
34
35
36
37
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
PIN_J1_45 38
PIN_J1_47 39
PIN_J1_49 40
PIN_J1_51 41
PIN_J1_55 42
PIN_J1_57 43
PIN_J1_59 44
PIN_J1_61 45
PIN_J1_65 46
PIN_J1_67 47
PIN_J1_69 48
PIN_J1_71 49
PIN_J1_75 50
PIN_J1_77 51
PIN_J1_81 52
PIN_J1_83 53
PIN_J1_36 54
PIN_J1_38 55
PIN_J1_40 56
PIN_J1_42 57
PIN_J1_46 58
PIN_J1_48 59
PIN_J1_50 60
PIN_J1_52 61
PIN_J1_56 62
PIN_J1_58 63
PIN_J1_60 64
PIN_J1_62 65
PIN_J1_66 66
PIN_J1_68 67
PIN_J1_70 68
PIN_J1_72 69
PIN_J1_76 70
PIN_J1_78 71
PIN_J1_80 72
PIN_J1_82 73
PIN_J1_86 74
PIN_J1_88 75
PIN_J1_94 76
PIN_J1_96 77
PIN_J1_98 78
PIN_J1_100 79
PIN_J2_41 80
PIN_J2_43 81
PIN_J2_45 82
PIN_J2_47 83
PIN_J2_51 84
PIN_J2_53 85
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
PIN_J2_55 86
PIN_J2_57 87
PIN_J2_61 88
PIN_J2_63 89
PIN_J2_65 90
PIN_J2_67 91
PIN_J2_71 92
PIN_J2_73 93
PIN_J2_75 94
PIN_J2_77 95
PIN_J2_81 96
PIN_J2_83 97
PIN_J2_85 98
PIN_J2_87 99
PIN_J2_32 100
PIN_J2_34 101
PIN_J2_36 102
PIN_J2_38 103
PIN_J2_42 104
PIN_J2_44 105
PIN_J2_46 106
PIN_J2_48 107
PIN_J2_52 108
PIN_J2_54 109
PIN_J2_56 110
PIN_J2_58 111
PIN_J2_62 112
PIN_J2_64 113
PIN_J2_66 114
PIN_J2_68 115
PIN_J2_72 116
PIN_J2_74 117
PIN_J2_76 118
PIN_J2_78 119
PIN_J2_82 120
PIN_J2_84 121
PIN_J2_86 122
PIN_J2_88 123
PIN_J2_92 124
PIN_J2_94 125
PIN_J2_96 126
PIN_J2_98 127
PIN_J2_100 128
PIN_J2_89 129
PIN_J2_11 130
PIN_J2_13 131
PIN_J2_15 132
PIN_J2_17 133
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
PIN_J2_21 134
PIN_J2_23 135
PIN_J2_25 136
PIN_J2_27 137
PIN_J2_31 138
PIN_J2_33 139
PIN_J2_35 140
PIN_J2_37 141
PIN_J2_14 142
PIN_J2_16 143
PIN_J2_22 144
PIN_J2_24 145
PIN_J2_26 146
PIN_J2_28 147
PIN_J1_4 148
PIN_J1_6 149
PIN_J1_10 150
PIN_J1_12 151
PIN_J1_16 152
PIN_J1_18 153
PIN_J1_22 154
PIN_J1_24 155
PIN_J3_7 156
PIN_J3_9 157
PIN_J3_13 158
PIN_J3_15 159
PIN_J3_19 160
PIN_J3_21 161
PIN_J3_25 162
PIN_J3_27 163
PIN_J3_31 164
PIN_J3_33 165
PIN_J3_8 166
PIN_J3_10 167
PIN_J3_14 168
PIN_J3_16 169
PIN_J3_20 170
PIN_J3_22 171
PIN_J3_26 172
PIN_J3_28 173
PIN_J3_32 174
PIN_J3_34 175
PIN_J3_1 176
PIN_J3_3 177
PIN_J3_37 178
PIN_J3_39 179
PIN_J3_41 180
PIN_J3_43 181
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
PIN_J3_57 182
PIN_J3_59 183
PIN_J3_2 184
PIN_J3_4 185
PIN_J3_38 186
PIN_J3_40 187
PIN_J3_42 188
PIN_J3_44 189
PIN_J3_48 190
PIN_J3_50 191
PIN_J3_52 192
PIN_J3_54 193
PIN_J3_58 194
PIN_J3_60 195
PIN_dummy_rst
XDC
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
L13 [get_ports spi_ss]

L14 [get_ports spi_io_2]
M14 [get_ports spi_io_3]
P17 [get_ports sys_clk]
A8 [get_ports sys_led]
R17 [get_ports led2]
L15 [get_ports led3]
K6 [get_ports dummy_pin]
R11 [get_ports ftdi_ch_a_rxd]
L16 [get_ports ftdi_ch_a_txd]
P18 [get_ports ftdi_bdbus_0]
R18 [get_ports ftdi_bdbus_1]
T18 [get_ports ftdi_bdbus_2]
U18 [get_ports ftdi_bdbus_3]
T16 [get_ports ftdi_bdbus_5]
V17 [get_ports ftdi_bdbus_6]
V16 [get_ports ftdi_bcbus_0]
U14 [get_ports ftdi_bcbus_1]
T13 [get_ports ftdi_bcbus_3]
U13 [get_ports ftdi_bcbus_7]
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

L4 [get_ports J1_4]
K5 [get_ports J1_6]
R6 [get_ports J3_7]
R5 [get_ports J3_9]
U7 [get_ports J3_8]
M4 [get_ports J3_1]
N4 [get_ports J3_3]
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
T3 [get_ports J3_2]
R3 [get_ports J3_4]
D9 [get_ports dummy_rst]
part0_pins.xml
<?xml version="1.0" encoding="UTF-8" standalone="no"?><part_info part_name="xc7a35tsg324
<pin index="0" name="spi_ss" iostandard="LVCMOS33" loc="L13"/>
<pin index="3" name="spi_io_2" iostandard="LVCMOS33" loc="L14"/>
<pin index="4" name="spi_io_3" iostandard="LVCMOS33" loc="M14"/>
<pin index="5" name="sys_clk" iostandard="LVCMOS33" loc="P17"/>
<pin index="6" name="sys_led" iostandard="LVCMOS18" loc="A8"/>
<pin index="7" name="led2" iostandard="LVCMOS33" loc="R17"/>
<pin index="8" name="led3" iostandard="LVCMOS33" loc="L15"/>
<pin index="9" name="dummy_pin" iostandard="LVCMOS33" loc="K6"/>
<pin index="10" name="ftdi_ch_a_rxd" iostandard="LVCMOS33" loc="R11"/>
<pin index="11" name="ftdi_ch_a_txd" iostandard="LVCMOS33" loc="L16"/>
<pin index="12" name="ftdi_bdbus_0" iostandard="LVCMOS33" loc="P18"/>
<pin index="13" name="ftdi_bdbus_1" iostandard="LVCMOS33" loc="R18"/>
<pin index="14" name="ftdi_bdbus_2" iostandard="LVCMOS33" loc="T18"/>
<pin index="15" name="ftdi_bdbus_3" iostandard="LVCMOS33" loc="U18"/>
<pin index="17" name="ftdi_bdbus_5" iostandard="LVCMOS33" loc="T16"/>
<pin index="18" name="ftdi_bdbus_6" iostandard="LVCMOS33" loc="V17"/>
<pin index="20" name="ftdi_bcbus_0" iostandard="LVCMOS33" loc="V16"/>
<pin index="21" name="ftdi_bcbus_1" iostandard="LVCMOS33" loc="U14"/>
<pin index="23" name="ftdi_bcbus_3" iostandard="LVCMOS33" loc="T13"/>
<pin index="25" name="ftdi_bcbus_7" iostandard="LVCMOS33" loc="U13"/>
<pin index="26" name="J1_87" iostandard="LVCMOS33" loc="R13"/>
<pin index="28" name="J1_95" iostandard="LVCMOS33" loc="M13"/>
<pin index="29" name="J1_93" iostandard="LVCMOS33" loc="L18"/>
<pin index="31" name="J1_97" iostandard="LVCMOS33" loc="M18"/>
<pin index="32" name="J1_92" iostandard="LVCMOS33" loc="N17"/>
<pin index="34" name="J1_17" iostandard="LVCMOS18" loc="C11"/>
<pin index="36" name="J1_21" iostandard="LVCMOS18" loc="A10"/>
<pin index="39" name="J1_27" iostandard="LVCMOS18" loc="B9"/>
<pin index="40" name="J1_31" iostandard="LVCMOS33" loc="F13"/>
<pin index="42" name="J1_35" iostandard="LVCMOS33" loc="H14"/>
<pin index="43" name="J1_37" iostandard="LVCMOS33" loc="G14"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="46"
index="47"
index="48"
index="49"
index="50"
index="51"
index="52"
index="53"
index="54"
index="55"
index="56"
index="57"
index="58"
index="59"
index="60"
index="61"
index="62"
index="63"
index="64"
index="65"
index="66"
index="67"
index="68"
index="69"
index="70"
index="71"
index="72"
index="73"
index="74"
index="75"
index="76"
index="77"
index="78"
index="79"
index="80"
index="81"
index="82"
index="83"
index="84"
index="85"
index="86"
index="87"
index="88"
index="89"
index="90"
index="91"
index="92"
index="93"

name="J1_49" iostandard="LVCMOS33" loc="D12"/>
name="J1_59" iostandard="LVCMOS33" loc="G16"/>
name="J1_61" iostandard="LVCMOS33" loc="H16"/>
name="J1_65" iostandard="LVCMOS33" loc="F16"/>
name="J1_36" iostandard="LVCMOS33" loc="E18"/>
name="J1_40" iostandard="LVCMOS33" loc="J18"/>
name="J1_56" iostandard="LVCMOS33" loc="K13"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="94" name="J2_55" iostandard="LVCMOS33" loc="G4"/>

index="96" name="J2_61" iostandard="LVCMOS33" loc="H2"/>
index="99" name="J2_67" iostandard="LVCMOS33" loc="F6"/>
index="100" name="J2_71" iostandard="LVCMOS33" loc="E7"/>
index="101" name="J2_73" iostandard="LVCMOS33" loc="D7"/>
index="102" name="J2_75" iostandard="LVCMOS33" loc="C4"/>
index="103" name="J2_77" iostandard="LVCMOS33" loc="B4"/>
index="110" name="J2_36" iostandard="LVCMOS33" loc="K2"/>
index="112" name="J2_42" iostandard="LVCMOS33" loc="J2"/>
index="127" name="J2_78" iostandard="LVCMOS33" loc="A1"/>
index="138" name="J2_11" iostandard="LVCMOS33" loc="U12"/>
index="139" name="J2_13" iostandard="LVCMOS33" loc="V12"/>
index="140" name="J2_15" iostandard="LVCMOS33" loc="N14"/>
index="141" name="J2_17" iostandard="LVCMOS33" loc="P14"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="142"
index="143"
index="144"
index="145"
index="146"
index="147"
index="148"
index="149"
index="150"
index="151"
index="152"
index="153"
index="154"
index="155"
index="156"
index="157"
index="158"
index="159"
index="160"
index="161"
index="162"
index="163"
index="164"
index="165"
index="166"
index="167"
index="168"
index="169"
index="170"
index="171"
index="172"
index="173"
index="174"
index="175"
index="176"
index="177"
index="178"
index="179"
index="180"
index="181"
index="182"
index="183"
index="184"
index="185"
index="186"
index="187"
index="188"
index="189"

name="J2_25" iostandard="LVCMOS33" loc="P15"/>
name="J2_33" iostandard="LVCMOS33" loc="U11"/>
name="J2_14" iostandard="LVCMOS33" loc="V11"/>
name="J2_22" iostandard="LVCMOS33" loc="N15"/>
<pin index="190"
<pin index="191"
<pin index="192"
<pin index="193"
<pin index="194"
<pin index="195"
<pin index="196"
<pin index="197"
<pin index="198"
<pin index="199"
<pin index="200"
<pin index="201"
<pin index="202"
<pin index="203"
<pin index="204"
</pins>
</part_info>

name="dummy_rst" iostandard="LVCMOS18" loc="D9"/>
name/first
width
spi_flash
0
10
11
26
33
26
31
40
32
71
31
72
16
87
15
88
32
119
31
120
18
137
17
138
18
155
17
sys_clk
leds
dummy_rst
base_uart0
p0
p0_6bit
p1a
p1b
p2a
p2b
p2c
p3a
184
32
215
31
164
171
34
39
156
163
p3b
p1c
p1d
dummy_rst
74
1
74
0
<connections>
</connection>
<connection name="part0_sys_clk" component1="part0" component2="sys_clk">

<connection_map name="part0_sys_clk_1" c1_st_index="5" c1_end_index="5" c2_st_index="0" c2
</connection>
<connection name="part0_leds" component1="part0" component2="leds">

<connection_map name="part0_leds_1" c1_st_index="6" c1_end_index="8" c2_st_index="0" c2_e
</connection>
<connection name="part0_dummy_rst" component1="part0" component2="dummy_rst">

<connection_map name="part0_dummy_rst_1" c1_st_index="9" c1_end_index="9" c2_st_index="
</connection>
<connection name="part0_base_uart0" component1="part0" component2="base_uart0">

<connection_map name="part0_base_uart0_1" c1_st_index="10" c1_end_index="11" c2_st_index=
</connection>

</connection>
<connection name="part0_p0_6bit" component1="part0" component2="p0_6bit">

<connection_map name="part0_p0_6bit_1" c1_st_index="26" c1_end_index="31" c2_st_index="0
</connection>

</connection>

<connection_map name="part0_p1b_1" c1_st_index="72" c1_end_index="87" c2_st_index="0" c2
</connection>

<connection_map name="part0_p2a_1" c1_st_index="88" c1_end_index="119" c2_st_index="0" c
</connection>
</connection>
<connection name="part0_p2c" component1="part0" component2="p2c">
<connection_map name="part0_p2c_1" c1_st_index="138" c1_end_index="155" c2_st_index="0"

</connection>
</connection>
</connection>

<connection_map name="part0_p1c_1" c1_st_index="34" c1_end_index="39" c2_st_index="0" c2
</connection>
<connection name="part0_p1d" component1="part0" component2="p1d">
<connection_map name="part0_p1d_1" c1_st_index="156" c1_end_index="163" c2_st_index="0"
</connection>
</connections>
<connection name="part0_dummy_rst component1="part0" component2="dummy_rst">

<connection_map name="part0_dummy_rst_1" c1_st_index="74" c1_end_index="74" c2_st_index=
</connection>
p0
0
1
2
3
4
5
6
7
8
J1_87
J1_91
J1_95
J1_93
J1_99
J1_97
J1_92
J1_85
p0_6bits
0
6
J1_87
1
2
3
4
5
J1_91
J1_95
J1_93
J1_99
J1_97
p1a
0
1
2
3
4
5
6
7
8
9
10
32
J1_31
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
J1_47
J1_49
J1_51
J1_55
31
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
J1_83
J1_36
J1_38
J1_40
J1_42
J1_46
J1_48
J1_50
J1_52
J1_56
J1_58
p1b
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J1_60
J1_62
J1_66
J1_68
J1_70
J1_72
J1_76
J1_78
J1_80
J1_82
J1_86
J1_88
J1_94
J1_96
J1_98
J1_100
15
p2a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
32
J2_41
J2_43
J2_45
J2_47
J2_51
J2_53
J2_55
J2_57
J2_61
J2_63
J2_65
J2_67
J2_71
J2_73
J2_75
J2_77
J2_81
J2_83
J2_85
J2_87
J2_32
J2_34
J2_36
31
23
24
25
26
27
28
29
30
31
J2_38
J2_42
J2_44
J2_46
J2_48
J2_52
J2_54
J2_56
J2_58
p2b
0
1
2
18
J2_62
J2_64
J2_66
17
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
J2_68
J2_72
J2_74
J2_76
J2_78
J2_82
J2_84
J2_86
J2_88
J2_92
J2_94
J2_96
J2_98
J2_100
J2_89
p2c
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
J2_11
J2_13
J2_15
J2_17
J2_21
J2_23
J2_25
J2_27
J2_31
J2_33
J2_35
J2_37
J2_14
J2_16
J2_22
J2_24
J2_26
J2_28
17
p1d
0
1
2
3
4
5
6
7
8
J1_4
J1_6
J1_10
J1_12
J1_16
J1_18
J1_22
J1_24
p1c
0
1
2
6
J1_17
J1_19
J1_21
3
4
5
J1_23
J1_25
J1_27
p3b
0
1
2
3
4
5
6
7
8
9
10
11
12
20
J3_7
J3_9
J3_13
J3_15
J3_19
J3_21
J3_25
J3_27
J3_31
J3_33
J3_8
J3_10
J3_14
19
13
14
15
16
17
18
19
J3_16
J3_20
J3_22
J3_26
J3_28
J3_32
J3_34
p3a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
J3_1
J3_3
J3_37
J3_39
J3_41
J3_43
J3_57
J3_59
J3_2
J3_4
J3_38
J3_40
J3_42
J3_44
J3_48
J3_50
J3_52
J3_54
J3_58
J3_60
19
asio
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
196
195
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
<interface mode="master" name="p0" type="xilinx.com:interface:gpio_rtl:1.0" of_compone

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p0_tri_o" dir="out" left="7" right="0"
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p0_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_co
<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p0_6bits_tri_o" dir="out" left="5" righ
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p0_6bits_tri_t" dir="out" left="5" righ
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="p0_6bits_tri_i" dir="in" left="5" right="
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p1a" type="xilinx.com:interface:gpio_rtl:1.0" of_compon

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p1a_tri_o" dir="out" left="31" right="
<pin_maps>

</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p1a_tri_t" dir="out" left="31" right="
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p1b" type="xilinx.com:interface:gpio_rtl:1.0" of_compon

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p1b_tri_o" dir="out" left="15" right="
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p1b_tri_t" dir="out" left="15" right="
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p2c" type="xilinx.com:interface:gpio_rtl:1.0" of_compon

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p2c_tri_o" dir="out" left="17" right="
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="0_tri_t" dir="out" left="" right="0">
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="p2c_tri_i" dir="in" left="17" right="0">
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p1d" type="xilinx.com:interface:gpio_rtl:1.0" of_compon

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p1d_tri_o" dir="out" left="7" right="0
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p1d_tri_t" dir="out" left="7" right="0
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="p1d_tri_i" dir="in" left="7" right="0">
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p1c_tri_o" dir="out" left="5" right="0
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p1c_tri_t" dir="out" left="5" right="0
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>

<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="asio" type="xilinx.com:interface:gpio_rtl:1.0" of_compo

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="asio_tri_o" dir="out" left="195" right=
<pin_maps>
<pin_map port_index="0" component_pin="sys_led"/>
<pin_map port_index="1" component_pin="led2"/>
<pin_map port_index="3" component_pin="dummy_pin"/>
<pin_map port_index="4" component_pin="ftdi_ch_a_rxd"/>
<pin_map port_index="5" component_pin="ftdi_ch_a_txd"/>
<pin_map port_index="6" component_pin="ftdi_bdbus_0"/>
<pin_map port_index="14" component_pin="ftdi_bcbus_0"/>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
port_index="82"
port_index="83"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="132"
port_index="133"
port_index="134"
port_index="135"
port_index="136"
port_index="137"
port_index="138"
port_index="139"
port_index="140"
port_index="141"
port_index="142"
port_index="143"
port_index="144"
port_index="145"
port_index="146"
port_index="147"
port_index="148"
port_index="149"
port_index="150"
port_index="151"
port_index="152"
port_index="153"
port_index="154"
port_index="155"
port_index="156"
port_index="157"
port_index="158"
port_index="159"
port_index="160"
port_index="161"
port_index="162"
port_index="163"
port_index="164"
port_index="165"
port_index="166"
port_index="167"
port_index="168"
port_index="169"
port_index="170"
port_index="171"
port_index="172"
port_index="173"
port_index="174"
port_index="175"
port_index="176"
port_index="177"
port_index="178"
port_index="179"

</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="asio_tri_t" dir="out" left="195" right=
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="28"
port_index="29"
port_index="30"
port_index="31"
port_index="32"
port_index="33"
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="124"
port_index="125"
port_index="126"
port_index="127"
port_index="128"
port_index="129"
port_index="130"
port_index="131"
port_index="132"
port_index="133"
port_index="134"
port_index="135"
port_index="136"
port_index="137"
port_index="138"
port_index="139"
port_index="140"
port_index="141"
port_index="142"
port_index="143"
port_index="144"
port_index="145"
port_index="146"
port_index="147"
port_index="148"
port_index="149"
port_index="150"
port_index="151"
port_index="152"
port_index="153"
port_index="154"
port_index="155"
port_index="156"
port_index="157"
port_index="158"
port_index="159"
port_index="160"
port_index="161"
port_index="162"
port_index="163"
port_index="164"
port_index="165"
port_index="166"
port_index="167"
port_index="168"
port_index="169"
port_index="170"
port_index="171"

</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="asio_tri_i" dir="in" left="195" right="0
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="20"
port_index="21"
port_index="22"
port_index="23"
port_index="24"
port_index="25"
port_index="26"
port_index="27"
port_index="28"
port_index="29"
port_index="30"
port_index="31"
port_index="32"
port_index="33"
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="116"
port_index="117"
port_index="118"
port_index="119"
port_index="120"
port_index="121"
port_index="122"
port_index="123"
port_index="124"
port_index="125"
port_index="126"
port_index="127"
port_index="128"
port_index="129"
port_index="130"
port_index="131"
port_index="132"
port_index="133"
port_index="134"
port_index="135"
port_index="136"
port_index="137"
port_index="138"
port_index="139"
port_index="140"
port_index="141"
port_index="142"
port_index="143"
port_index="144"
port_index="145"
port_index="146"
port_index="147"
port_index="148"
port_index="149"
port_index="150"
port_index="151"
port_index="152"
port_index="153"
port_index="154"
port_index="155"
port_index="156"
port_index="157"
port_index="158"
port_index="159"
port_index="160"
port_index="161"
port_index="162"
port_index="163"
</pin_maps>
</port_map>
</port_maps>
</interface>
Index
Name
0 RESET
1 spi_ss_i_0
2 spi_io0_i
3 spi_io1_i
4 spi_io2_i
5 spi_io3_i
6 sys_diff_clkp
7 sys_diff_clkn
8 sys_led
9 led2
10 iic_main0_scl_i
11 iic_main0_sda_i
12 mgt_diff_clkp
13 mgt_diff_clkn
14 RMII0_TXD0
15 RMII0_TXD1
16 RMII0_TXEN
17 RMII0_CRSDV
18 RMII0_RXD0
19 RMII0_RXD1
20 PHY0_MDIO
21 PHY0_MDC
22 phy_rst_out
23 J1_87
24 J1_91
25 J1_95
26 J1_93
27 J1_99
28 J1_97
29 J1_92
30 J1_85
31 J1_17
32 J1_19
33 J1_21
34 J1_23
35 J1_25
36 J1_27
37 J1_16
38 J1_18
39 J1_22
40 J1_24
41 J1_31
42 J1_33
iostandard
loc
bank
LVCMOS15
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCOMS15
LVCMOS15
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
T3
T19
P22
R22
P21
R21
H4
G4
U22
W22
W21
T20
F6
E6
P14
P15
R14
P20
N13
N14
P17
R16
N17
U17
Y21
T21
Y22
R17
U21
P16
U18
AA13
AB13
Y12
Y11
AA11
AA10
Y14
W14
AA14
Y13
E22
D22
B34
B14
B14
B14
B14
B14
B35
B35
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B16
B16
43 J1_35
44 J1_37
45 J1_41
46 J1_43
47 J1_45
48 J1_47
49 J1_49
50 J1_51
51 J1_55
52 J1_57
53 J1_59
54 J1_61
55 J1_65
56 J1_67
57 J1_69
58 J1_71
59 J1_75
60 J1_77
61 J1_81
62 J1_83
63 J1_36
64 J1_38
65 J1_40
66 J1_42
67 J1_46
68 J1_48
69 J1_50
70 J1_52
71 J1_56
72 J1_58
73 J1_60
74 J1_62
75 J1_66
76 J1_68
77 J1_70
78 J1_72
79 J1_76
80 J1_78
81 J1_80
82 J1_82
83 J1_86
84 J1_88
85 J1_94
86 J1_96
87 J1_98
G22
G21
E21
D21
F18
E18
C22
B22
B21
A21
C18
C19
E19
D19
C15
C14
D17
C17
B13
C13
B20
A20
C20
D20
A19
A18
F20
F19
A16
A15
B16
B15
B17
B18
A14
A13
D16
E16
E17
F16
D15
D14
E14
E13
F14
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
88 J1_100
89 J2_11
90 J2_13
91 J2_15
92 J2_17
93 J2_21
94 J2_23
95 J2_25
96 J2_27
97 J2_31
98 J2_33
99 J2_35
100 J2_37
101 J2_14
102 J2_16
103 J2_22
104 J2_24
105 J2_26
106 J2_28
107 J2_41
108 J2_43
109 J2_45
110 J2_47
111 J2_51
112 J2_53
113 J2_55
114 J2_57
115 J2_61
116 J2_63
117 J2_65
118 J2_67
119 J2_71
120 J2_73
121 J2_75
122 J2_77
123 J2_81
124 J2_83
125 J2_85
126 J2_87
127 J2_32
128 J2_34
129 J2_36
130 J2_38
131 J2_42
132 J2_44
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
F13
AA21
AA20
AB18
AA18
V18
V19
Y18
Y19
V17
W17
AA19
AB20
AB22
AB21
W19
W20
U20
V20
L16
K16
K13
K14
J20
J21
J14
H14
N19
N18
M18
L18
H13
G13
G16
G15
G17
G18
H15
J15
K22
K21
G20
H20
H22
J22
B16
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
133 J2_46
134 J2_48
135 J2_52
136 J2_54
137 J2_56
138 J2_58
139 J2_62
140 J2_64
141 J2_66
142 J2_68
143 J2_72
144 J2_74
145 J2_76
146 J2_78
147 J2_82
148 J2_84
149 J2_86
150 J2_88
151 J2_92
152 J2_94
153 J2_96
154 J2_98
155 J2_100
156 J2_89
157 J3_1
158 J3_3
159 J3_37
160 J3_39
161 J3_41
162 J3_43
163 J3_57
164 J3_59
165 J3_2
166 J3_4
167 J3_38
168 J3_40
169 J3_42
170 J3_44
171 J3_48
172 J3_50
173 J3_52
174 J3_54
175 J3_58
176 J3_60
177 J3_47
LVCMOS33
K18
K19
L19
L20
J19
H19
L21
M21
N20
M20
M13
L13
N22
M22
H18
H17
K17
J17
M16
M15
L15
L14
M17
J16
T16
U16
V10
W10
T14
T15
V13
V14
U15
V15
W15
W16
Y16
AA16
AA15
AB15
AB17
AB16
W11
W12
P19
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B14
178 J3_49
179 J3_51
180 J3_53
181 onewire
182 PLL_INT
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS15
R19
R18
T18
V22
B2
B14
B14
B14
B14
B35
PINAPI include
158 #define PIN_sys_led 158

159 #define PIN_led2 159
{1,87,0},
{1,91,1},
{1,95,2},
{1,93,3},
{1,99,4},
{1,97,5},
{1,17,6},
{1,19,7},
{1,21,8},
{1,23,9},
{1,25,10},
{1,27,11},
{1,16,12},
{1,18,13},
{1,22,14},
{1,24,15},
{1,31,16},
{1,33,17},
0 #define
1 #define
2 #define
3 #define
4 #define
5 #define
PIN_J1_87
PIN_J1_91
PIN_J1_95
PIN_J1_93
PIN_J1_99
PIN_J1_97
0
1
2
3
4
5
6 #define
7 #define
8 #define
9 #define
10 #define
11 #define
12 #define
13 #define
14 #define
15 #define
16 #define
17 #define
PIN_J1_17
PIN_J1_19
PIN_J1_21
PIN_J1_23
PIN_J1_25
PIN_J1_27
PIN_J1_16
PIN_J1_18
PIN_J1_22
PIN_J1_24
PIN_J1_31
PIN_J1_33
6
7
8
9
10
11
12
13
14
15
16
17
{1,35,18},
{1,37,19},
{1,41,20},
{1,43,21},
{1,45,22},
{1,47,23},
{1,49,24},
{1,51,25},
{1,55,26},
{1,57,27},
{1,59,28},
{1,61,29},
{1,65,30},
{1,67,31},
{1,69,32},
{1,71,33},
{1,75,34},
{1,77,35},
{1,81,36},
{1,83,37},
{1,36,38},
{1,38,39},
{1,40,40},
{1,42,41},
{1,46,42},
{1,48,43},
{1,50,44},
{1,52,45},
{1,56,46},
{1,58,47},
{1,60,48},
{1,62,49},
{1,66,50},
{1,68,51},
{1,70,52},
{1,72,53},
{1,76,54},
{1,78,55},
{1,80,56},
{1,82,57},
{1,86,58},
{1,88,59},
{1,94,60},
{1,96,61},
{1,98,62},
18 #define
19 #define
20 #define
21 #define
22 #define
23 #define
24 #define
25 #define
26 #define
27 #define
28 #define
29 #define
30 #define
31 #define
32 #define
33 #define
34 #define
35 #define
36 #define
37 #define
38 #define
39 #define
40 #define
41 #define
42 #define
43 #define
44 #define
45 #define
46 #define
47 #define
48 #define
49 #define
50 #define
51 #define
52 #define
53 #define
54 #define
55 #define
56 #define
57 #define
58 #define
59 #define
60 #define
61 #define
62 #define
PIN_J1_35
PIN_J1_37
PIN_J1_41
PIN_J1_43
PIN_J1_45
PIN_J1_47
PIN_J1_49
PIN_J1_51
PIN_J1_55
PIN_J1_57
PIN_J1_59
PIN_J1_61
PIN_J1_65
PIN_J1_67
PIN_J1_69
PIN_J1_71
PIN_J1_75
PIN_J1_77
PIN_J1_81
PIN_J1_83
PIN_J1_36
PIN_J1_38
PIN_J1_40
PIN_J1_42
PIN_J1_46
PIN_J1_48
PIN_J1_50
PIN_J1_52
PIN_J1_56
PIN_J1_58
PIN_J1_60
PIN_J1_62
PIN_J1_66
PIN_J1_68
PIN_J1_70
PIN_J1_72
PIN_J1_76
PIN_J1_78
PIN_J1_80
PIN_J1_82
PIN_J1_86
PIN_J1_88
PIN_J1_94
PIN_J1_96
PIN_J1_98
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
{1,100,63},
{2,11,64},
{2,13,65},
{2,15,66},
{2,17,67},
{2,21,68},
{2,23,69},
{2,25,70},
{2,27,71},
{2,31,72},
{2,33,73},
{2,35,74},
{2,37,75},
{2,14,76},
{2,16,77},
{2,22,78},
{2,24,79},
{2,26,80},
{2,28,81},
{2,41,82},
{2,43,83},
{2,45,84},
{2,47,85},
{2,51,86},
{2,53,87},
{2,55,88},
{2,57,89},
{2,61,90},
{2,63,91},
{2,65,92},
{2,67,93},
{2,71,94},
{2,73,95},
{2,75,96},
{2,77,97},
{2,81,98},
{2,83,99},
{2,85,100},
{2,87,101},
{2,32,102},
{2,34,103},
{2,36,104},
{2,38,105},
{2,42,106},
{2,44,107},
63 #define
64 #define
65 #define
66 #define
67 #define
68 #define
69 #define
70 #define
71 #define
72 #define
73 #define
74 #define
75 #define
76 #define
77 #define
78 #define
79 #define
80 #define
81 #define
82 #define
83 #define
84 #define
85 #define
86 #define
87 #define
88 #define
89 #define
90 #define
91 #define
92 #define
93 #define
94 #define
95 #define
96 #define
97 #define
98 #define
99 #define
100 #define
101 #define
102 #define
103 #define
104 #define
105 #define
106 #define
107 #define
PIN_J1_100 63
PIN_J2_11 64
PIN_J2_13 65
PIN_J2_15 66
PIN_J2_17 67
PIN_J2_21 68
PIN_J2_23 69
PIN_J2_25 70
PIN_J2_27 71
PIN_J2_31 72
PIN_J2_33 73
PIN_J2_35 74
PIN_J2_37 75
PIN_J2_14 76
PIN_J2_16 77
PIN_J2_22 78
PIN_J2_24 79
PIN_J2_26 80
PIN_J2_28 81
PIN_J2_41 82
PIN_J2_43 83
PIN_J2_45 84
PIN_J2_47 85
PIN_J2_51 86
PIN_J2_53 87
PIN_J2_55 88
PIN_J2_57 89
PIN_J2_61 90
PIN_J2_63 91
PIN_J2_65 92
PIN_J2_67 93
PIN_J2_71 94
PIN_J2_73 95
PIN_J2_75 96
PIN_J2_77 97
PIN_J2_81 98
PIN_J2_83 99
PIN_J2_85 100
PIN_J2_87 101
PIN_J2_32 102
PIN_J2_34 103
PIN_J2_36 104
PIN_J2_38 105
PIN_J2_42 106
PIN_J2_44 107
{2,46,108},
{2,48,109},
{2,52,110},
{2,54,111},
{2,56,112},
{2,58,113},
{2,62,114},
{2,64,115},
{2,66,116},
{2,68,117},
{2,72,118},
{2,74,119},
{2,76,120},
{2,78,121},
{2,82,122},
{2,84,123},
{2,86,124},
{2,88,125},
{2,92,126},
{2,94,127},
{2,96,128},
{2,98,129},
{2,100,130},
{2,89,131},
{3,1,132},
{3,3,133},
{3,37,134},
{3,39,135},
{3,41,136},
{3,43,137},
{3,57,138},
{3,59,139},
{3,2,140},
{3,4,141},
{3,38,142},
{3,40,143},
{3,42,144},
{3,44,145},
{3,48,146},
{3,50,147},
{3,52,148},
{3,54,149},
{3,58,150},
{3,60,151},
{3,47,152},
108 #define
109 #define
110 #define
111 #define
112 #define
113 #define
114 #define
115 #define
116 #define
117 #define
118 #define
119 #define
120 #define
121 #define
122 #define
123 #define
124 #define
125 #define
126 #define
127 #define
128 #define
129 #define
130 #define
131 #define
132 #define
133 #define
134 #define
135 #define
136 #define
137 #define
138 #define
139 #define
140 #define
141 #define
142 #define
143 #define
144 #define
145 #define
146 #define
147 #define
148 #define
149 #define
150 #define
151 #define
152 #define
PIN_J2_46 108
PIN_J2_48 109
PIN_J2_52 110
PIN_J2_54 111
PIN_J2_56 112
PIN_J2_58 113
PIN_J2_62 114
PIN_J2_64 115
PIN_J2_66 116
PIN_J2_68 117
PIN_J2_72 118
PIN_J2_74 119
PIN_J2_76 120
PIN_J2_78 121
PIN_J2_82 122
PIN_J2_84 123
PIN_J2_86 124
PIN_J2_88 125
PIN_J2_92 126
PIN_J2_94 127
PIN_J2_96 128
PIN_J2_98 129
PIN_J2_100 130
PIN_J2_89 131
PIN_J3_1 132
PIN_J3_3 133
PIN_J3_37 134
PIN_J3_39 135
PIN_J3_41 136
PIN_J3_43 137
PIN_J3_57 138
PIN_J3_59 139
PIN_J3_2 140
PIN_J3_4 141
PIN_J3_38 142
PIN_J3_40 143
PIN_J3_42 144
PIN_J3_44 145
PIN_J3_48 146
PIN_J3_50 147
PIN_J3_52 148
PIN_J3_54 149
PIN_J3_58 150
PIN_J3_60 151
PIN_J3_47 152
{3,49,153},
{3,51,154},
{3,53,155},
153 #define
154 #define
155 #define
156 #define
157 #define
PIN_J3_49 153
PIN_J3_51 154
PIN_J3_53 155
PIN_onewire 156
PIN_PLL_INT 157
XDC
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
T3 [get_ports RESET]
T19 [get_ports spi_ss_i_0]
P22 [get_ports spi_io0_i]
R22 [get_ports spi_io1_i]
P21 [get_ports spi_io2_i]
R21 [get_ports spi_io3_i]
H4 [get_ports sys_diff_clkp]
G4 [get_ports sys_diff_clkn]
U22 [get_ports sys_led]
W22 [get_ports led2]
W21 [get_ports iic_main0_scl_i]
T20 [get_ports iic_main0_sda_i]
F6 [get_ports mgt_diff_clkp]
E6 [get_ports mgt_diff_clkn]
P14 [get_ports RMII0_TXD0]
P15 [get_ports RMII0_TXD1]
R14 [get_ports RMII0_TXEN]
P20 [get_ports RMII0_CRSDV]
N13 [get_ports RMII0_RXD0]
N14 [get_ports RMII0_RXD1]
P17 [get_ports PHY0_MDIO]
R16 [get_ports PHY0_MDC]
N17 [get_ports phy_rst_out]
Y21 [get_ports J1_91]
AA13 [get_ports J1_17]
AB13 [get_ports J1_19]
W14 [get_ports J1_18]
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

V22 [get_ports onewire]
B2 [get_ports PLL_INT]
part0_pins.xml
<?xml version="1.0" encoding="UTF-8" standalone="no"?><part_info part_name="xc7a100tfgg484<pin index="0" name="RESET" iostandard="LVCMOS15" loc="T3"/>
<pin index="1" name="spi_ss_i_0" iostandard="LVCMOS33" loc="T19"/>
<pin index="2" name="spi_io0_i" iostandard="LVCMOS33" loc="P22"/>
<pin index="3" name="spi_io1_i" iostandard="LVCMOS33" loc="R22"/>
<pin index="4" name="spi_io2_i" iostandard="LVCMOS33" loc="P21"/>
<pin index="5" name="spi_io3_i" iostandard="LVCMOS33" loc="R21"/>
<pin index="6" name="sys_diff_clkp" iostandard="LVCOMS15" loc="H4"/>
<pin index="7" name="sys_diff_clkn" iostandard="LVCMOS15" loc="G4"/>
<pin index="8" name="sys_led" iostandard="LVCMOS33" loc="U22"/>
<pin index="9" name="led2" iostandard="LVCMOS33" loc="W22"/>
<pin index="10" name="iic_main0_scl_i" iostandard="LVCMOS33" loc="W21"/>
<pin index="11" name="iic_main0_sda_i" iostandard="LVCMOS33" loc="T20"/>
<pin index="12" name="mgt_diff_clkp" iostandard="LVCMOS33" loc="F6"/>
<pin index="13" name="mgt_diff_clkn" iostandard="LVCMOS33" loc="E6"/>
<pin index="14" name="RMII0_TXD0" iostandard="LVCMOS33" loc="P14"/>
<pin index="15" name="RMII0_TXD1" iostandard="LVCMOS33" loc="P15"/>
<pin index="16" name="RMII0_TXEN" iostandard="LVCMOS33" loc="R14"/>
<pin index="17" name="RMII0_CRSDV" iostandard="LVCMOS33" loc="P20"/>
<pin index="18" name="RMII0_RXD0" iostandard="LVCMOS33" loc="N13"/>
<pin index="19" name="RMII0_RXD1" iostandard="LVCMOS33" loc="N14"/>
<pin index="20" name="PHY0_MDIO" iostandard="LVCMOS33" loc="P17"/>
<pin index="21" name="PHY0_MDC" iostandard="LVCMOS33" loc="R16"/>
<pin index="22" name="phy_rst_out" iostandard="LVCMOS33" loc="N17"/>
<pin index="23" name="J1_87" iostandard="LVCMOS33" loc="U17"/>
<pin index="24" name="J1_91" iostandard="LVCMOS33" loc="Y21"/>
<pin index="25" name="J1_95" iostandard="LVCMOS33" loc="T21"/>
<pin index="29" name="J1_92" iostandard="LVCMOS33" loc="P16"/>
<pin index="31" name="J1_17" loc="AA13"/>
<pin index="32" name="J1_19" loc="AB13"/>
<pin index="33" name="J1_21" loc="Y12"/>
<pin index="38" name="J1_18" loc="W14"/>
<pin index="41" name="J1_31" loc="E22"/>
<pin index="42" name="J1_33" loc="D22"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="43"
index="44"
index="45"
index="46"
index="47"
index="48"
index="49"
index="50"
index="51"
index="52"
index="53"
index="54"
index="55"
index="56"
index="57"
index="58"
index="59"
index="60"
index="61"
index="62"
index="63"
index="64"
index="65"
index="66"
index="67"
index="68"
index="69"
index="70"
index="71"
index="72"
index="73"
index="74"
index="75"
index="76"
index="77"
index="78"
index="79"
index="80"
index="81"
index="82"
index="83"
index="84"
index="85"
index="86"
index="87"
name="J1_35"
name="J1_37"
name="J1_41"
name="J1_43"
name="J1_45"
name="J1_47"
name="J1_49"
name="J1_51"
name="J1_55"
name="J1_57"
name="J1_59"
name="J1_61"
name="J1_65"
name="J1_67"
name="J1_69"
name="J1_71"
name="J1_75"
name="J1_77"
name="J1_81"
name="J1_83"
name="J1_36"
name="J1_38"
name="J1_40"
name="J1_42"
name="J1_46"
name="J1_48"
name="J1_50"
name="J1_52"
name="J1_56"
name="J1_58"
name="J1_60"
name="J1_62"
name="J1_66"
name="J1_68"
name="J1_70"
name="J1_72"
name="J1_76"
name="J1_78"
name="J1_80"
name="J1_82"
name="J1_86"
name="J1_88"
name="J1_94"
name="J1_96"
name="J1_98"
loc="G22"/>
loc="G21"/>
loc="E21"/>
loc="D21"/>
loc="F18"/>
loc="E18"/>
loc="C22"/>
loc="B22"/>
loc="B21"/>
loc="A21"/>
loc="C18"/>
loc="C19"/>
loc="E19"/>
loc="D19"/>
loc="C15"/>
loc="C14"/>
loc="D17"/>
loc="C17"/>
loc="B13"/>
loc="C13"/>
loc="B20"/>
loc="A20"/>
loc="C20"/>
loc="D20"/>
loc="A19"/>
loc="A18"/>
loc="F20"/>
loc="F19"/>
loc="A16"/>
loc="A15"/>
loc="B16"/>
loc="B15"/>
loc="B17"/>
loc="B18"/>
loc="A14"/>
loc="A13"/>
loc="D16"/>
loc="E16"/>
loc="E17"/>
loc="F16"/>
loc="D15"/>
loc="D14"/>
loc="E14"/>
loc="E13"/>
loc="F14"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="88" name="J1_100" loc="F13"/>

index="89" name="J2_11" iostandard="LVCMOS33" loc="AA21"/>
index="91" name="J2_15" iostandard="LVCMOS33" loc="AB18"/>
index="95" name="J2_25" iostandard="LVCMOS33" loc="Y18"/>
index="98" name="J2_33" iostandard="LVCMOS33" loc="W17"/>
index="107" name="J2_41" loc="L16"/>
index="108" name="J2_43" loc="K16"/>
index="109" name="J2_45" loc="K13"/>
index="110" name="J2_47" loc="K14"/>
index="111" name="J2_51" loc="J20"/>
index="112" name="J2_53" loc="J21"/>
index="113" name="J2_55" loc="J14"/>
index="114" name="J2_57" loc="H14"/>
index="115" name="J2_61" loc="N19"/>
index="116" name="J2_63" loc="N18"/>
index="117" name="J2_65" loc="M18"/>
index="118" name="J2_67" loc="L18"/>
index="119" name="J2_71" loc="H13"/>
index="120" name="J2_73" loc="G13"/>
index="121" name="J2_75" loc="G16"/>
index="122" name="J2_77" loc="G15"/>
index="123" name="J2_81" loc="G17"/>
index="124" name="J2_83" loc="G18"/>
index="125" name="J2_85" loc="H15"/>
index="126" name="J2_87" loc="J15"/>
index="127" name="J2_32" loc="K22"/>
index="128" name="J2_34" loc="K21"/>
index="129" name="J2_36" loc="G20"/>
index="130" name="J2_38" loc="H20"/>
index="131" name="J2_42" loc="H22"/>
index="132" name="J2_44" loc="J22"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="133"
index="134"
index="135"
index="136"
index="137"
index="138"
index="139"
index="140"
index="141"
index="142"
index="143"
index="144"
index="145"
index="146"
index="147"
index="148"
index="149"
index="150"
index="151"
index="152"
index="153"
index="154"
index="155"
index="156"
index="157"
index="158"
index="159"
index="160"
index="161"
index="162"
index="163"
index="164"
index="165"
index="166"
index="167"
index="168"
index="169"
index="170"
index="171"
index="172"
index="173"
index="174"
index="175"
index="176"
index="177"
name="J2_46" loc="K18"/>
name="J2_48" loc="K19"/>
name="J2_52" loc="L19"/>
name="J2_54" loc="L20"/>
name="J2_56" loc="J19"/>
name="J2_58" loc="H19"/>
name="J2_62" loc="L21"/>
name="J2_64" loc="M21"/>
name="J2_66" loc="N20"/>
name="J2_68" loc="M20"/>
name="J2_72" loc="M13"/>
name="J2_74" loc="L13"/>
name="J2_76" loc="N22"/>
name="J2_78" loc="M22"/>
name="J2_82" loc="H18"/>
name="J2_84" loc="H17"/>
name="J2_86" loc="K17"/>
name="J2_88" loc="J17"/>
name="J2_92" loc="M16"/>
name="J2_94" loc="M15"/>
name="J2_96" loc="L15"/>
name="J2_98" loc="L14"/>
name="J2_100" loc="M17"/>
name="J2_89" loc="J16"/>
name="J3_1" loc="T16"/>
name="J3_3" loc="U16"/>
name="J3_37" loc="V10"/>
name="J3_39" loc="W10"/>
name="J3_41" loc="T14"/>
name="J3_43" loc="T15"/>
name="J3_57" loc="V13"/>
name="J3_59" loc="V14"/>
name="J3_2" loc="U15"/>
name="J3_4" loc="V15"/>
name="J3_38" loc="W15"/>
name="J3_40" loc="W16"/>
name="J3_42" loc="Y16"/>
name="J3_44" loc="AA16"/>
name="J3_50" loc="AB15"/>
name="J3_58" loc="W11"/>
name="J3_60" loc="W12"/>
<pin
<pin
<pin
<pin
<pin
index="178"
index="179"
index="180"
index="181"
index="182"

name="onewire" iostandard="LVCMOS33" loc="V22"/>
name="PLL_INT" iostandard="LVCMOS15" loc="B2"/>
name/first
width
reset
0
29
30
10
11
12
13
14
19
20
21
spi_flash
sys_diff_clock
leds
sys_led
led2
uart0
iic_main0
mgt1_diff_clock
rmii0
mdio_io0
phy_reset_out
22
22
23
30
23
28
41
22
62
21
63
26
88
25
31
10
40
107
20
126
19
127
30
156
29
89
18
106
17
157
20
176
19
177
180
p0
p0_6bits
p1a
p1b
p1c
p2a
p2b
p2c
p3a
p3b
<connections>

<connection_map name="part0_reset_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_
</connection>

</connection>
<connection name="part0_sys_diff_clock" component1="part0" component2="sys_diff_clock">

<connection_map name="part0_sys_diff_clock_1" c1_st_index="6" c1_end_index="7" c2_st_index
</connection>

<connection_map name="part0_leds_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_e
</connection>
<connection name="part0_sys_led" component1="part0" component2="sys_led">

<connection_map name="part0_sys_led_1" c1_st_index="8" c1_end_index="8" c2_st_index="0" c
</connection>
<connection name="part0_led2" component1="part0" component2="led2">

<connection_map name="part0_led2_1" c1_st_index="9" c1_end_index="9" c2_st_index="0" c2_
</connection>
<connection_map name="part0_uart0_1" c1_st_index="29" c1_end_index="30" c2_st_index="0"
</connection>
<connection name="part0_iic_main0" component1="part0" component2="iic_main0">

<connection_map name="part0_iic_main0_1" c1_st_index="10" c1_end_index="11" c2_st_index=
</connection>
<connection name="part0_mgt1_diff_clock" component1="part0" component2="mgt1_diff_clock">

<connection_map name="part0_mgt1_diff_clock_1" c1_st_index="12" c1_end_index="13" c2_st_i
</connection>
<connection name="part0_rmii0" component1="part0" component2="rmii0">

<connection_map name="part0_rmii0_1" c1_st_index="14" c1_end_index="19" c2_st_index="0" c
</connection>

</connection>
<connection name="part0_phy_reset_out" component1="part0" component2="phy_reset_out">

<connection_map name="part0_phy_reset_out_1" c1_st_index="22" c1_end_index="22" c2_st_ind
</connection>

</connection>

<connection_map name="part0_p0_6bits_1" c1_st_index="23" c1_end_index="28" c2_st_index="
</connection>

</connection>

</connection>

</connection>

</connection>

</connection>

<connection_map name="part0_p2c_1" c1_st_index="89" c1_end_index="106" c2_st_index="0" c
</connection>

</connection>

</connection>

<connection_map name="part0_asio_2" c1_st_index="31" c1_end_index="182" c2_st_index="6"
</connection>
p0
0
1
2
3
4
5
6
7
8
J1_87
J1_91
J1_95
J1_93
J1_99
J1_97
J1_92
J1_85
p0_6bits
0
1
2
3
4
5
6
J1_87
J1_91
J1_95
J1_93
J1_99
J1_97
p1a
0
22
J1_31
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
J1_47
J1_49
J1_51
J1_55
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
J1_83
p1b
0
26
J1_36
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J1_38
J1_40
J1_42
J1_46
J1_48
J1_50
J1_52
J1_56
J1_58
J1_60
J1_62
J1_66
J1_68
J1_70
J1_72
J1_76
J1_78
J1_80
J1_82
J1_86
J1_88
J1_94
J1_96
J1_98
J1_100
p1c
0
1
2
3
4
5
6
7
8
9
10
J1_17
J1_19
J1_21
J1_23
J1_25
J1_27
J1_16
J1_18
J1_22
J1_24
p2a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
J2_41
J2_43
J2_45
J2_47
J2_51
J2_53
J2_55
J2_57
J2_61
J2_63
J2_65
J2_67
J2_71
J2_73
J2_75
J2_77
J2_81
J2_83
J2_85
J2_87
19
p2b
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
J2_32
J2_34
J2_36
J2_38
J2_42
J2_44
J2_46
J2_48
J2_52
J2_54
J2_56
J2_58
J2_62
J2_64
J2_66
J2_68
J2_72
J2_74
J2_76
J2_78
J2_82
J2_84
J2_86
J2_88
J2_92
J2_94
J2_96
J2_98
J2_100
J2_89
29
p2c
0
1
2
3
4
5
6
7
18
J2_11
J2_13
J2_15
J2_17
J2_21
J2_23
J2_25
J2_27
17
8
9
10
11
12
13
14
15
16
17
J2_31
J2_33
J2_35
J2_37
J2_14
J2_16
J2_22
J2_24
J2_26
J2_28
p3a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
J3_1
J3_3
J3_37
J3_39
J3_41
J3_43
J3_57
J3_59
J3_2
J3_4
J3_38
J3_40
J3_42
J3_44
J3_48
J3_50
J3_52
J3_54
J3_58
J3_60
19
p3b
0
1
2
3
4
J3_47
J3_49
J3_51
J3_53
asio
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
160
J1_87
J1_91
J1_95
J1_93
J1_99
J1_97
J1_17
J1_19
J1_21
J1_23
J1_25
J1_27
J1_16
J1_18
J1_22
J1_24
J1_31
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
J1_47
J1_49
J1_51
J1_55
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
159
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
J1_83
J1_36
J1_38
J1_40
J1_42
J1_46
J1_48
J1_50
J1_52
J1_56
J1_58
J1_60
J1_62
J1_66
J1_68
J1_70
J1_72
J1_76
J1_78
J1_80
J1_82
J1_86
J1_88
J1_94
J1_96
J1_98
J1_100
J2_11
J2_13
J2_15
J2_17
J2_21
J2_23
J2_25
J2_27
J2_31
J2_33
J2_35
J2_37
J2_14
J2_16
J2_22
J2_24
J2_26
J2_28
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
J2_41
J2_43
J2_45
J2_47
J2_51
J2_53
J2_55
J2_57
J2_61
J2_63
J2_65
J2_67
J2_71
J2_73
J2_75
J2_77
J2_81
J2_83
J2_85
J2_87
J2_32
J2_34
J2_36
J2_38
J2_42
J2_44
J2_46
J2_48
J2_52
J2_54
J2_56
J2_58
J2_62
J2_64
J2_66
J2_68
J2_72
J2_74
J2_76
J2_78
J2_82
J2_84
J2_86
J2_88
J2_92
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
J2_94
J2_96
J2_98
J2_100
J2_89
J3_1
J3_3
J3_37
J3_39
J3_41
J3_43
J3_57
J3_59
J3_2
J3_4
J3_38
J3_40
J3_42
J3_44
J3_48
J3_50
J3_52
J3_54
J3_58
J3_60
J3_47
J3_49
J3_51
J3_53
onewire
PLL_INT
sys_led
led2
<interface mode="master" name="p0" type="xilinx.com:interface:gpio_rtl:1.0" of_component

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p0_tri_o" dir="out" left="7" right="0">
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p0_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_comp

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p0_6bits_tri_o" dir="out" left="5" right="
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p0_6bits_tri_t" dir="out" left="5" right="
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="p0_6bits_tri_i" dir="in" left="5" right="0">
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p1c" type="xilinx.com:interface:gpio_rtl:1.0" of_componen

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p1c_tri_o" dir="out" left="9" right="0">
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p1c_tri_t" dir="out" left="9" right="0">
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="30"
port_index="31"
port_index="32"
port_index="33"
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map

<pin_map port_index="156" component_pin="onewire"/>
<pin_map port_index="157" component_pin="PLL_INT"/>
</pin_maps>
</port_map>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
port_index="82"
port_index="83"
port_index="84"
port_index="85"
port_index="86"
port_index="87"
port_index="88"
port_index="89"
port_index="90"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map

<pin_map port_index="156" component_pin="onewire"/>
<pin_map port_index="157" component_pin="PLL_INT"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="asio_tri_i" dir="in" left="159" right="0">
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="17"
port_index="18"
port_index="19"
port_index="20"
port_index="21"
port_index="22"
port_index="23"
port_index="24"
port_index="25"
port_index="26"
port_index="27"
port_index="28"
port_index="29"
port_index="30"
port_index="31"
port_index="32"
port_index="33"
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="107"
port_index="108"
port_index="109"
port_index="110"
port_index="111"
port_index="112"
port_index="113"
port_index="114"
port_index="115"
port_index="116"
port_index="117"
port_index="118"
port_index="119"
port_index="120"
port_index="121"
port_index="122"
port_index="123"
port_index="124"
port_index="125"
port_index="126"
port_index="127"
port_index="128"
port_index="129"
port_index="130"
port_index="131"
port_index="132"
port_index="133"
port_index="134"
port_index="135"
port_index="136"
port_index="137"
port_index="138"
port_index="139"
port_index="140"
port_index="141"
port_index="142"
port_index="143"
port_index="144"
port_index="145"
port_index="146"
port_index="147"
port_index="148"
port_index="149"
port_index="150"
port_index="151"
</pin_maps>
</port_map>
</port_maps>
</interface>
component_pin="onewire"/>
component_pin="PLL_INT"/>
component_pin="sys_led"/>
component_pin="led2"/>
Index
Name
0 J1_31
1 J1_33
2 J1_35
3 J1_37
4 J1_41
5 J1_43
6 J1_45
7 J1_47
8 J1_49
9 J1_51
10 J1_55
11 J1_57
12 J1_59
13 J1_61
14 J1_65
15 J1_67
16 J1_69
17 J1_71
18 J1_75
19 J1_77
20 J1_81
21 J1_83
22 J1_36
23 J1_38
24 J1_40
25 J1_42
26 J1_46
27 J1_48
28 J1_50
29 J1_52
30 J1_56
31 J1_58
32 J1_60
33 J1_62
34 J1_66
35 J1_68
36 J1_70
37 J1_72
38 J1_76
39 J1_78
40 J1_80
41 J1_82
42 J1_86
43 J1_88
44 J1_94
45 J1_96
iostandard
LVCMOS18
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
loc
bank
W12
W13
U11
U12
V15
W15
R17
T17
V13
V14
AB13
AB14
Y15
Y14
AA15
AA14
AB16
AB17
Y19
Y18
AB18
AB19
U13
U14
V11
W11
AA11
AB11
AA12
AB12
Y12
Y13
V16
W16
AA17
AA16
Y17
W17
AA19
AA20
W18
V18
V19
U19
AB21
AB22
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
31
33
35
37
41
43
45
47
49
51
55
57
59
61
65
67
69
71
75
77
81
83
36
38
40
42
46
48
50
52
56
58
60
62
66
68
70
72
76
78
80
82
86
88
94
96
46 J1_98
47 J1_100
48 J2_11
49 J2_13
50 J2_15
51 J2_17
52 J2_21
53 J2_23
54 J2_25
55 J2_27
56 J2_31
57 J2_33
58 J2_35
59 J2_37
60 J2_14
61 J2_16
62 J2_22
63 J2_24
64 J2_26
65 J2_28
66 J2_41
67 J2_43
68 J2_45
69 J2_47
70 J2_51
71 J2_53
72 J2_55
73 J2_57
74 J2_61
75 J2_63
76 J2_65
77 J2_67
78 J2_71
79 J2_73
80 J2_75
81 J2_77
82 J2_81
83 J2_83
84 J2_85
85 J2_87
86 J2_32
87 J2_34
88 J2_36
89 J2_38
90 J2_42
91 J2_44
92 J2_46
93 J2_48
LVCMOS33
LVCMOS33
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
U17
U18
R3
R2
P3
P2
K4
K3
L5
L4
J2
J1
J5
K5
M1
M2
J7
J6
M7
M8
E3
E4
B6
B7
C6
C5
E7
F7
D8
E8
C8
B8
G7
G8
H3
H4
E5
F5
F6
G6
D1
C1
B1
B2
A1
A2
B4
B3
B13
B13
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
98
100
11
13
15
17
21
23
25
27
31
33
35
37
14
16
22
24
26
28
41
43
45
47
51
53
55
57
61
63
65
67
71
73
75
77
81
83
85
87
32
34
36
38
42
44
46
48
94 J2_52
95 J2_54
96 J2_56
97 J2_58
98 J2_62
99 J2_64
100 J2_66
101 J2_68
102 J2_72
103 J2_74
104 J2_76
105 J2_78
106 J2_82
107 J2_84
108 J2_86
109 J2_88
110 J2_92
111 J2_94
112 J2_96
113 J2_98
114 J2_100
115 J2_89
116 J3_37
117 J3_39
118 J3_41
119 J3_43
120 J3_57
121 J3_59
122 J3_38
123 J3_40
124 J3_42
125 J3_44
126 J3_48
127 J3_50
128 J3_52
129 J3_54
130 J3_58
131 J3_60
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
D3
C3
D5
C4
F1
F2
D6
D7
E2
D2
H1
G1
A6
A7
G2
G3
A4
A5
F4
G4
H5
H6
P6
P5
N4
N3
T2
T1
R5
R4
N1
P1
L2
L1
M4
M3
U2
U1
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
52
54
56
58
62
64
66
68
72
74
76
78
82
84
86
88
92
94
96
98
100
89
37
39
41
43
57
59
38
40
42
44
48
50
52
54
58
60
XDC
{1,31,0},
{1,33,1},
{1,35,2},
{1,37,3},
{1,41,4},
{1,43,5},
{1,45,6},
{1,47,7},
{1,49,8},
{1,51,9},
{1,55,10},
{1,57,11},
{1,59,12},
{1,61,13},
{1,65,14},
{1,67,15},
{1,69,16},
{1,71,17},
{1,75,18},
{1,77,19},
{1,81,20},
{1,83,21},
{1,36,22},
{1,38,23},
{1,40,24},
{1,42,25},
{1,46,26},
{1,48,27},
{1,50,28},
{1,52,29},
{1,56,30},
{1,58,31},
{1,60,32},
{1,62,33},
{1,66,34},
{1,68,35},
{1,70,36},
{1,72,37},
{1,76,38},
{1,78,39},
{1,80,40},
{1,82,41},
{1,86,42},
{1,88,43},
{1,94,44},
{1,96,45},
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

{1,98,46},
{1,100,47},
{2,11,48},
{2,13,49},
{2,15,50},
{2,17,51},
{2,21,52},
{2,23,53},
{2,25,54},
{2,27,55},
{2,31,56},
{2,33,57},
{2,35,58},
{2,37,59},
{2,14,60},
{2,16,61},
{2,22,62},
{2,24,63},
{2,26,64},
{2,28,65},
{2,41,66},
{2,43,67},
{2,45,68},
{2,47,69},
{2,51,70},
{2,53,71},
{2,55,72},
{2,57,73},
{2,61,74},
{2,63,75},
{2,65,76},
{2,67,77},
{2,71,78},
{2,73,79},
{2,75,80},
{2,77,81},
{2,81,82},
{2,83,83},
{2,85,84},
{2,87,85},
{2,32,86},
{2,34,87},
{2,36,88},
{2,38,89},
{2,42,90},
{2,44,91},
{2,46,92},
{2,48,93},
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

{2,52,94},
{2,54,95},
{2,56,96},
{2,58,97},
{2,62,98},
{2,64,99},
{2,66,100},
{2,68,101},
{2,72,102},
{2,74,103},
{2,76,104},
{2,78,105},
{2,82,106},
{2,84,107},
{2,86,108},
{2,88,109},
{2,92,110},
{2,94,111},
{2,96,112},
{2,98,113},
{2,100,114},
{2,89,115},
{3,37,116},
{3,39,117},
{3,41,118},
{3,43,119},
{3,57,120},
{3,59,121},
{3,38,122},
{3,40,123},
{3,42,124},
{3,44,125},
{3,48,126},
{3,50,127},
{3,52,128},
{3,54,129},
{3,58,130},
{3,60,131},
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
part0_pins.xml
<?xml version="1.0" encoding="UTF-8" standalone="no"?><part_info part_name="xc7z030sbg48
<pin index="0" name="J1_31" iostandard="LVCMOS33" loc="W12"/>
<pin index="4" name="J1_41" iostandard="LVCMOS33" loc="V15"/>
<pin index="7" name="J1_47" iostandard="LVCMOS33" loc="T17"/>
<pin index="10" name="J1_55" iostandard="LVCMOS33" loc="AB13"/>
<pin index="14" name="J1_65" iostandard="LVCMOS33" loc="AA15"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="46"
index="47"
index="48"
index="49"
index="50"
index="51"
index="52"
index="53"
index="54"
index="55"
index="56"
index="57"
index="58"
index="59"
index="60"
index="61"
index="62"
index="63"
index="64"
index="65"
index="66"
index="67"
index="68"
index="69"
index="70"
index="71"
index="72"
index="73"
index="74"
index="75"
index="76"
index="77"
index="78"
index="79"
index="80"
index="81"
index="82"
index="83"
index="84"
index="85"
index="86"
index="87"
index="88"
index="89"
index="90"
index="91"
index="92"
index="93"

<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin

index="120" name="J3_57" iostandard="LVCMOS18" loc="T2"/>
index="122" name="J3_38" iostandard="LVCMOS18" loc="R5"/>
index="126" name="J3_48" iostandard="LVCMOS18" loc="L2"/>
index="128" name="J3_52" iostandard="LVCMOS18" loc="M4"/>
name/first
width
p1a
0
22
21
21
22
26
47
25
66
20
85
19
86
30
115
29
48
18
65
17
116
16
131
15
p1b
p2a
P2b
P2c
P3
<connections>
</connection>

<connection_map name="part0_p1b_1" c1_st_index="22" c1_end_index="47" c2_st_index="0
</connection>

<connection_map name="part0_p2a_1" c1_st_index="66" c1_end_index="85" c2_st_index="0
</connection>
<connection name="part0_P2b" component1="part0" component2="P2b">

<connection_map name="part0_P2b_1" c1_st_index="86" c1_end_index="115" c2_st_index="
</connection>
<connection name="part0_P2c" component1="part0" component2="P2c">

<connection_map name="part0_P2c_1" c1_st_index="48" c1_end_index="65" c2_st_index="0"
</connection>
<connection name="part0_P3" component1="part0" component2="P3">

<connection_map name="part0_P3_1" c1_st_index="116" c1_end_index="131" c2_st_index="
</connection>
p1a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
J1_31
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
J1_47
J1_49
J1_51
J1_55
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
J1_83
21
p1b
26
0 J1_36
1 J1_38
2 J1_40
3 J1_42
4 J1_46
5 J1_48
25
6 J1_50
7 J1_52
8 J1_56
9 J1_58
10 J1_60
11 J1_62
12 J1_66
13 J1_68
14 J1_70
15 J1_72
16 J1_76
17 J1_78
18 J1_80
19 J1_82
20 J1_86
21 J1_88
22 J1_94
23 J1_96
24 J1_98
25 J1_100
p2a
20
0 J2_41
1 J2_43
19
2 J2_45
3 J2_47
4 J2_51
5 J2_53
6 J2_55
7 J2_57
8 J2_61
9 J2_63
10 J2_65
11 J2_67
12 J2_71
13 J2_73
14 J2_75
15 J2_77
16 J2_81
17 J2_83
18 J2_85
19 J2_87
p2b
30
0 J2_32
1 J2_34
2 J2_36
3 J2_38
4 J2_42
5 J2_44
6 J2_46
7 J2_48
8 J2_52
9 J2_54
10 J2_56
11 J2_58
12 J2_62
13 J2_64
14 J2_66
29
15 J2_68
16 J2_72
17 J2_74
18 J2_76
19 J2_78
20 J2_82
21 J2_84
22 J2_86
23 J2_88
24 J2_92
25 J2_94
26 J2_96
27 J2_98
28 J2_100
29 J2_89
p2c
18
0 J2_11
1 J2_13
2 J2_15
3 J2_17
4 J2_21
5 J2_23
6 J2_25
7 J2_27
8 J2_31
9 J2_33
10 J2_35
11 J2_37
12 J2_14
13 J2_16
14 J2_22
15 J2_24
16 J2_26
17 J2_28
17
p3
16
0 J3_37
1 J3_39
2 J3_41
3 J3_43
4 J3_57
5 J3_59
6 J3_38
7 J3_40
8 J3_42
9 J3_44
10 J3_48
11 J3_50
12 J3_52
13 J3_54
14 J3_58
15 J3_60
15
asio
132
0 J1_31
1 J1_33
2 J1_35
3 J1_37
4 J1_41
5 J1_43
6 J1_45
7 J1_47
8 J1_49
9 J1_51
10 J1_55
11 J1_57
12 J1_59
13 J1_61
14 J1_65
15 J1_67
16 J1_69
17 J1_71
18 J1_75
19 J1_77
20 J1_81
21 J1_83
22 J1_36
23 J1_38
24 J1_40
25 J1_42
26 J1_46
27 J1_48
28 J1_50
29 J1_52
30 J1_56
31 J1_58
32 J1_60
33 J1_62
34 J1_66
35 J1_68
36 J1_70
37 J1_72
38 J1_76
39 J1_78
40 J1_80
41 J1_82
42 J1_86
43 J1_88
131
44 J1_94
45 J1_96
46 J1_98
47 J1_100
48 J2_11
49 J2_13
50 J2_15
51 J2_17
52 J2_21
53 J2_23
54 J2_25
55 J2_27
56 J2_31
57 J2_33
58 J2_35
59 J2_37
60 J2_14
61 J2_16
62 J2_22
63 J2_24
64 J2_26
65 J2_28
66 J2_41
67 J2_43
68 J2_45
69 J2_47
70 J2_51
71 J2_53
72 J2_55
73 J2_57
74 J2_61
75 J2_63
76 J2_65
77 J2_67
78 J2_71
79 J2_73
80 J2_75
81 J2_77
82 J2_81
83 J2_83
84 J2_85
85 J2_87
86 J2_32
87 J2_34
88 J2_36
89 J2_38
90 J2_42
91 J2_44
92 J2_46
93 J2_48
94 J2_52
95 J2_54
96 J2_56
97 J2_58
98 J2_62
99 J2_64
100 J2_66
101 J2_68
102 J2_72
103 J2_74
104 J2_76
105 J2_78
106 J2_82
107 J2_84
108 J2_86
109 J2_88
110 J2_92
111 J2_94
112 J2_96
113 J2_98
114 J2_100
115 J2_89
116 J3_37
117 J3_39
118 J3_41
119 J3_43
120 J3_57
121 J3_59
122 J3_38
123 J3_40
124 J3_42
125 J3_44
126 J3_48
127 J3_50
128 J3_52
129 J3_54
130 J3_58
131 J3_60

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>

</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p2c_tri_t" dir="out" left="17" right="
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p3_tri_o" dir="out" left="15" right="0
<pin_maps>

</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p3_tri_t" dir="out" left="15" right="0
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
port_index="82"
port_index="83"
port_index="84"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
</pin_maps>
</port_map>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
port_index="82"
port_index="83"
port_index="84"
port_index="85"
port_index="86"
port_index="87"
port_index="88"
port_index="89"

</pin_maps>
</port_map>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
port_index="82"
port_index="83"
port_index="84"
port_index="85"
port_index="86"
port_index="87"
port_index="88"
port_index="89"
port_index="90"
port_index="91"
port_index="92"
port_index="93"
port_index="94"
port_index="95"
port_index="96"
port_index="97"

</pin_maps>
</port_map>
</port_maps>
</interface>
Index
Name
0 J1_31
1 J1_33
2 J1_35
3 J1_37
4 J1_41
5 J1_43
6 J1_45
7 J1_47
8 J1_49
9 J1_51
10 J1_55
11 J1_57
12 J1_59
13 J1_61
14 J1_65
15 J1_67
16 J1_69
17 J1_71
18 J1_75
19 J1_77
20 J1_81
21 J1_83
22 J1_36
23 J1_38
24 J1_40
25 J1_42
26 J1_46
27 J1_48
28 J1_50
29 J1_52
30 J1_56
31 J1_58
32 J1_60
33 J1_62
34 J1_66
35 J1_68
36 J1_70
37 J1_72
38 J1_76
39 J1_78
40 J1_80
41 J1_82
42 J1_86
iostandard
loc
bank
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
C22
D22
G22
H22
B22
B21
A22
A21
G21
G20
D21
E21
B20
B19
C20
D20
G16
G15
C19
D18
F19
G19
A19
A18
A17
A16
B15
C15
D17
D16
B17
B16
E20
E19
C18
C17
F22
F21
E18
F18
D15
E15
F17
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
B35
31
33
35
37
41
43
45
47
49
51
55
57
59
61
65
67
69
71
75
77
81
83
36
38
40
42
46
48
50
52
56
58
60
62
66
68
70
72
76
78
80
82
86
43 J1_88
44 J1_94
45 J1_96
46 J1_98
47 J1_100
48 J2_11
49 J2_13
50 J2_15
51 J2_17
52 J2_21
53 J2_23
54 J2_25
55 J2_27
56 J2_31
57 J2_33
58 J2_35
59 J2_37
60 J2_14
61 J2_16
62 J2_22
63 J2_24
64 J2_26
65 J2_28
66 J2_41
67 J2_43
68 J2_45
69 J2_47
70 J2_51
71 J2_53
72 J2_55
73 J2_57
74 J2_61
75 J2_63
76 J2_65
77 J2_67
78 J2_71
79 J2_73
80 J2_75
81 J2_77
82 J2_81
83 J2_83
84 J2_85
85 J2_87
86 J2_32
87 J2_34
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
G17
E16
F16
H20
H19
AA22
AB22
AA21
AB21
Y19
AA19
Y18
AA18
AA17
AB17
AA16
AB16
W20
W21
W17
W18
W16
Y16
AA12
AB12
AA11
AB11
AA9
AA8
AB10
AB9
T4
U4
AB7
AB6
AB5
AB4
Y4
AA4
AB2
AB1
V5
V4
U12
U11
B35
B35
B35
B35
B35
B33
B33
B33
B33
B33
B33
B33
B33
B33
B33
B33
B33
B33
B33
B33
B33
B33
B33
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
88
94
96
98
100
11
13
15
17
21
23
25
27
31
33
35
37
14
16
22
24
26
28
41
43
45
47
51
53
55
57
61
63
65
67
71
73
75
77
81
83
85
87
32
34
88 J2_36
89 J2_38
90 J2_42
91 J2_44
92 J2_46
93 J2_48
94 J2_52
95 J2_54
96 J2_56
97 J2_58
98 J2_62
99 J2_64
100 J2_66
101 J2_68
102 J2_72
103 J2_74
104 J2_76
105 J2_78
106 J2_82
107 J2_84
108 J2_86
109 J2_88
110 J2_92
111 J2_94
112 J2_96
113 J2_98
114 J2_100
115 J2_89
116 J3_7
117 J3_9
118 J3_13
119 J3_15
120 J3_19
121 J3_21
122 J3_25
123 J3_27
124 J3_31
125 J3_33
126 J3_37
127 J3_39
128 J3_41
129 J3_43
130 J3_57
131 J3_59
132 J3_8
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
U10
U9
V10
V9
Y9
Y8
AA7
AA6
Y6
Y5
V12
W12
W11
W10
Y11
Y10
V8
W8
V7
W7
W6
W5
R6
T6
U6
U5
R7
U7
J18
K18
J16
J17
L17
M17
N17
N18
L18
L19
J21
J22
J20
K21
R19
T19
J15
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
36
38
42
44
46
48
52
54
56
58
62
64
66
68
72
74
76
78
82
84
86
88
92
94
96
98
100
89
7
9
13
15
19
21
25
27
31
33
37
39
41
43
57
59
8
133 J3_10
134 J3_14
135 J3_16
136 J3_20
137 J3_22
138 J3_26
139 J3_28
140 J3_32
141 J3_34
142 J3_38
143 J3_40
144 J3_42
145 J3_44
146 J3_48
147 J3_50
148 J3_52
149 J3_54
150 J3_58
151 J3_60
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
K15
P20
P21
P17
P18
L21
L22
M19
M20
T16
T17
M21
M22
R20
R21
R18
T18
N19
N20
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
B34
10
14
16
20
22
26
28
32
34
38
40
42
44
48
50
52
54
58
60
{1,31,0},
{1,33,1},
{1,35,2},
{1,37,3},
{1,41,4},
{1,43,5},
{1,45,6},
{1,47,7},
{1,49,8},
{1,51,9},
{1,55,10},
{1,57,11},
{1,59,12},
{1,61,13},
{1,65,14},
{1,67,15},
{1,69,16},
{1,71,17},
{1,75,18},
{1,77,19},
{1,81,20},
{1,83,21},
{1,36,22},
{1,38,23},
{1,40,24},
{1,42,25},
{1,46,26},
{1,48,27},
{1,50,28},
{1,52,29},
{1,56,30},
{1,58,31},
{1,60,32},
{1,62,33},
{1,66,34},
{1,68,35},
{1,70,36},
{1,72,37},
{1,76,38},
{1,78,39},
{1,80,40},
{1,82,41},
{1,86,42},
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
{1,88,43},
{1,94,44},
{1,96,45},
{1,98,46},
{1,100,47},
{2,11,48},
{2,13,49},
{2,15,50},
{2,17,51},
{2,21,52},
{2,23,53},
{2,25,54},
{2,27,55},
{2,31,56},
{2,33,57},
{2,35,58},
{2,37,59},
{2,14,60},
{2,16,61},
{2,22,62},
{2,24,63},
{2,26,64},
{2,28,65},
{2,41,66},
{2,43,67},
{2,45,68},
{2,47,69},
{2,51,70},
{2,53,71},
{2,55,72},
{2,57,73},
{2,61,74},
{2,63,75},
{2,65,76},
{2,67,77},
{2,71,78},
{2,73,79},
{2,75,80},
{2,77,81},
{2,81,82},
{2,83,83},
{2,85,84},
{2,87,85},
{2,32,86},
{2,34,87},
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
{2,36,88},
{2,38,89},
{2,42,90},
{2,44,91},
{2,46,92},
{2,48,93},
{2,52,94},
{2,54,95},
{2,56,96},
{2,58,97},
{2,62,98},
{2,64,99},
{2,66,100},
{2,68,101},
{2,72,102},
{2,74,103},
{2,76,104},
{2,78,105},
{2,82,106},
{2,84,107},
{2,86,108},
{2,88,109},
{2,92,110},
{2,94,111},
{2,96,112},
{2,98,113},
{2,100,114}
{2,89,115},
{3,7,116},
{3,9,117},
{3,13,118},
{3,15,119},
{3,19,120},
{3,21,121},
{3,25,122},
{3,27,123},
{3,31,124},
{3,33,125},
{3,37,126},
{3,39,127},
{3,41,128},
{3,43,129},
{3,57,130},
{3,59,131},
{3,8,132},
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
{3,10,133},
{3,14,134},
{3,16,135},
{3,20,136},
{3,22,137},
{3,26,138},
{3,28,139},
{3,32,140},
{3,34,141},
{3,38,142},
{3,40,143},
{3,42,144},
{3,44,145},
{3,48,146},
{3,50,147},
{3,52,148},
{3,54,149},
{3,58,150},
{3,60,151},
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
XDC
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

part0_pins.xml
<?xml version="1.0" encoding="UTF-8" standalone="no"?><part_info part_name="xc7z020clg484-1
<pin index="1" name="J1_33" iostandard="LVCMOS33" loc="D22"/>
<pin index="11" name="J1_57" iostandard="LVCMOS33" loc="E21"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="43"
index="44"
index="45"
index="46"
index="47"
index="48"
index="49"
index="50"
index="51"
index="52"
index="53"
index="54"
index="55"
index="56"
index="57"
index="58"
index="59"
index="60"
index="61"
index="62"
index="63"
index="64"
index="65"
index="66"
index="67"
index="68"
index="69"
index="70"
index="71"
index="72"
index="73"
index="74"
index="75"
index="76"
index="77"
index="78"
index="79"
index="80"
index="81"
index="82"
index="83"
index="84"
index="85"
index="86"
index="87"

name="J2_11" iostandard="LVCMOS33" loc="AA22"/>
name="J2_13" iostandard="LVCMOS33" loc="AB22"/>
name="J2_21" iostandard="LVCMOS33" loc="Y19"/>
name="J2_14" iostandard="LVCMOS33" loc="W20"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin

<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="133"
index="134"
index="135"
index="136"
index="137"
index="138"
index="139"
index="140"
index="141"
index="142"
index="143"
index="144"
index="145"
index="146"
index="147"
index="148"
index="149"
index="150"
index="151"
name="J3_10"
name="J3_14"
name="J3_16"
name="J3_20"
name="J3_22"
name="J3_26"
name="J3_28"
name="J3_32"
name="J3_34"
name="J3_38"
name="J3_40"
name="J3_42"
name="J3_44"
name="J3_48"
name="J3_50"
name="J3_52"
name="J3_54"
name="J3_58"
name="J3_60"
loc="K15"/>
loc="P20"/>
loc="P21"/>
loc="P17"/>
loc="P18"/>
loc="L21"/>
loc="L22"/>
loc="M19"/>
loc="M20"/>
loc="T16"/>
loc="T17"/>
loc="M21"/>
loc="M22"/>
loc="R20"/>
loc="R21"/>
loc="R18"/>
loc="T18"/>
loc="N19"/>
loc="N20"/>
name/first
width
p1a
0
22
21
21
22
26
47
25
66
20
85
19
86
30
115
29
48
18
65
17
116
16
131
15
132
20
151
19
152
151
151
p1b
p2a
p2b
p2c
p3a
p3b
asio
<connections>

<connection_map name="part0_p1a_1" c1_st_index="0" c1_end_index="21" c2_st_index="0" c2_
</connection>

</connection>

</connection>

<connection_map name="part0_p2b_1" c1_st_index="86" c1_end_index="115" c2_st_index="0" c
</connection>

</connection>

</connection>

</connection>

</connection>
p1a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
J1_31
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
J1_47
J1_49
J1_51
J1_55
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
J1_83
21
p1b
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
J1_36
J1_38
J1_40
J1_42
J1_46
J1_48
J1_50
J1_52
J1_56
J1_58
J1_60
J1_62
J1_66
J1_68
J1_70
J1_72
J1_76
J1_78
J1_80
J1_82
J1_86
J1_88
J1_94
J1_96
J1_98
J1_100
25
p2a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
J2_41
J2_43
J2_45
J2_47
J2_51
J2_53
J2_55
J2_57
J2_61
J2_63
J2_65
J2_67
J2_71
J2_73
J2_75
J2_77
J2_81
J2_83
J2_85
J2_87
19
p2b
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
J2_32
J2_34
J2_36
J2_38
J2_42
J2_44
J2_46
J2_48
J2_52
J2_54
J2_56
J2_58
J2_62
J2_64
J2_66
J2_68
J2_72
J2_74
J2_76
J2_78
J2_82
J2_84
J2_86
J2_88
J2_92
J2_94
J2_96
J2_98
J2_100
J2_89
29
p2c
0
1
2
3
4
5
6
7
8
9
10
11
18
J2_11
J2_13
J2_15
J2_17
J2_21
J2_23
J2_25
J2_27
J2_31
J2_33
J2_35
J2_37
17
12
13
14
15
16
17
J2_14
J2_16
J2_22
J2_24
J2_26
J2_28
p3a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J3_7
J3_9
J3_13
J3_15
J3_19
J3_21
J3_25
J3_27
J3_31
J3_33
J3_37
J3_39
J3_41
J3_43
J3_57
J3_59
15
p3b
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
J3_8
J3_10
J3_14
J3_16
J3_20
J3_22
J3_26
J3_28
J3_32
J3_34
J3_38
J3_40
J3_42
J3_44
J3_48
J3_50
J3_52
J3_54
J3_58
J3_60
19
asio
0
152
J1_31
151
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
J1_47
J1_49
J1_51
J1_55
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
J1_83
J1_36
J1_38
J1_40
J1_42
J1_46
J1_48
J1_50
J1_52
J1_56
J1_58
J1_60
J1_62
J1_66
J1_68
J1_70
J1_72
J1_76
J1_78
J1_80
J1_82
J1_86
J1_88
J1_94
J1_96
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
J1_98
J1_100
J2_11
J2_13
J2_15
J2_17
J2_21
J2_23
J2_25
J2_27
J2_31
J2_33
J2_35
J2_37
J2_14
J2_16
J2_22
J2_24
J2_26
J2_28
J2_41
J2_43
J2_45
J2_47
J2_51
J2_53
J2_55
J2_57
J2_61
J2_63
J2_65
J2_67
J2_71
J2_73
J2_75
J2_77
J2_81
J2_83
J2_85
J2_87
J2_32
J2_34
J2_36
J2_38
J2_42
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
J2_44
J2_46
J2_48
J2_52
J2_54
J2_56
J2_58
J2_62
J2_64
J2_66
J2_68
J2_72
J2_74
J2_76
J2_78
J2_82
J2_84
J2_86
J2_88
J2_92
J2_94
J2_96
J2_98
J2_100
J2_89
J3_7
J3_9
J3_13
J3_15
J3_19
J3_21
J3_25
J3_27
J3_31
J3_33
J3_37
J3_39
J3_41
J3_43
J3_57
J3_59
J3_8
J3_10
J3_14
J3_16
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
J3_20
J3_22
J3_26
J3_28
J3_32
J3_34
J3_38
J3_40
J3_42
J3_44
J3_48
J3_50
J3_52
J3_54
J3_58
J3_60

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
port_index="82"
port_index="83"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map

</pin_maps>
</port_map>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="18"
port_index="19"
port_index="20"
port_index="21"
port_index="22"
port_index="23"
port_index="24"
port_index="25"
port_index="26"
port_index="27"
port_index="28"
port_index="29"
port_index="30"
port_index="31"
port_index="32"
port_index="33"
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="asio_tri_i" dir="in" left="151" right="0">
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
port_index="82"
port_index="83"
port_index="84"
port_index="85"
port_index="86"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
</pin_maps>
</port_map>
</port_maps>
</interface>
Index
Name
0 RESET
1 spi_ss_i_0
2 spi_io0_i
3 spi_io1_i
4 spi_io2_i
5 spi_io3_i
6 sys_diff_clkp
7 sys_diff_clkn
8 iic_main0_scl_i
9 iic_main0_sda_i
10 sys_led
11 led2
12 PLL_IN4
13 CLK_EN
14 J1_87
15 J1_91
16 J1_95
17 J1_93
18 J1_99
19 J1_97
20 J1_92
21 J1_85
22 J1_31
23 J1_33
24 J1_35
25 J1_37
26 J1_41
27 J1_43
28 J1_45
29 J1_47
30 J1_49
31 J1_51
32 J1_55
33 J1_57
34 J1_59
35 J1_61
36 J1_65
37 J1_67
38 J1_69
39 J1_71
40 J1_75
41 J1_77
42 J1_81
43 J1_83
44 J1_36
45 J1_38
iostandard
loc
bank
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVDS_25
LVDS_25
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
L23
C23
B24
A25
B22
A22
F22
E23
A20
B21
D26
E26
B20
C26
H21
G21
L22
K21
H23
K22
J21
G24
K26
K25
M26
N26
L25
M25
P26
R26
N24
P24
T25
T24
N22
N21
N23
P23
R16
R17
P21
R21
T17
U17
P16
N17
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
46 J1_40
47 J1_42
48 J1_46
49 J1_48
50 J1_50
51 J1_52
52 J1_56
53 J1_58
54 J1_60
55 J1_62
56 J1_66
57 J1_68
58 J1_70
59 J1_72
60 J1_76
61 J1_78
62 J1_80
63 J1_82
64 J1_86
65 J1_88
66 J1_94
67 J1_96
68 J1_98
69 J1_100
70 J2_41
71 J2_43
72 J2_45
73 J2_47
74 J2_51
75 J2_53
76 J2_55
77 J2_57
78 J2_61
79 J2_63
80 J2_65
81 J2_67
82 J2_71
83 J2_73
84 J2_75
85 J2_77
86 J2_81
87 J2_83
88 J2_85
89 J2_87
90 J2_32
91 J2_34
92 J2_36
93 J2_38
L24
M24
M20
N19
M22
M21
P18
R18
M19
N18
R23
R22
R20
T20
U19
U20
P19
P20
T19
T18
T22
T23
P25
R25
U22
V22
U24
U25
AA23
AB24
V23
V24
W26
W25
W24
W23
AB26
AC26
AD25
AE25
AD26
AE26
AD24
AD23
W20
Y21
W21
V21
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
94 J2_42
95 J2_44
96 J2_46
97 J2_48
98 J2_52
99 J2_54
100 J2_56
101 J2_58
102 J2_62
103 J2_64
104 J2_66
105 J2_68
106 J2_72
107 J2_74
108 J2_76
109 J2_78
110 J2_82
111 J2_84
112 J2_86
113 J2_88
114 J2_92
115 J2_94
116 J2_96
117 J2_98
118 J2_100
119 J2_89
120 J2_11
121 J2_13
122 J2_15
123 J2_17
124 J2_21
125 J2_23
126 J2_25
127 J2_27
128 J2_29
129 J2_31
130 J2_33
131 J2_35
132 J2_37
133 J2_14
134 J2_16
135 J2_22
136 J2_24
137 J2_26
138 J2_28
139 J3_37
140 J3_39
141 J3_41
U26
V26
Y23
AA24
AC23
AC24
Y22
AA22
Y26
Y25
AA25
AB25
AB22
AC22
AB21
AC21
AE23
AF23
AF24
AF25
AD21
AE21
AE22
AF22
Y20
U21
G16
H16
J18
J19
G17
F18
F17
E17
J20
L20
L19
L18
M17
C17
C18
E18
D18
H17
H18
A14
B14
A15
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B12
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B16
B16
B16
142 J3_43
143 J3_57
144 J3_59
145 J3_38
146 J3_40
147 J3_42
148 J3_44
149 J3_48
150 J3_50
151 J3_52
152 J3_54
153 J3_58
154 J3_60
155 J3_47
156 J3_49
157 J3_51
158 J3_53
159 REV2_ID
160 EN_MGT
161 PG_MGT_1V
162 PG_MGT_1V2
163 XIO
164 PLL_SCL
165 PLL_SDA
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
B15
E10
D10
G11
F10
E11
D11
E12
E13
D13
D14
C12
C11
G22
F23
A23
A24
C21
H22
K23
G25
H26
A20
B21
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
PINAPI include
87
91
95
93
99
97
92
85
31
33
35
37
41
43
45
47
49
51
55
57
59
61
65
67
69
71
75
77
81
83
36
38
0 #define
1 #define
2 #define
3 #define
4 #define
5 #define
6 #define
7 #define
8 #define
9 #define
{1,31,10},
{1,33,11},
{1,35,12},
{1,37,13},
{1,41,14},
{1,43,15},
{1,45,16},
{1,47,17},
{1,49,18},
{1,51,19},
{1,55,20},
{1,57,21},
{1,59,22},
{1,61,23},
{1,65,24},
{1,67,25},
{1,69,26},
{1,71,27},
{1,75,28},
{1,77,29},
{1,81,30},
{1,83,31},
{1,36,32},
{1,38,33},
10 #define
11 #define
12 #define
13 #define
14 #define
15 #define
16 #define
17 #define
18 #define
19 #define
20 #define
21 #define
22 #define
23 #define
24 #define
25 #define
26 #define
27 #define
28 #define
29 #define
30 #define
31 #define
32 #define
33 #define
PIN_sys_led 0
PIN_led2 1
PIN_PLL_IN4 2
PIN_CLK_EN 3
PIN_J1_87 4
PIN_J1_91 5
PIN_J1_95 6
PIN_J1_93 7
PIN_J1_99 8
PIN_J1_97 9
PIN_J1_31
PIN_J1_33
PIN_J1_35
PIN_J1_37
PIN_J1_41
PIN_J1_43
PIN_J1_45
PIN_J1_47
PIN_J1_49
PIN_J1_51
PIN_J1_55
PIN_J1_57
PIN_J1_59
PIN_J1_61
PIN_J1_65
PIN_J1_67
PIN_J1_69
PIN_J1_71
PIN_J1_75
PIN_J1_77
PIN_J1_81
PIN_J1_83
PIN_J1_36
PIN_J1_38
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
40
42
46
48
50
52
56
58
60
62
66
68
70
72
76
78
80
82
86
88
94
96
98
100
41
43
45
47
51
53
55
57
61
63
65
67
71
73
75
77
81
83
85
87
32
34
36
38
{1,40,34},
{1,42,35},
{1,46,36},
{1,48,37},
{1,50,38},
{1,52,39},
{1,56,40},
{1,58,41},
{1,60,42},
{1,62,43},
{1,66,44},
{1,68,45},
{1,70,46},
{1,72,47},
{1,76,48},
{1,78,49},
{1,80,50},
{1,82,51},
{1,86,52},
{1,88,53},
{1,94,54},
{1,96,55},
{1,98,56},
{1,100,57},
{2,41,58},
{2,43,59},
{2,45,60},
{2,47,61},
{2,51,62},
{2,53,63},
{2,55,64},
{2,57,65},
{2,61,66},
{2,63,67},
{2,65,68},
{2,67,69},
{2,71,70},
{2,73,71},
{2,75,72},
{2,77,73},
{2,81,74},
{2,83,75},
{2,85,76},
{2,87,77},
{2,32,78},
{2,34,79},
{2,36,80},
{2,38,81},
34 #define
35 #define
36 #define
37 #define
38 #define
39 #define
40 #define
41 #define
42 #define
43 #define
44 #define
45 #define
46 #define
47 #define
48 #define
49 #define
50 #define
51 #define
52 #define
53 #define
54 #define
55 #define
56 #define
57 #define
58 #define
59 #define
60 #define
61 #define
62 #define
63 #define
64 #define
65 #define
66 #define
67 #define
68 #define
69 #define
70 #define
71 #define
72 #define
73 #define
74 #define
75 #define
76 #define
77 #define
78 #define
79 #define
80 #define
81 #define
PIN_J1_40 34
PIN_J1_42 35
PIN_J1_46 36
PIN_J1_48 37
PIN_J1_50 38
PIN_J1_52 39
PIN_J1_56 40
PIN_J1_58 41
PIN_J1_60 42
PIN_J1_62 43
PIN_J1_66 44
PIN_J1_68 45
PIN_J1_70 46
PIN_J1_72 47
PIN_J1_76 48
PIN_J1_78 49
PIN_J1_80 50
PIN_J1_82 51
PIN_J1_86 52
PIN_J1_88 53
PIN_J1_94 54
PIN_J1_96 55
PIN_J1_98 56
PIN_J1_100 57
PIN_J2_41 58
PIN_J2_43 59
PIN_J2_45 60
PIN_J2_47 61
PIN_J2_51 62
PIN_J2_53 63
PIN_J2_55 64
PIN_J2_57 65
PIN_J2_61 66
PIN_J2_63 67
PIN_J2_65 68
PIN_J2_67 69
PIN_J2_71 70
PIN_J2_73 71
PIN_J2_75 72
PIN_J2_77 73
PIN_J2_81 74
PIN_J2_83 75
PIN_J2_85 76
PIN_J2_87 77
PIN_J2_32 78
PIN_J2_34 79
PIN_J2_36 80
PIN_J2_38 81
42
44
46
48
52
54
56
58
62
64
66
68
72
74
76
78
82
84
86
88
92
94
96
98
100
89
11
13
15
17
21
23
25
27
29
31
33
35
37
14
16
22
24
26
28
37
39
41
{2,42,82},
{2,44,83},
{2,46,84},
{2,48,85},
{2,52,86},
{2,54,87},
{2,56,88},
{2,58,89},
{2,62,90},
{2,64,91},
{2,66,92},
{2,68,93},
{2,72,94},
{2,74,95},
{2,76,96},
{2,78,97},
{2,82,98},
{2,84,99},
{2,86,100},
{2,88,101},
{2,92,102},
{2,94,103},
{2,96,104},
{2,98,105},
{2,100,106},
{2,89,107},
{2,11,108},
{2,13,109},
{2,15,110},
{2,17,111},
{2,21,112},
{2,23,113},
{2,25,114},
{2,27,115},
{2,29,116},
{2,31,117},
{2,33,118},
{2,35,119},
{2,37,120},
{2,14,121},
{2,16,122},
{2,22,123},
{2,24,124},
{2,26,125},
{2,28,126},
{3,37,127},
{3,39,128},
{3,41,129},
82 #define
83 #define
84 #define
85 #define
86 #define
87 #define
88 #define
89 #define
90 #define
91 #define
92 #define
93 #define
94 #define
95 #define
96 #define
97 #define
98 #define
99 #define
100 #define
101 #define
102 #define
103 #define
104 #define
105 #define
106 #define
107 #define
108 #define
109 #define
110 #define
111 #define
112 #define
113 #define
114 #define
115 #define
116 #define
117 #define
118 #define
119 #define
120 #define
121 #define
122 #define
123 #define
124 #define
125 #define
126 #define
127 #define
128 #define
129 #define
PIN_J2_42 82
PIN_J2_44 83
PIN_J2_46 84
PIN_J2_48 85
PIN_J2_52 86
PIN_J2_54 87
PIN_J2_56 88
PIN_J2_58 89
PIN_J2_62 90
PIN_J2_64 91
PIN_J2_66 92
PIN_J2_68 93
PIN_J2_72 94
PIN_J2_74 95
PIN_J2_76 96
PIN_J2_78 97
PIN_J2_82 98
PIN_J2_84 99
PIN_J2_86 100
PIN_J2_88 101
PIN_J2_92 102
PIN_J2_94 103
PIN_J2_96 104
PIN_J2_98 105
PIN_J2_100 106
PIN_J2_89 107
PIN_J2_11 108
PIN_J2_13 109
PIN_J2_15 110
PIN_J2_17 111
PIN_J2_21 112
PIN_J2_23 113
PIN_J2_25 114
PIN_J2_27 115
PIN_J2_29 116
PIN_J2_31 117
PIN_J2_33 118
PIN_J2_35 119
PIN_J2_37 120
PIN_J2_14 121
PIN_J2_16 122
PIN_J2_22 123
PIN_J2_24 124
PIN_J2_26 125
PIN_J2_28 126
PIN_J3_37 127
PIN_J3_39 128
PIN_J3_41 129
43
57
59
38
40
42
44
48
50
52
54
58
60
47
49
51
53
{3,43,130},
{3,57,131},
{3,59,132},
{3,38,133},
{3,40,134},
{3,42,135},
{3,44,136},
{3,48,137},
{3,50,138},
{3,52,139},
{3,54,140},
{3,58,141},
{3,60,142},
{3,47,143},
{3,49,144},
{3,51,145},
{3,53,146},
130 #define
131 #define
132 #define
133 #define
134 #define
135 #define
136 #define
137 #define
138 #define
139 #define
140 #define
141 #define
142 #define
143 #define
144 #define
145 #define
146 #define
147 #define
148 #define
149 #define
150 #define
151 #define
152 #define
153 #define
PIN_J3_43 130
PIN_J3_57 131
PIN_J3_59 132
PIN_J3_38 133
PIN_J3_40 134
PIN_J3_42 135
PIN_J3_44 136
PIN_J3_48 137
PIN_J3_50 138
PIN_J3_52 139
PIN_J3_54 140
PIN_J3_58 141
PIN_J3_60 142
PIN_J3_47 143
PIN_J3_49 144
PIN_J3_51 145
PIN_J3_53 146
PIN_REV2_ID 147
PIN_EN_MGT 148
PIN_PG_MGT_1V 149
PIN_PG_MGT_1V2 150
PIN_XIO 151
PIN_PLL_SCL 152
PIN_PLL_SDA 153
XDC
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
L23 [get_ports RESET]

C23 [get_ports spi_ss_i_0]
B24 [get_ports spi_io0_i]
A25 [get_ports spi_io1_i]
F22 [get_ports sys_diff_clkp]
E23 [get_ports sys_diff_clkn]
A20 [get_ports iic_main0_scl_i]
B21 [get_ports iic_main0_sda_i]
D26 [get_ports sys_led]
E26 [get_ports led2]
B20 [get_ports PLL_IN4]
C26 [get_ports CLK_EN]
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

AC26 [get_ports J2_73]
AD25 [get_ports J2_75]
AE25 [get_ports J2_77]
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

AF23 [get_ports J2_84]
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

C21 [get_ports REV2_ID]
H22 [get_ports EN_MGT]
K23 [get_ports PG_MGT_1V]
G25 [get_ports PG_MGT_1V2]
H26 [get_ports XIO]
A20 [get_ports PLL_SCL]
B21 [get_ports PLL_SDA]
part0_pins.xml
<?xml version="1.0" encoding="UTF-8" standalone="no"?><part_info part_name="xc7k160tfbg6
<pin index="0" name="RESET" iostandard="LVCMOS33" loc="L23"/>
<pin index="1" name="spi_ss_i_0" iostandard="LVCMOS33" loc="C23"/>
<pin index="2" name="spi_io0_i" iostandard="LVCMOS33" loc="B24"/>
<pin index="3" name="spi_io1_i" iostandard="LVCMOS33" loc="A25"/>
<pin index="6" name="sys_diff_clkp" iostandard="LVDS_25" loc="F22"/>
<pin index="7" name="sys_diff_clkn" iostandard="LVDS_25" loc="E23"/>
<pin index="8" name="iic_main0_scl_i" iostandard="LVCMOS33" loc="A20"/>
<pin index="9" name="iic_main0_sda_i" iostandard="LVCMOS33" loc="B21"/>
<pin index="10" name="sys_led" iostandard="LVCMOS33" loc="D26"/>
<pin index="11" name="led2" iostandard="LVCMOS33" loc="E26"/>
<pin index="12" name="PLL_IN4" iostandard="LVCMOS33" loc="B20"/>
<pin index="13" name="CLK_EN" iostandard="LVCMOS33" loc="C26"/>
<pin index="17" name="J1_93" iostandard="LVCMOS33" loc="K21"/>
<pin index="20" name="J1_92" iostandard="LVCMOS33" loc="J21"/>
<pin index="22" name="J1_31" loc="K26"/>
<pin index="24" name="J1_35" loc="M26"/>
<pin index="25" name="J1_37" loc="N26"/>
<pin index="26" name="J1_41" loc="L25"/>
<pin index="28" name="J1_45" loc="P26"/>
<pin index="29" name="J1_47" loc="R26"/>
<pin index="32" name="J1_55" loc="T25"/>
<pin index="43" name="J1_83" loc="U17"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="46"
index="47"
index="48"
index="49"
index="50"
index="51"
index="52"
index="53"
index="54"
index="55"
index="56"
index="57"
index="58"
index="59"
index="60"
index="61"
index="62"
index="63"
index="64"
index="65"
index="66"
index="67"
index="68"
index="69"
index="70"
index="71"
index="72"
index="73"
index="74"
index="75"
index="76"
index="77"
index="78"
index="79"
index="80"
index="81"
index="82"
index="83"
index="84"
index="85"
index="86"
index="87"
index="88"
index="89"
index="90"
index="91"
index="92"
index="93"
name="J1_40" loc="L24"/>
name="J1_42" loc="M24"/>
name="J1_46" loc="M20"/>
name="J1_48" loc="N19"/>
name="J1_50" loc="M22"/>
name="J1_52" loc="M21"/>
name="J1_56" loc="P18"/>
name="J1_58" loc="R18"/>
name="J1_60" loc="M19"/>
name="J1_62" loc="N18"/>
name="J1_66" loc="R23"/>
name="J1_68" loc="R22"/>
name="J1_70" loc="R20"/>
name="J1_72" loc="T20"/>
name="J1_76" loc="U19"/>
name="J1_78" loc="U20"/>
name="J1_80" loc="P19"/>
name="J1_82" loc="P20"/>
name="J1_86" loc="T19"/>
name="J1_88" loc="T18"/>
name="J1_94" loc="T22"/>
name="J1_96" loc="T23"/>
name="J1_98" loc="P25"/>
name="J1_100" loc="R25"/>
name="J2_41" loc="U22"/>
name="J2_43" loc="V22"/>
name="J2_45" loc="U24"/>
name="J2_47" loc="U25"/>
name="J2_55" loc="V23"/>
name="J2_57" loc="V24"/>
name="J2_61" loc="W26"/>
name="J2_63" loc="W25"/>
name="J2_65" loc="W24"/>
name="J2_67" loc="W23"/>
name="J2_73" loc="AC26"/>
name="J2_75" loc="AD25"/>
name="J2_77" loc="AE25"/>
name="J2_83" loc="AE26"/>
name="J2_32" loc="W20"/>
name="J2_34" loc="Y21"/>
name="J2_36" loc="W21"/>
name="J2_38" loc="V21"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin

index="95" name="J2_44" loc="V26"/>
index="96" name="J2_46" loc="Y23"/>
index="97" name="J2_48" loc="AA24"/>
index="98" name="J2_52" loc="AC23"/>
index="100" name="J2_56" loc="Y22"/>
index="102" name="J2_62" loc="Y26"/>
index="103" name="J2_64" loc="Y25"/>
index="105" name="J2_68" loc="AB25"/>
index="110" name="J2_82" loc="AE23"/>
index="111" name="J2_84" loc="AF23"/>
index="114" name="J2_92" loc="AD21"/>
index="118" name="J2_100" loc="Y20"/>
index="119" name="J2_89" loc="U21"/>
index="120" name="J2_11" loc="G16"/>
index="121" name="J2_13" loc="H16"/>
index="122" name="J2_15" loc="J18"/>
index="123" name="J2_17" loc="J19"/>
index="124" name="J2_21" loc="G17"/>
index="125" name="J2_23" loc="F18"/>
index="126" name="J2_25" loc="F17"/>
index="127" name="J2_27" loc="E17"/>
index="128" name="J2_29" loc="J20"/>
index="129" name="J2_31" loc="L20"/>
index="130" name="J2_33" loc="L19"/>
index="131" name="J2_35" loc="L18"/>
index="132" name="J2_37" loc="M17"/>
index="133" name="J2_14" loc="C17"/>
index="134" name="J2_16" loc="C18"/>
index="135" name="J2_22" loc="E18"/>
index="136" name="J2_24" loc="D18"/>
index="137" name="J2_26" loc="H17"/>
index="138" name="J2_28" loc="H18"/>
index="139" name="J3_37" loc="A14"/>
index="140" name="J3_39" loc="B14"/>
index="141" name="J3_41" loc="A15"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="142"
index="143"
index="144"
index="145"
index="146"
index="147"
index="148"
index="149"
index="150"
index="151"
index="152"
index="153"
index="154"
index="155"
index="156"
index="157"
index="158"
index="159"
index="160"
index="161"
index="162"
index="163"
index="164"
index="165"
name="J3_43" loc="B15"/>
name="J3_57" loc="E10"/>
name="J3_59" loc="D10"/>
name="J3_38" loc="G11"/>
name="J3_40" loc="F10"/>
name="J3_42" loc="E11"/>
name="J3_44" loc="D11"/>
name="J3_48" loc="E12"/>
name="J3_50" loc="E13"/>
name="J3_52" loc="D13"/>
name="J3_54" loc="D14"/>
name="J3_58" loc="C12"/>
name="J3_60" loc="C11"/>
name="REV2_ID" iostandard="LVCMOS33" loc="C21"/>
name="EN_MGT" iostandard="LVCMOS33" loc="H22"/>
name="PG_MGT_1V" iostandard="LVCMOS33" loc="K23"/>
name="PG_MGT_1V2" iostandard="LVCMOS33" loc="G25"/>
name="XIO" iostandard="LVCMOS33" loc="H26"/>
name="PLL_SCL" iostandard="LVCMOS33" loc="A20"/>
name="PLL_SDA" iostandard="LVCMOS33" loc="B21"/>
name/first
width
reset
0
10
11
10
10
11
11
20
21
mgt1_diff_clock
12
13
14
21
14
19
22
22
43
21
spi_flash
sys_diff_clock
leds
sys_led
led2
iic_main0
uart0
p0
p0_6bits
p1a
p1b
44
26
69
25
70
20
89
19
90
30
119
29
120
19
138
18
139
16
154
15
155
158
p2a
p2b
p2c
p3a
p3b
<connections>
<connection_map name="part0_reset_1" c1_st_index="0" c1_end_index="0" c2_st_index="0"
</connection>

<connection_map name="part0_spi_flash_1" c1_st_index="1" c1_end_index="5" c2_st_index=
</connection>
<connection name="part0_sys_diff_clock" component1="part0" component2="sys_diff_clock">

<connection_map name="part0_sys_diff_clock_1" c1_st_index="6" c1_end_index="7" c2_st_ind
</connection>

<connection_map name="part0_leds_1" c1_st_index="10" c1_end_index="11" c2_st_index="0
</connection>
<connection name="part0_sys_led" component1="part0" component2="sys_led">

<connection_map name="part0_sys_led_1" c1_st_index="10" c1_end_index="10" c2_st_index=
</connection>
<connection name="part0_led2" component1="part0" component2="led2">

<connection_map name="part0_led2_1" c1_st_index="11" c1_end_index="11" c2_st_index="0
</connection>
<connection name="part0_iic_main0" component1="part0" component2="iic_main0">

<connection_map name="part0_iic_main0_1" c1_st_index="8" c1_end_index="9" c2_st_index=
</connection>

<connection_map name="part0_uart0_1" c1_st_index="20" c1_end_index="21" c2_st_index="
</connection>
<connection name="part0_mgt1_diff_clock" component1="part0" component2="mgt1_diff_cloc

<connection_map name="part0_mgt1_diff_clock_1" c1_st_index="12" c1_end_index="13" c2_s
</connection>
<connection_map name="part0_p0_1" c1_st_index="14" c1_end_index="21" c2_st_index="0"
</connection>

<connection_map name="part0_p0_6bits_1" c1_st_index="14" c1_end_index="19" c2_st_index
</connection>

</connection>

<connection_map name="part0_p1b_1" c1_st_index="44" c1_end_index="69" c2_st_index="0
</connection>

</connection>

<connection_map name="part0_p2b_1" c1_st_index="90" c1_end_index="119" c2_st_index="
</connection>

<connection_map name="part0_p2c_1" c1_st_index="120" c1_end_index="138" c2_st_index=
</connection>

<connection_map name="part0_p3a_1" c1_st_index="139" c1_end_index="154" c2_st_index=
</connection>

<connection_map name="part0_p3b_1" c1_st_index="155" c1_end_index="158" c2_st_index=
</connection>

<connection_map name="part0_asio_1" c1_st_index="10" c1_end_index="19" c2_st_index="0
<connection_map name="part0_asio_2" c1_st_index="22" c1_end_index="163" c2_st_index="
</connection>
p0
0
1
2
3
4
5
6
7
8
J1_87
J1_91
J1_95
J1_93
J1_99
J1_97
J1_92
J1_85
p0_6bits
0
1
2
3
4
5
6
J1_87
J1_91
J1_95
J1_93
J1_99
J1_97
p1a
0
1
2
3
4
5
6
22
J1_31
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
21
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
J1_47
J1_49
J1_51
J1_55
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
J1_83
p1b
0
1
2
3
4
5
6
7
8
9
10
11
12
26
J1_36
J1_38
J1_40
J1_42
J1_46
J1_48
J1_50
J1_52
J1_56
J1_58
J1_60
J1_62
J1_66
25
13
14
15
16
17
18
19
20
21
22
23
24
25
J1_68
J1_70
J1_72
J1_76
J1_78
J1_80
J1_82
J1_86
J1_88
J1_94
J1_96
J1_98
J1_100
p2a
0
1
2
3
4
5
6
20
J2_41
J2_43
J2_45
J2_47
J2_51
J2_53
J2_55
19
7
8
9
10
11
12
13
14
15
16
17
18
19
J2_57
J2_61
J2_63
J2_65
J2_67
J2_71
J2_73
J2_75
J2_77
J2_81
J2_83
J2_85
J2_87
p2b
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
30
J2_32
J2_34
J2_36
J2_38
J2_42
J2_44
J2_46
J2_48
J2_52
J2_54
J2_56
J2_58
J2_62
J2_64
J2_66
J2_68
J2_72
J2_74
J2_76
29
19
20
21
22
23
24
25
26
27
28
29
J2_78
J2_82
J2_84
J2_86
J2_88
J2_92
J2_94
J2_96
J2_98
J2_100
J2_89
p2c
0
19
J2_11
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
J2_13
J2_15
J2_17
J2_21
J2_23
J2_25
J2_27
J2_29
J2_31
J2_33
J2_35
J2_37
J2_14
J2_16
J2_22
J2_24
J2_26
J2_28
p3a
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J3_37
J3_39
J3_41
J3_43
J3_57
J3_59
J3_38
J3_40
J3_42
J3_44
J3_48
J3_50
J3_52
J3_54
J3_58
J3_60
15
p3b
0
1
2
3
4
J3_47
J3_49
J3_51
J3_53
asio
0
1
2
3
4
152
sys_led
led2
PLL_IN4
CLK_EN
J1_87
151
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
J1_91
J1_95
J1_93
J1_99
J1_97
J1_31
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
J1_47
J1_49
J1_51
J1_55
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
J1_83
J1_36
J1_38
J1_40
J1_42
J1_46
J1_48
J1_50
J1_52
J1_56
J1_58
J1_60
J1_62
J1_66
J1_68
J1_70
J1_72
J1_76
J1_78
J1_80
J1_82
J1_86
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
J1_88
J1_94
J1_96
J1_98
J1_100
J2_41
J2_43
J2_45
J2_47
J2_51
J2_53
J2_55
J2_57
J2_61
J2_63
J2_65
J2_67
J2_71
J2_73
J2_75
J2_77
J2_81
J2_83
J2_85
J2_87
J2_32
J2_34
J2_36
J2_38
J2_42
J2_44
J2_46
J2_48
J2_52
J2_54
J2_56
J2_58
J2_62
J2_64
J2_66
J2_68
J2_72
J2_74
J2_76
J2_78
J2_82
J2_84
J2_86
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
J2_88
J2_92
J2_94
J2_96
J2_98
J2_100
J2_89
J2_11
J2_13
J2_15
J2_17
J2_21
J2_23
J2_25
J2_27
J2_29
J2_31
J2_33
J2_35
J2_37
J2_14
J2_16
J2_22
J2_24
J2_26
J2_28
J3_37
J3_39
J3_41
J3_43
J3_57
J3_59
J3_38
J3_40
J3_42
J3_44
J3_48
J3_50
J3_52
J3_54
J3_58
J3_60
J3_47
J3_49
J3_51
J3_53
REV2_ID
EN_MGT
149
150
151
PG_MGT_1V
PG_MGT_1V2
XIO

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p0_tri_o" dir="out" left="7" right="0"
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="p0_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_co

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p0_6bits_tri_o" dir="out" left="5" righ
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p0_6bits_tri_t" dir="out" left="5" righ
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="p0_6bits_tri_i" dir="in" left="5" right="
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>
<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p2c_tri_t" dir="out" left="18" right="
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>

</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="p3b_tri_o" dir="out" left="3" right="0
<pin_maps>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="p3b_tri_t" dir="out" left="3" right="0
<pin_maps>
</pin_maps>
</port_map>
<pin_maps>
</pin_maps>
</port_map>
</port_maps>
</interface>

<preferred_ips>
</preferred_ips>
<port_maps>

<pin_maps>
<pin_map port_index="2" component_pin="PLL_IN4"/>
<pin_map port_index="3" component_pin="CLK_EN"/>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
port_index="82"
port_index="83"
port_index="84"
port_index="85"
port_index="86"
port_index="87"
port_index="88"
port_index="89"
port_index="90"
port_index="91"
port_index="92"
port_index="93"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map

<pin_map port_index="147" component_pin="REV2_ID"/>
<pin_map port_index="148" component_pin="EN_MGT"/>
<pin_map port_index="149" component_pin="PG_MGT_1V"/>
<pin_map port_index="150" component_pin="PG_MGT_1V2"/>
<pin_map port_index="151" component_pin="XIO"/>
</pin_maps>
</port_map>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"
port_index="78"
port_index="79"
port_index="80"
port_index="81"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map

</pin_maps>
</port_map>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="22"
port_index="23"
port_index="24"
port_index="25"
port_index="26"
port_index="27"
port_index="28"
port_index="29"
port_index="30"
port_index="31"
port_index="32"
port_index="33"
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
</pin_maps>
</port_map>
</port_maps>
</interface>
component_pin="REV2_ID"/>
component_pin="EN_MGT"/>
component_pin="PG_MGT_1V"/>
component_pin="PG_MGT_1V2"/>
component_pin="XIO"/>
Index
Name
0 RESET
1 spi_ss_i_0
2 spi_io0_i
3 spi_io1_i
4 spi_io2_i
5 spi_io3_i
6 sys_diff_clkp
7 sys_diff_clkn
8 iic_main0_scl_i
9 iic_main0_sda_i
10 sys_led
11 led2
12 PLL_IN4
13 CLK_EN
14 J1_87
15 J1_91
16 J1_95
17 J1_93
18 J1_99
19 J1_97
20 J1_92
21 J1_85
22 J1_31
23 J1_33
24 J1_35
25 J1_37
26 J1_41
27 J1_43
28 J1_45
29 J1_47
30 J1_49
31 J1_51
32 J1_55
33 J1_57
34 J1_59
35 J1_61
36 J1_65
37 J1_67
38 J1_69
39 J1_71
40 J1_75
41 J1_77
42 J1_81
43 J1_83
44 J1_36
45 J1_38
iostandard
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVDS_25
LVDS_25
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
46 J1_40
47 J1_42
48 J1_46
49 J1_48
50 J1_50
51 J1_52
52 J1_56
53 J1_58
54 J1_60
55 J1_62
56 J1_66
57 J1_68
58 J1_70
59 J1_72
60 J1_76
61 J1_78
62 J1_80
63 J1_82
64 J1_86
65 J1_88
66 J1_94
67 J1_96
68 J1_98
69 J1_100
70 J2_11
71 J2_13
72 J2_15
73 J2_17
74 J2_21
75 J2_23
76 J2_25
77 J2_27
78 J2_29
79 J2_31
80 J2_33
81 J2_35
82 J2_37
83 J2_14
84 J2_16
85 J2_22
86 J2_24
87 J2_26
88 J2_28
89 J3_37
90 J3_39
91 J3_41
92 J3_43
93 J3_57
94 J3_59
95 J3_38
96 J3_40
97 J3_42
98 J3_44
99 J3_48
100 J3_50
101 J3_52
102 J3_54
103 J3_58
104 J3_60
105 J3_47
106 J3_49
107 J3_51
108 J3_53
109 REV2_ID
110 EN_MGT
111 PG_MGT_1V
112 PG_MGT_1V2
113 XIO
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
loc
bank
L23
C23
B24
A25
B22
A22
F22
E23
A20
B21
D26
E26
B20
C26
H21
G21
L22
K21
H23
K22
J21
G24
K26
K25
M26
N26
L25
M25
P26
R26
N24
P24
T25
T24
N22
N21
N23
P23
R16
R17
P21
R21
T17
U17
P16
N17
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B14
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
L24
M24
M20
N19
M22
M21
P18
R18
M19
N18
R23
R22
R20
T20
U19
U20
P19
P20
T19
T18
T22
T23
P25
R25
G16
H16
J18
J19
G17
F18
F17
E17
J20
L20
L19
L18
M17
C17
C18
E18
D18
H17
H18
A14
B14
A15
B15
E10
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B13
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B15
B16
B16
B16
B16
B16
D10
G11
F10
E11
D11
E12
E13
D13
D14
C12
C11
G22
F23
A23
A24
C21
H22
K23
G25
H26
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B16
B14
B14
B14
B14
B14
B14
B14
B14
B14
XDC
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
L23 [get_ports RESET]

C23 [get_ports spi_ss_i_0]
F22 [get_ports sys_diff_clkp]
E23 [get_ports sys_diff_clkn]
A20 [get_ports iic_main0_scl_i]
B21 [get_ports iic_main0_sda_i]
D26 [get_ports sys_led]
E26 [get_ports led2]
B20 [get_ports PLL_IN4]
C26 [get_ports CLK_EN]
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN
PACKAGE_PIN

C21 [get_ports REV2_ID]
H22 [get_ports EN_MGT]
K23 [get_ports PG_MGT_1V]
G25 [get_ports PG_MGT_1V2]
H26 [get_ports XIO]
part0_pins.xml
<?xml version="1.0" encoding="UTF-8" standalone="no"?><part_info part_name="xc7k160tfbg6
<pin index="0" name="RESET" iostandard="LVCMOS33" loc="L23"/>
<pin index="1" name="spi_ss_i_0" iostandard="LVCMOS33" loc="C23"/>
<pin index="6" name="sys_diff_clkp" iostandard="LVDS_25" loc="F22"/>
<pin index="7" name="sys_diff_clkn" iostandard="LVDS_25" loc="E23"/>
<pin index="8" name="iic_main0_scl_i" iostandard="LVCMOS33" loc="A20"/>
<pin index="9" name="iic_main0_sda_i" iostandard="LVCMOS33" loc="B21"/>
<pin index="10" name="sys_led" iostandard="LVCMOS33" loc="D26"/>
<pin index="11" name="led2" iostandard="LVCMOS33" loc="E26"/>
<pin index="12" name="PLL_IN4" iostandard="LVCMOS33" loc="B20"/>
<pin index="13" name="CLK_EN" iostandard="LVCMOS33" loc="C26"/>
<pin index="20" name="J1_92" iostandard="LVCMOS33" loc="J21"/>
<pin index="26" name="J1_41" loc="L25"/>
<pin index="43" name="J1_83" loc="U17"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="46"
index="47"
index="48"
index="49"
index="50"
index="51"
index="52"
index="53"
index="54"
index="55"
index="56"
index="57"
index="58"
index="59"
index="60"
index="61"
index="62"
index="63"
index="64"
index="65"
index="66"
index="67"
index="68"
index="69"
index="70"
index="71"
index="72"
index="73"
index="74"
index="75"
index="76"
index="77"
index="78"
index="79"
index="80"
index="81"
index="82"
index="83"
index="84"
index="85"
index="86"
index="87"
index="88"
index="89"
index="90"
index="91"
index="92"
index="93"
name="J1_40" loc="L24"/>
name="J1_42" loc="M24"/>
name="J1_46" loc="M20"/>
name="J1_48" loc="N19"/>
name="J1_50" loc="M22"/>
name="J1_52" loc="M21"/>
name="J1_56" loc="P18"/>
name="J1_58" loc="R18"/>
name="J1_60" loc="M19"/>
name="J1_62" loc="N18"/>
name="J1_66" loc="R23"/>
name="J1_68" loc="R22"/>
name="J1_70" loc="R20"/>
name="J1_72" loc="T20"/>
name="J1_76" loc="U19"/>
name="J1_78" loc="U20"/>
name="J1_80" loc="P19"/>
name="J1_82" loc="P20"/>
name="J1_86" loc="T19"/>
name="J1_88" loc="T18"/>
name="J1_94" loc="T22"/>
name="J1_96" loc="T23"/>
name="J1_98" loc="P25"/>
name="J1_100" loc="R25"/>
name="J2_11" loc="G16"/>
name="J2_13" loc="H16"/>
name="J2_15" loc="J18"/>
name="J2_17" loc="J19"/>
name="J2_21" loc="G17"/>
name="J2_23" loc="F18"/>
name="J2_25" loc="F17"/>
name="J2_27" loc="E17"/>
name="J2_29" loc="J20"/>
name="J2_31" loc="L20"/>
name="J2_33" loc="L19"/>
name="J2_35" loc="L18"/>
name="J2_37" loc="M17"/>
name="J2_14" loc="C17"/>
name="J2_16" loc="C18"/>
name="J2_22" loc="E18"/>
name="J2_24" loc="D18"/>
name="J2_26" loc="H17"/>
name="J2_28" loc="H18"/>
name="J3_37" loc="A14"/>
name="J3_39" loc="B14"/>
name="J3_41" loc="A15"/>
name="J3_43" loc="B15"/>
name="J3_57" loc="E10"/>
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
<pin
index="94" name="J3_59" loc="D10"/>

index="96" name="J3_40" loc="F10"/>
index="98" name="J3_44" loc="D11"/>
index="100" name="J3_50" loc="E13"/>
index="101" name="J3_52" loc="D13"/>
index="102" name="J3_54" loc="D14"/>
index="103" name="J3_58" loc="C12"/>
index="104" name="J3_60" loc="C11"/>
index="109" name="REV2_ID" iostandard="LVCMOS33" loc="C21"/>
index="110" name="EN_MGT" iostandard="LVCMOS33" loc="H22"/>
index="111" name="PG_MGT_1V" iostandard="LVCMOS33" loc="K23"/>
index="112" name="PG_MGT_1V2" iostandard="LVCMOS33" loc="G25"/>
index="113" name="XIO" iostandard="LVCMOS33" loc="H26"/>
asio
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
102
sys_led
led2
PLL_IN4
CLK_EN
J1_87
J1_91
J1_95
J1_93
J1_99
J1_97
J1_31
J1_33
J1_35
J1_37
J1_41
J1_43
J1_45
J1_47
J1_49
J1_51
J1_55
J1_57
J1_59
J1_61
J1_65
J1_67
J1_69
J1_71
J1_75
J1_77
J1_81
J1_83
J1_36
J1_38
J1_40
J1_42
J1_46
101
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
J1_48
J1_50
J1_52
J1_56
J1_58
J1_60
J1_62
J1_66
J1_68
J1_70
J1_72
J1_76
J1_78
J1_80
J1_82
J1_86
J1_88
J1_94
J1_96
J1_98
J1_100
J2_11
J2_13
J2_15
J2_17
J2_21
J2_23
J2_25
J2_27
J2_29
J2_31
J2_33
J2_35
J2_37
J2_14
J2_16
J2_22
J2_24
J2_26
J2_28
J3_37
J3_39
J3_41
J3_43
J3_57
J3_59
J3_38
J3_40
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
J3_42
J3_44
J3_48
J3_50
J3_52
J3_54
J3_58
J3_60
J3_47
J3_49
J3_51
J3_53
REV2_ID
EN_MGT
PG_MGT_1V
PG_MGT_1V2
XIO
TE0741-70-2CF
xc7k70tfbg676-2

<preferred_ips>
</preferred_ips>
<port_maps>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="30"
port_index="31"
port_index="32"
port_index="33"
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"
port_index="68"
port_index="69"
port_index="70"
port_index="71"
port_index="72"
port_index="73"
port_index="74"
port_index="75"
port_index="76"
port_index="77"

</pin_maps>
</port_map>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="20"
port_index="21"
port_index="22"
port_index="23"
port_index="24"
port_index="25"
port_index="26"
port_index="27"
port_index="28"
port_index="29"
port_index="30"
port_index="31"
port_index="32"
port_index="33"
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"
port_index="58"
port_index="59"
port_index="60"
port_index="61"
port_index="62"
port_index="63"
port_index="64"
port_index="65"
port_index="66"
port_index="67"

</pin_maps>
</port_map>
<pin_maps>
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
<pin_map
port_index="10"
port_index="11"
port_index="12"
port_index="13"
port_index="14"
port_index="15"
port_index="16"
port_index="17"
port_index="18"
port_index="19"
port_index="20"
port_index="21"
port_index="22"
port_index="23"
port_index="24"
port_index="25"
port_index="26"
port_index="27"
port_index="28"
port_index="29"
port_index="30"
port_index="31"
port_index="32"
port_index="33"
port_index="34"
port_index="35"
port_index="36"
port_index="37"
port_index="38"
port_index="39"
port_index="40"
port_index="41"
port_index="42"
port_index="43"
port_index="44"
port_index="45"
port_index="46"
port_index="47"
port_index="48"
port_index="49"
port_index="50"
port_index="51"
port_index="52"
port_index="53"
port_index="54"
port_index="55"
port_index="56"
port_index="57"

</pin_maps>
</port_map>
</port_maps>
</interface>

MasterPinout 4x5

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MasterPinout 4x5

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TE0710

Jxx JBx TE0701-0x

J17 VCC SELECT

PLEASE READ The Usage note for

G18 [get_ports J1_46]

name="sys_gpio1" iostandard="LVCMOS33" loc="D9"/>

index="88" name="J1_46" loc="G18"/>

<connection name="part0_reset" component1="part0" component2="reset">

<connection name="part0_spi_flash" component1="part0" component2="spi_flash">

<connection name="part0_sys_clock" component1="part0" component2="sys_clock">

<connection name="part0_mii0" component1="part0" component2="mii0">

<connection name="part0_mdio_io0" component1="part0" component2="mdio_io0">

<connection name="part0_mii1" component1="part0" component2="mii1">

<connection name="part0_mdio_io1" component1="part0" component2="mdio_io1">

<connection name="part0_sys_gpio" component1="part0" component2="sys_gpio">

<connection name="part0_p0" component1="part0" component2="p0">

<connection name="part0_p0_6bits" component1="part0" component2="p0_6bits">

<connection name="part0_p1a" component1="part0" component2="p1a">

<connection name="part0_p1b" component1="part0" component2="p1b">

<connection name="part0_p2a" component1="part0" component2="p2a">

<connection name="part0_p2b" component1="part0" component2="p2b">

<connection name="part0_asio" component1="part0" component2="asio">

<interface mode="master" name="sys_gpio" type="xilinx.com:interface:gpio_rtl:1.0" of_comp

<interface mode="master" name="p0" type="xilinx.com:interface:gpio_rtl:1.0" of_component

<interface mode="master" name="p0_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_comp

<interface mode="master" name="p1a" type="xilinx.com:interface:gpio_rtl:1.0" of_componen

<port_map logical_port="TRI_O" physical_port="p1a_tri_o" dir="out" left="27" right="0">

<pin_map port_index="11" component_pin="J1_43"/>

<interface mode="master" name="p1b" type="xilinx.com:interface:gpio_rtl:1.0" of_componen

<interface mode="master" name="p2a" type="xilinx.com:interface:gpio_rtl:1.0" of_componen

<pin_map port_index="15" component_pin="J2_77"/>

<interface mode="master" name="p2b" type="xilinx.com:interface:gpio_rtl:1.0" of_componen

<pin_map port_index="21" component_pin="J2_84"/>

<port_map logical_port="TRI_I" physical_port="p2b_tri_i" dir="in" left="29" right="0">

<interface mode="master" name="asio" type="xilinx.com:interface:gpio_rtl:1.0" of_componen

<pin_map port_index="86" component_pin="J2_46"/>

<pin_map port_index="107" component_pin="J2_98"/>

<pin_map port_index="83" component_pin="J2_38"/>

L13 [get_ports spi_ss]

B17 [get_ports J1_45]

T14 [get_ports J2_21]

name="J1_45" iostandard="LVCMOS33" loc="B17"/>

index="94" name="J2_55" iostandard="LVCMOS33" loc="G4"/>

name="J2_21" iostandard="LVCMOS33" loc="T14"/>

name="J3_57" iostandard="LVCMOS33" loc="M1"/>

<connection name="part0_sys_clk" component1="part0" component2="sys_clk">

<connection name="part0_leds" component1="part0" component2="leds">

<connection name="part0_dummy_rst" component1="part0" component2="dummy_rst">

<connection name="part0_base_uart0" component1="part0" component2="base_uart0">

<connection name="part0_p0" component1="part0" component2="p0">

<connection name="part0_p0_6bit" component1="part0" component2="p0_6bit">

<connection name="part0_p1a" component1="part0" component2="p1a">

<connection name="part0_p1b" component1="part0" component2="p1b">

<connection name="part0_p2a" component1="part0" component2="p2a">

<connection_map name="part0_p2c_1" c1_st_index="138" c1_end_index="155" c2_st_index="0"

<connection name="part0_p1c" component1="part0" component2="p1c">

<connection name="part0_dummy_rst component1="part0" component2="dummy_rst">

<interface mode="master" name="p0" type="xilinx.com:interface:gpio_rtl:1.0" of_compone

<interface mode="master" name="p0_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_co

<interface mode="master" name="p1a" type="xilinx.com:interface:gpio_rtl:1.0" of_compon

<pin_map port_index="4" component_pin="J1_41"/>

<pin_map port_index="16" component_pin="J1_69"/>