1.

ADC and correlations among subprojects

My goal is to design a high speed analog to digital data converter
for signal bandwidth about 10 MHz and resolution about 10 bits.
There are several data converter architectures to meet this
specification. Nevertheless, our lab (SOC LAB) has been working
on sigma-delta converters design for many years. Due to its
oversampling property, it makes analog design easier than that
in Nyquist ADCs. High resolution sigma-delta ADCs for
measurement are very popular among commercial products. With
technology process scaling down, even high speed sigma delta
ADCs can be implemented. Therefore, my goal is to design a high
speed continuous time sigma delta ADCs for signal bandwidth
10MHz and 10 bits resolution.

Fig. 1 ADC and other subprojects

2. System level simulation using MATLAB delta sigma tool

box
It is crucial to verify system level designs before starting to build
a transistor level designs. For such complicated circuit, it may
take many days and hours for transistor level simulation. System
level simulation help engineer to quickly verify if his/her design
meet specifications and to gain an insight how the circuit works
with each other. Delta sigma tool box offers tremendous
functions related to sigma delta ADCs. For example,
synthesizeNTF() gives a noise transfer function which is the most
important thing when one comes into design sigma delta ADCs.
After having noise transfer function, loop filter transfer function is
obtained. Next step is to choose modulator architecture, either
CIFF or CIFB, then realizeNTF_ct() gives coefficients based on
modulator topology.

Choosing order (modulators order)=3, OSR=32 (oversampling

ratio), nlev=2 (number of level in quantizer) and CIFB topology,
simulation result shows that SNR is about 72.3dB when input is
-2dBFS. The result gives a good design margin for targeting
10bits resolution. Signal transfer function(STF) and noise transfer
function(NTF) figure also indicates that the inband noise is
attenuated about 50dB and most of quantization noise is pushed
to outband through the NTF.

Fig. 2-1 STF and NTF of sigma delta modulator

Fig. 2-2 output spectrum and SQNR vs. input amplitude

3. Bandgap reference circuit

As in other analog ICs, the majority of sigma delta
modulators(SDM) generate their internal reference voltages and
bias currents from a DC temperature-independent voltage. This
voltage is generated using the well-known bandgap-reference
generator circuits, often referred to as bandgap circuits.

Fig. 3-1 bandgap reference circuit

The reference voltage Vref required for the modulator operation
can be obtained as a linear function of the bandgap voltage.
Vref = Vr+ Vr- = Vbg where is a proportionality factor. For
instance, if = 4/5, then a reference voltage of Vref = 1 V is
obtained. This can be easily implemented using a fullydifferential amplifier in inverting configuration. This way, by
simply choosing R2 = 4/5 R1, a reference voltage of Vref = 1 V
is obtained. Note that a bufferthat can be implemented by
using a simple (asymmetric) OTA circuitis used for driving the
bandgap voltage Vbg. In addition, a damping network that is
made up of an RC circuit based on MOS capacitors connected in
antiparallel configuration, is used for removing ringing voltages
added to the reference voltages

Fig. 3-2 reference voltage generator

All current sources and sinks required to bias the SDM subcircuits
(opamps, comparators, etc.) need to be generated internally (onchip) from a master bias current by a single circuit, commonly
referred to as master bias current generator. A single master current
is generated from the bandgap voltage and an external (off-chip)
resistor. The generated master bias current is mirrored and properly
scaled to bias all amplifiers (used in integrators), the preamplifying
stages of comparators, as well as other auxiliary (analog) sigma
delta modulator building blocks such as the reference voltage
generator and the common-mode voltage generator

Fig. 3-3 master bias current source

The common-mode voltage VCM is usually defined as a half of the
supply voltage, that is, VCM = (VDD VSS)/2. This operation can be
easily performed by a resistor divider and a buffer. This circuit
implements the required ratio of 1/2 in a simple and robust way
using two identical resistors and a simple OTA configured as a
buffer. Similar to the case of the reference voltage generators, a
large (off-chip) capacitor may be used in combination with an onchip damping network in order to clean the generated voltage and
keep it constant and stable despite the switching-noise
activity propagated across the substrate.

Fig. 3-4 common mode voltage generator

4. Reference
[1] Schreier, Richard, and Gabor C. Temes. Understanding delta-sigma
data converters. Vol. 74. Piscataway, NJ: IEEE press, 2005.
[2] Jos, M., and Roco del Ro. CMOS sigma-delta converters: Practical
design guide. John Wiley & Sons, 2013.
[3] Hong, Kuo-Che, and Herming Chiueh. "A 36-mW 320-MHz CMOS
continuous-time sigma-delta modulator with 10-MHz bandwidth and 12bit resolution."Circuits and Systems (MWSCAS), 2010 53rd IEEE
International Midwest Symposium on. IEEE, 2010.