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Synopsys Documentation
Logic Synthesis 5
FSM and Retiming
FF1
FF3
Input
Logic
Q
FF
Logic
Logic
FF
Q
FF
Logic
g
Clk
Two Clock Periods
This input
changes
once every
2nd cycle
FF4
D
FF5
Q
Large Logic
FF
Q
FF
Multi-Cycle Path
False Paths
You can exclude false paths from an Static Timing Analysis run.
False paths are considered unconstrained.
Top
A
U3
Alpha
U1
Beta
U5
Gamma
False Path
Reset
U4
Alpha
U2
Delta
Clk
REG
Original design
Op1
Op2
Op3
30 ns
Go get better performance
- symbolical!
REG
REG
Op1
Op2
REG
REG
Op3
30 ns
REG
Note:
REG
R EG
REG
Op1
Op2
Op3
10 ns
10 ns
10 ns
This approach will create an overall larger latency due to the extra
registers, but the through-put will increase!
REG
Original design
Op1 - e.g. multiplier
30 ns
REG
HDL:
Add some registers
REG
REG
REG
30 ns
REG
Note:
REG
R EG
REG
Op1.1
Op1.2
Op1.3
10 ns
10 ns
10 ns
This approach will create an overall larger delay due to the extra registers
but the through-put will increase!
Re-timing - Limitations
Only works on mapped/compiled designs
No Set or Reset on the registers allowed
1
Reset
Reset
x(n+1)
REG
Op1
R EG4
O 1
Op1
Registers Added
REG2
REG3
REG4
Op1
Registers Added
REG2
Op1.1
REG3
Op1.2
R EG 4
Op1.3
: IN BIT;
: IN BIT;
: OUT BIT);
Output
Mealy Machine
Output
p
Register
Input
BEGIN
next_state
logic
seq_logic : PROCESS(Clk)
BEGIN
IF (ClkEVENT and Clk = 1) then
current_state <= next_state;
END IF;
END PROCESS;
State
Register
state
Combinatorial logic
Sequential logic
y Machine
Mealy
: IN BIT;
: IN BIT;
: OUT BIT);
Input
next_state
logic
Output
Register
State
Register
state
Order is important!
BEGIN
seq_logic : PROCESS(Clk)
BEGIN
VHDL
Compile
State
T bl
Tables
Gates
Change
StateState
Encodings
FSM compile
Extraction of the state-vector in a design where the state-vector is not the only
sequential elements
dc>
dc>
d
dc>
dc>
dc>
dc>
dc>
Extraction of the state-vector in a design where the state-vector attribute is not set
in the HDL
Existing Registers
U1:FLIP_FLOP p
port map
p (NEXT_STATE[0], CLK, STATE[0]);
U2:FLIP_FLOP port map (NEXT_STATE[1], CLK, STATE[1]);
VHDL
Compile
State
Tables
Gates
Change
StateEncodings
FSM compile
How to set the encoding of the fsm to one-hot and perform an FSM compile
The script was extracted from command-window after graphical interface manipulations :(
dc>
dc>
dc>
dc>
dc>
dc>
dc>
set_fsm_order { S0 S1 S2 S3 }
set_fsm_encoding { }
set_fsm_encoding_style one_hot
set_fsm_order { S0 S1 S2 S3 }
set_fsm_encoding { "S0=2#1000"
"S0=2#1000"S2=2#0100
"S0=2#1000"
"S0=2#1000"}
S0=2#0001 S1=2#0010
S3=2#1000
set_fsm_minimize true
compile -map_effort medium