PRAGATI SACHAN et al.

Volume 3 Issue 4: 2015

Citation: 10.2348/ijset07150914
Impact Factor- 3.25

ISSN (O): 2348-4098

ISSN (P): 2395-4752

VHDLIMPLEMENTATIONOFFLOATINGPOINTMULTIPLIERBASEDONVEDIC
MULTIPLICATIONTECHNIQUE

PRAGATISACHAN
M.Tech(VLSI)Scholar,ElectronicsandcommunicationEngineering,JayotiVidyapeethWomensUniversityJaipur,
Rajasthan,India,sachanpragati.kgi@gmail.com

ABSTRACT
Inthispaper,IEEEfloatingpointformatwasastandardformatusedinallprocessingelementssinceBinaryfloatingpoint
numbersmultiplicationisoneofthebasicfunctionsusedindigitalsignalprocessing(DSP)application.InthatworkVHDL
implementation of Floating Point Multiplier using ancient Vedic mathematics is presented. The idea for designing the
multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhvatriyakbhyam sutra will be used for the
multiplicationofMantissa.Theunderflowandoverflowcaseswillbehandled.Theinputstothemultiplierin32bitformat.
ThemultiplierisdesignedinVHDLorVERILOGandsimulatedusingModelsim.
Keywords:VedicMathematics,Urdhvatriyakbhyamsutra,FloatingPointmultiplier,FPGA.

1.INTRODUCTION
1.1 FLOATING POINT MULTIPLIER FOR IEEE
FORMATE
Multiplication of two nos using Urdhva Tiryakbhyam
sutraisperformedbyverticallyandcrosswise,crosswise
means diagonal multiplication and vertically means
straight above multiplication and taking their sum. The
feature is any multibit multiplication can be reduced
downtosinglebitmultiplicationandadditionusingthis
method. On account of these formulas, the carry
propagationfromLSBtoMSBisreducesduetoonestep
generation of partial product, the efficient use of Vedic
multiplication method in order to multiply two floating
pointnumbers.Thisworkpresentsanimplementationof
a floating point multiplier that supports the IEEE 754
2008binaryinterchangeformat.Basedonthediscussion
made above it is very clear that a multiplier is a very
important element in any processor design and a
processor spends considerable amount of time in
performing multiplication and generally the most area
consuming.Hence,optimizingthespeedandareaofthe
multiplier is a major design issue. An improvement in
multiplication speed by using new techniques can
greatlyimprovesystemperformance.Inthenextstageof
the project the design will be designed using VHDL or
VERILOG and will be simulated using Modelsim
Simulator. The design will be synthesized using Xilinx
ISE 12.1 tool. A test bench will be used to generate the
stimulus and the multiplier operation is to be
verified.The over flow and under flow flags are to
incorporated in the design in order to show the over
flow and under flow cases. The theory states that the
efficient use of Vedic multiplication method in order to
multiplytwofloatingpointnumbers.Thatthehardware
requirement is reduced, thereby reducing the power
consumption. The power consumption upon reducing
affectively may not compromise delay so much.
Multiplicationofthefloatingpointnumbersdescribedin
IEEE754singleprecisionvalid.Floatingpointmultiplier
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is done using VHDL.Implementation in VHDL(VHSIC

Hardware Description Language) is used because it
allow direct implementation on the hardware while in
otherlanguagetheyhavetoconvertthemintoHDLthen
only can be implemented on the hardware. In floating
pointmultiplication,addingofthetwonumbersisdone
with the help of various types of adders but for
multiplication some extra shifting is needed. This
floating point multiplication handles various conditions
like overflow, underflow, normalization, rounding. In
this work they use IEEE rounding method for perform
the rounding of the resulted number.This work focuses
only on single precision normalized binary interchange
format targeted for Xilinx Spartan3 FPGA based on
VHDL.ThemultiplierwasverifiedagainstXilinxfloating
point multiplier core. It handles the overflow and
underflow cases. Rounding is not implemented to give
more precision when using the multiplier in a Multiply
andAccumulate(MAC)unit.
1.2 VEDICMULTIPLIERFORBINARYNUMBERS
The design of high speed and area efficient Binary
Number Multiplier often called Binary Vedic Multiplier
using the techniques of Ancient Indian Vedic
Mathematics i.e.Urdhva Tiryagbhyam Sutra. Urdhva
Tiryagbhyam Sutra is the Vedic method for
multiplication which strikes a difference in the actual
processofmultiplicationitself,givingminimumdelayfor
multiplication of all types of numbers, either small or
large. The work has proved the efficiency of Binary
NumberMultiplierdesignedusingUrdhvaTiryagbhyam
Sutra where multiplication process enables parallel
generation of intermediate products and eliminates
unwantedmultiplicationsteps.Further,theVerilogHDL
coding of Urdhva Tiryagbhyam Sutra for 23x23 bits
multiplication and their implementation in Xilinx
Synthesis Tool on Spartan 3E kit have been done. The
propagationtimefortheproposedarchitectureis26.559
ns.Theworkthenextendsmultiplicationto1616Vedic
multiplier using "NikhilamSutra"technique. The 1616
914

PRAGATI SACHAN et al.

Volume 3 Issue 4: 2015

Citation: 10.2348/ijset07150914
Impact Factor- 3.25

Vediic multiplierr module ussing Urdhvaa Tiryagbhyaam

Sutrrausesfour8
88Vedicmu
ultipliermodu
ules;one16b
bit
carrysaveadderrs,andtwo1
17bitfulladd
derstages.T
The
carrysaveadderrinthemultiplierarchitecctureincreasses
ddition of paartial produccts. The 1616
the speed of ad
i VHDL, sy
ynthesized and
Vediic multiplierr is coded in
simu
ulatedusingX
XilinxISE10
0.1software. Thismultipliier
is im
mplemented on Spartan
n 2 FPGA device XC2S3
30
5pq2
208.Theperrformanceev
valuationresu
ultsinterms of
speeed and device utilization are compareed with earliier
multtiplier archittecture.Vedic Mathematics has a uniq
que
tech
hniqueofcalcculationsbasedon16Suttras.Thiswo
ork
pressents study on
o high speeed 8x8 bit Vedic multipliier
arch
hitecture wh
hich is qu
uite different from the
t
Conv
ventionalmeethodofmultiplicationlikeeaddandshift.
Furtther,theVeriilogHDLcod
dingofUrdhv
vatiryakbhyaam
Sutrra for 8x8 bits multip
plication and
d their FPG
GA
impllementationb
byXilinxSyn
nthesisToolo
onSpartan3k
kit
haveebeendoneaandoutputh
hasbeendisp
playedonLED
Ds
ofSp
partan3kit.T
Theworktheenextendsm
multiplication to
161
16 Vedic multiplier using "Nik
khilam Sutrra"
tech
hnique. The 1616 Vedicc multiplier module usiing
Urdh
hva Tiryagb
bhyam Sutra uses fou
ur 88 Ved
dic
multtiplier modules; one 16 bit carry sav
ve adders, and
two 17bitfullad
dderstages.T
Thecarrysav
veadderintthe
dofadditionof
multtiplierarchiteectureincreaasesthespeed
parttialproducts.The1616V
Vedicmultiplieriscoded in
VHD
DL, synthesized and simu
ulated using Xilinx
X
ISE 10
0.1
softw
ware. This multiplier
m
is implemented
i
d on Spartan
n 2
FPGA
AdeviceXC2
2S305pq208.The16x16V
Vedicmultipliier
usin
ng Nikhilam Sutra found to be bettter than 16x16
Vediic multiplier using Urdh
hva Tiryakbh
hyam Sutra in
term
ms of speed when
w
magnitude of both
h operands are
a
morethanhalfofftheirmaxim
mumvalues.
VEDIC
MATHE
EMATICS
DIFFEREN
NT
1.3
THODOLOGIESFORMUL
LTIPLICATIO
ON
MET
A neew 4bit adder is propo
osed which when used in
multtiplier,reduccesitsdelay. Thismultipliiercanbeused
in applications
a
ng,
such as digital signal processin
encrryption and decryption
d
a
algorithms
in
n cryptograph
hy,
and in other logical
l
comp
putations. This
T
design is
ulated usingg VHDL.A 4 bit add
der has beeen
simu
impllemented in 4X4 multipliier using Ved
dic sutras. Itt is
seen
nthatthespeeedoftheprroposedmulttiplierishigh
her
than
n that of norrmal array multiplier
m
i.e. the delay has
h
been
ndrasticallyrreduced.4X4
4multipliercaanbeextend
ded
to8 bitandhigherordermulltipliers.Thissmultiplierccan
usedinappliccationssuch asdigitalsiggnalprocessin
ng,
beu
encrryption and decryption
d
a
algorithms
in
n cryptograph
hy.
The proposed design
d
can fu
urther be im
mplemented at
nsistor level and verifieed.The Vedicc Multiplier is
tran
testeed by using BIST
B
(Built in Self Test) and it is found
Faullt free. The results
r
are compared
c
wiith the Booth
h's
Multtiplier in terms of time delay
d
and po
ower. The hiigh
speeed processorr requires high speed and low pow
wer
multtipliersandttheVedicMu
ultiplicationttechniqueweere
very
y much suitaable for thiss purpose.Hiigh speed lo
ow
pow
werVedicmultiplierbyco
omparingthissdesignwith
ha
conv
ventional Arrray Multipliier and Boo
oth Multiplier.
Thessemultipliersareimplem
mentedusing VHDLInord
der
togeetthepowerrreportandd
delayreport themultiplieers
are synthesized using Xilinxx ISE tool an
nd Spartan 2E
Aisused.
FPGA
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2.METHODO
OLOGY
2..1VEDICMU
ULTIPLIER
DSPapplicatio
onsessentialllyrequiretheemultiplicationof
mbers. The IE
EEE 754 stan
ndard
biinary floatingg point num
prrovides the format forr representation of Biinary
Flloating poin
nt numbers. The Binary
y Floating point
p
nu
umbers are represented
r
in Single and
d Double form
mats.
Th
heSinglecon
nsistof32bittsandtheDoubleconsistof64
biits. The forrmats are ccomposed off 3 fields; Sign,
Exxponent and
d Mantissa. The Figuree 3.1 showss the
sttructure of Single
S
and D
Double form
mats of IEEE 754
sttandard.IncaaseofSingle,theMantissaaisrepresenttedin
23
3bitsand1 bitisadded totheMSBffornormalizaation,
Exxponentisreepresentedin
n8bitswhich
hisbiasedto
o127,
acctually the Exponent is rrepresented in
i excess 127 bit
fo
ormatandMSSBofSingleiisreservedfforSignbit.W
When
th
he sign bit is 1 that mean
ns the numbeer is negativee and
whenthesign
w
bitis0that meansthenu
umberispossitive.
In
n64bitsform
mattheManttissaisrepreesentedin52bits,
th
heExponentiisrepresenteedin11bitsw
whichisbiasedto
10
023andtheM
MSBofDoublleisreserved
dforsignbit.
2..2.1UrdhvaTriyaKbhya
am(Verticallly&Crossw
wise)
Urdhva tiryak
kbhyam Sutra is a generral multiplication
ormula appliicable to all cases of multiplicatio
on. It
fo
litterally means Vertically and Crossw
wise. To illusstrate
th
his multipliccation scheeme, let us consider the
multiplication
m
of two decimal numbers (5498 23
314).
Th
he conventio
onal method
ds already know
k
to us will
reequire 16 multiplicatio
ons and 15
5 additions.. An
allternative method
m
of m
multiplication
n using Urrdhva
tirryakbhyamSSutraisshow
wninFig.1.1. Thenumbeersto
beemultipliedaarewritteno
ontwoconseccutivesideso
ofthe
sq
quareasshow
wninthefigu
ure.Thesquaareisdivided
dinto
ro
owsandcolumnswhereeeachrow/columncorresp
ponds
to
ooneofthed
digitofeitheramultiplieroramultipliccand.
Th
hus, each digit
d
of the multiplier has
h
a small box
co
ommontoad
digitofthem
multiplicand.T
Thesesmallb
boxes
arre partitioned into two h
halves by thee crosswise lines.
l
Eaach digit off the multip
plier is theen independently
multiplied
m
witth every digiit of the mulltiplicand and
d the
tw
wodigit prod
duct is writteen in the com
mmon box. Alll the
diigits lying on
n a crosswisee dotted line are added to
o the
prreviouscarry
y.Theleastsiignificantdiggitoftheobtaained
nu
umberactsaastheresult digitandtheerestastheccarry
fo
orthenextsttep.Carryforrthefirststeep(i.e.,thedo
otted
lin
neontheextremerightsiide)istakenttobezero.

2..2FLOATING
GPOINTMUL
LTIPLICATIO
ON
915

PRAGATI SACHAN et al.

Volume 3 Issue 4: 2015

Citation: 10.2348/ijset07150914
Impact Factor- 3.25

The multiplier for the floating po

oint numbeers
d
in fo
our
reprresented in IEEE 754 format can be divided
diffeerentunits:

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1..0011x24 and
d B = 1.0011
1x23. IEEE representations of
op
perandsare

Man
ntissaCalculattionUnit
Expo
onentCalculaationUnit
Sign
nCalculationU
Unit

ConttrolUnit
The standardforrmatforreprresentationo
offloatingpoiint
mberis
num
(1))S2E(b0b1
1b2bp1)
The biasedexpon
nente=E+12
27,andthefrractionf=b1b2
p1.
bp
The Mantissa Calculation Unit requirres a 24 bit
b
bitsingleIEEE754formattisconsidereed.
multtiplierif32b
In this
t
work we
w propose the
t
efficientt use of Ved
dic
Multtiplication Teechnique for this 24 bit multiplier. The
T
Expo
onent Calculaation Unit is implemented in this pap
per
usin
ng8BITRipp
pleCarryAdd
der.Theadvan
ntagesofripp
ple
carry adder in addition
a
to itts implementtation ease are
a
mplelayout.
lowareaandsim
N,Infinity,zerro,
The ControlUnittraisestheflaagwhenNaN
overflowcaseesaredetecteed.Thecontrrol
undeerflowando
unit raises appro
opriate flag accordingly
a
w
when
the casses
urs.Thevario
ouscasesand
ditsconstitueentflagsare:
occu
Ife=
=255andf0,thenNaN

perandshowsthesignbitt,the
Here,MSBoftthe32bitop
d the
exxponents aree expressed in excess 127 bit and
mantissa
m
is reepresented in
n 23 bit. Sign
n of the resu
ult is
caalculated by XORing sign
n bits of both
h the operan
nds A
an
nd B. In this case sign biit obtained after
a
XORing is 1.
Exxponents of A and B are added to get the resu
ultant
exxponent.Add
ditionofexpo
onentisdoneusing8bitrripple
caarryadderFiggure3.3.

dtoexcess12
27bit
Affteraddition theresultis againbiased
Co
ode.Forthis purpose127
7issubtracteedfromthereesult.
Tw
wos compllement subttraction usiing addition
n is
in
ncorporatedfforthispurpo
ose.IfERistthefinalresu
ultant
exxponentthen
n,
ER
R=EA+EB127

Ife=
=255andf=0,thenInfiniity
If0<
<e<255,theenNumberis(1)s2e127
7(1f)
If e = 0 and f 0, then (1)ss 2126(0 f)
f (demoralizzed
mbers)
num
Ife=
=0andf=0,thenzero.

WhereEAand
W
dEBarethe exponentpartsofoperan
ndsA
an
ndBrespectiively.InthisccaseER=10000110.Man
ntissa
multiplication
m
is done usin
ng the 24 bitt Vedic Multip
plier.
Th
hemantissa isexpressed in23bitwh
hichisnormaalized
to
o 24 BIT by adding
a
a 1 att MSB. The normalized
n
2 bit
24
mantissasare
m
10
00110000000000000000
0000

10
00110000000000000000
0000
Multiplication
M
of two, 24 b
bit mantissa is done usingg the
VeedicMultiplier.Inthiscase48bitresultobtained after
th
hemultiplicattionofmantisssais
10
01101001000000000000
00000000000
00000000000000
00
00
Nowsettingup
pthreeinterm
mediateresu
ultsthefinalrresult
normalizing the mantiissa by elliminating most
(n
significant1)w
weobtainediis:
1101001000
00000000000
000
11000011001
hisresultisd
deducedas
Th

ure 2.2 show

ws the prop
posed architeecture for the
t
Figu
Floaating point multiplier.
m
Con
nsider the multiplication
m
of
twofloatingpoin
ntnumbersA
AandB,wherreA=19.0and
ntation are A=
A
B = 9.5. The norrmalized binary represen
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AxxB=19.0x9.5
=
=180.5
=
=1.01101001
1x2134127
916

PRAGATI SACHAN et al.

Volume 3 Issue 4: 2015

Citation: 10.2348/ijset07150914
Impact Factor- 3.25

=(10110100.1))2

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ISSN (P): 2395-4752

6bitblockand
dthenfinally
y32x
bllock,8x8bit block,16x16
32
2bitMultiplierasshowniinfigure3.5h
hasbeenmad
de.

=(180.5)10
PROPOSEDD
DESIGN
2.3P
The performanceeofMantissaacalculationU
Unitdominattes
oatingPointM
Multiplier.Th
his
overrallperformaanceoftheFlo
unit requires un
nsigned multtiplier for multiplication of
24BITs.TheVedicMultiplicationtechn
niqueischosen
24x2
forttheimplemen
ntationofthiisunit.Thisttechniquegiv
ves
prom
mising resultt in terms off speed and power [6].T
The
Vediicmultiplicattionsystemiisbasedon1
16Vedicsutrras
orap
phorisms,wh
hichdescribeesnaturalwaaysofsolvingga
who
ole rangeofm
mathematicall problems.O
Out ofthese 16
Vediic Sutras thee Urdhvatriy
yakbhyam su
utra is suitab
ble
fortthispurpose.Inthismeth
hodthepartiaalproductsaare
geneeratedsimulttaneouslywh
hichitselfred
ducesdelayand
mak
kesthismetho
odfast.Them
methodform
multiplicationof
two,, 3 BITs num
mber is show
wn Figure 3.4
4. Consider the
t
num
mbersAandB
BwhereA=aa2a1a0andB
B=b2b1b0.T
The
LSBofAismultip
pliedwiththeeLSBofB:
s0=aa0b0;
Then
na0ismultip
pliedwithb1
1,andb0ism
multipliedwiith
a1andtheresulttsareaddedttogetheras:
1=a1b0+a0b1
1;
c1s1
Hereec1iscarryaands1issum
m.Nextstepisstoaddc1wiith
the multiplicatio
m
n results of a0
a with b2, a1
a with b1 and
a2w
withb0.
c2s2
2=c1+a2b0+aa1b1+a0b2;

Th
hedesignstaartsfirstwith
hMultiplierd
designthatiss2x2
biit multiplier as shown in figure 3.6
6. Here, Urrdhva
Tiiryakbhyam Sutra or Vertically and Crossswise
Allgorithmforrmultiplicatio
onhasbeeneeffectivelyusedto
deevelopdigitaalmultiplieraarchitecture. Thisalgorith
hmis
qu
uite different from tthe traditional method
d of
multiplication,
m
, which is tto add and shift the paartial
prroducts.
To
o scale the multiplier further, Karratsuba Ofman
allgorithmcan beemployed
d.KaratsubaOfmanalgorrithm
isconsideredaasoneoftheefastestwaysstomultiply
ylong
ntegers.Itisb
basedonthed
divideandco
onquerstrateegy.A
in
multiplication
m
of 2n digit integer is reduced
r
to tw
wo n
diigit multipliccations, one ((n+1) digit multiplication
m
, two
n digitsubtracctions,twoleeftshiftoperaations,twon digit
dditionsandtwo2ndigitadditions.
ad

Nextt step is to add

a c3 with the
t multiplicaation results of
a1w
withb2anda2
2withb1.
c3s3
3=c2+a1b2+aa2b1;
Simiilarlythelasttstep
c4s4
4=c3+a2b2;
Now
w the final result
r
of mu
ultiplication of
o A and B is
c4s4
4s3s2s1s0.

HardwareR
Realizationo
of2x2block
Fig3.6:H
Th
he proposed
d multiplications were im
mplemented using
u
tw
wodifferentccodingtechniiquesviz.,con
nventionalsh
hift&
ad
dd and Ved
dic techniquee for 4, 8, 16, and 32
2 bit
multipliers.
m
Itt is evident that there is
i a considerable
in
ncreaseinspeeedoftheVed
dicarchitectu
ure.

For Multiplier, first

f
the basiic blocks, thaat are the 2x2
multipliers haave been maade and theen, using theese
bitm
blocks, 4x4block
k has been made
m
by add
ding the parttial
ductsusingcaarrysaveadd
dersandthen
nusingthis4
4x4
prod

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Th
he number of
o LUTs and slices requirred for the Vedic
V
Multiplier
M
is less and due to wh
hich the power
co
onsumptioniisreduced.A
Alsotherepettitiveandreggular
sttructureofth
hemultiplier makesiteasiertodesign.And
th
he time requ
uired for com
mputing multtiplication iss less
th
hantheotherrmultiplicatio
ontechniques.
An
n Overflow or
o Underflow
w case occurss when the result
r
Exxponent is higher than th
he 8 BIT or lower than 8
8 BIT
reespectively.O
Overflowmayyoccurdurin
ngtheadditio
onof
tw
woExponentsswhichcanb
becompensaatedatthetim
meof
su
ubtracting th
he bias from
m the exponeent result. When
W
ov
verflow occu
urs the overfflow flag goees up. The under
u
917

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Volume 3 Issue 4: 2015

Citation: 10.2348/ijset07150914
Impact Factor- 3.25

flow
w can occur after the subtraction of bias from the
t
expo
onent, it is th
he case when
n the numberr goes below
w 0
andthissituation
ncanbehand
dledbyaddin
ng1atthetim
me
n
n. When the underflow case
c
occur the
t
of normalization
undeerflowflagggoeshigh.

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B is Signed Floating
F
Poin
nt Number. Now we hav
ve to
B
co
onvertvalue ofAtobinaaryformataffternormalizzewe
geet1.0000110
00001x2^7th
henwehave toconvertittinto
IE
EE32 floatin
ng point form
mat then we get 0 10000110
00
00011000010000000000
000 then convert
c
it into
heexadecimal format
f
we geet 0x4306100
00. Now we have
to
o convert value of B to b
binary formaat after norm
malize
weget1.001x
w
x2^1thenweehavetoconv
vertitintoIE
EE32
flo
oating poin
nt format tthen we geet 1 10000000
00
01000000000000000000
000 then convert
c
it into
heexadecimal format wee get 0xC
C0100000. After
multiplication
m
using V
Vedic Multiplier we get
0xxC396D200 the value o
of this hexadecimal no. is
30
01.640625figg 3.1 shows the simulatiion result off this
daata.

3.SIIMULATION
NRESULTS
Weh
havetakentw
woinputsAandBasamultiplierand
multtiplicandthessearefloatin
ngpointsigneedvalueweaare
perfformmultiplierusingVedicAlgorithm betweentheese
inpu
utsandwillb
bestoredino
otheroutput portwhichw
we
havee taken as Z all operations are performing
p
on
positiveedgeofcclock.
ke value of A
A is 134.062
25 and value of
For case I we tak
Biss2.25.HereAisunsigneedfloatingpiintnumberand

Fig3.1:Sim
mulationRessultofCaseI
ForccaseIIwetak
kevalueofA
Ais14.5and
dvalueofBiis
0.37
75. Here A iss signed floating pint num
mber and B is
also a signed Flo
oating Point Number. No
ow we have to
vertvalueof Atobinary
yformatafterrnormalizew
we
conv
get 1.1101x2^3

then we hav
ve to convertt it into IEE32
floatting point format then we get 1 10000010
1101
10000000000000000000
0 then con
nvert it in
nto
hexaadecimal form
mat we get 0xC1680000.
0
. Now we haave

International Journal of Science, Engineering and Technology- www.ijset.in

to
o convert value of B to b
binary formaat after norm
malize
weget1.1x2^
w
^2thenwe havetoconv
vertitintoIE
EE32
flo
oating poin
nt format tthen we geet 1 01111101
10
00000000000000000000
000 then convert
c
it into
heexadecimal format wee get 0xB
BEC00000. After
multiplication
m
using V
Vedic Multiplier we get
0xx40AE0000tthevalueoftthishexadeciimalno.is5.4
4375
figg3.2showstthesimulation
nresultofthisdata.

918

PRAGATI SACHAN et al.

Volume 3 Issue 4: 2015

Citation: 10.2348/ijset07150914
Impact Factor- 3.25

ISSN (O): 2348-4098

ISSN (P): 2395-4752

Fig3.2:Sim
mulationResu
ultofCaseIII
to
o convert value of B to b
binary formaat after norm
malize
weget1.1111
w
1x2^3thenw
wehavetoco
onvertitinto
oIEE
32
2 floating point
p
formatt then we get
g 0 10000010
11
11100000000000000000
000 then convert
c
it into
heexadecimal format wee get 0x4
41780000. After
multiplication
m
usingVedic Multiplierw
weget0x42E8800
th
hevalueofth
hishexadecim
malno.is116
6.25fig3.3sh
hows
th
hesimulation
nresultofthissdata.

For caseIIIwetakevalueof Ais7.5and

dvalueofBis
5.HereAisu
unsignedfloaatingpintnumberandBis
15.5
also aunsignedF
FloatingPoin
ntNumber.N
Nowwehave to
vertvalueof Atobinary
yformatafterrnormalizew
we
conv
get 1.111x2^2 th
hen we havee to convert it into IEE32
floatting point format then we get 0 10000001
1110
00000000000000000000
0 then con
nvert it in
nto
hexaadecimal form
mat we get 0x40F00000.
0
. Now we haave

Fig3.3:Simu
ulationResu
ultofCaseIII

International Journal of Science, Engineering and Technology- www.ijset.in

919

PRAGATI SACHAN et al.

Volume 3 Issue 4: 2015

Citation: 10.2348/ijset07150914
Impact Factor- 3.25

ISSN (O): 2348-4098

ISSN (P): 2395-4752

3.1S
SYNTHESISR
RESULTS
Fig3
3.4showstheeRTLofour code,fig3.5 showsthein
nternalRTLaandfig3.6sh
howsthedeviicesutilizediinourwork. Here
weaattachthesyn
nthesisreporrtofourcode.

g3.4:MainR
RTL
Fig

Fig3
3.5:InternallRTL

Fig3.6
6:DeviceUtillization

PECTS
4.FUTUREEXP
The time taken for multipliccation operattion is reducced
dic
by employing the Vedic algorithms.. Here Ved
multtiplierarchiteectureisproposedforfurrtherreduction
in tiime. Depend
ding on the inputs, the better
b
sutra is
selecctedbytheaarchitectureiitself.Futureeworkcanallso
furth
her extend to increase th
he more speeed and redu
uce
areaa. It can be extended to
o have moree mathematiccal
operrations likee adder/ssubtractor, divider and
International Journal of Science, Engineering and Technology- www.ijset.in

unctions.An im
mprovementt in multiplication
exxponential fu
sp
peed by usin
ng new tech
hniques can greatly imp
prove
sy
ystemperform
mance.

5.CONCLUSIION
Th
his paper named VHDL Implementa
ation of Floa
ating
Po
oint Multip
plier based
d on Vedicc Multiplica
ation
Technique undertook
u
byy the studentt of M.Tech (VERI
(
ARGE SCALE
E INTEGERA
ATION) FOU
URTH SEMESSTER
LA
920

PRAGATI SACHAN et al.

Volume 3 Issue 4: 2015

Citation: 10.2348/ijset07150914
Impact Factor- 3.25

ISSN (O): 2348-4098

ISSN (P): 2395-4752

under the guidance and support of our teacher.The

paper shows the efficient use of Vedic multiplication
methodinordertomultiplytwofloatingpointnumbers.
The lesser number of LUTs verifies that the hardware
requirement is reduced, thereby reducing the power
consumption.

REFERENCES
1. Manoranjan Pradhan et al, Speed Comparison of
16x16 Vedic Multipliers International Journal of
ComputerApplications(09758887)Volume21No.6,
May2011.
2. Brian Hickman et al, A Parallel IEEE P754 Decimal
FloatingPoint Multiplier University of Wisconsin
Madison Dept. of Electrical and Computer Engineering
Madison,WI53706
3. IEEE 7542008, IEEE Standard for FloatingPoint
Arithmetic,2008.

4.RekhaKJames,PouloseKJacob,SreelaSasi,Decimal
FloatingPointMultiplicationusingRPSAlgorithm,IJCA
Proceedings on International Conference on VLSI,
CommunicationsandInstrumentation(ICVCI):2011.
5. Brian Hickmann, Andrew Krioukov, and Michael
Schulte,MarkErle,AParallelIEEE754DecimalFloating
Point Multiplier, In 25th International Conference on
ComputerDesignICCD,Oct.2007.

International Journal of Science, Engineering and Technology- www.ijset.in

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