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Monday, September 6, 2010

Difference between Harvard and Von Neumann computer

architectures
There are basically two types of digital computer architectures. The first one is called Von
Neumann architecture and later Harvard architecture was adopted for designing digital
computers.
Von Neumann Architecture:

It is named after themathematicianand earlycomputer scientistJohn Von Neumann.

The computer has single storage system(memory) for storing data as well as program to be executed.
Processor needs two clock cycles to complete an instruction.Pipelining the instructions is not possible
with this architecture.
In the first clock cycle the processor gets the instruction from memory and decodes it. In the next clock
cycle the required data is taken from memory. For each instruction this cycle repeats and hence needs
two cycles to complete an instruction.
This is a relatively older architecture and was replaced by Harvard architecture.
Harvard Architecture:

The name is originated from "Harvard Mark I" a relay based old computer.
The computer has two separate memories for storing data and program.

Processor can complete an instruction in one cycle if appropriate pipelining strategies are
implemented.
In the first stage of pipeline the instruction to be executed can be taken from program memory.In the
second stage of pipeline data is taken from the data memory using the decoded instruction or
address.
Most of the modern computing architectures are based on Harvard architecture.But the number of
stages in the pipeline varies from system to system.
These are the basic differences between the two architectures.A more comprehensive list can be found here with
respect to ARM class of processors.

vipin at 4:47 AM
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14 comments:
P.Mukesh Kumar December 28, 2012 at 8:02 AM
Satisfied with this answer..Need more explanation.
thank you
Reply

vikas sharma June 7, 2013 at 8:40 PM

very very thanks .....
Reply

surendar September 27, 2013 at 12:19 AM

a gud and simple one
Reply

Sai Tarun Pallati November 3, 2013 at 8:08 AM

thnk u very much
Reply

Anuraagwrites November 25, 2013 at 10:30 PM

thanks a lot. helped a lot. !!!!!
Reply

BekoC December 16, 2013 at 1:41 PM

i'm not sure why pipelining is not allowed on Von Neumann Architecture, is this statement correct?
Reply
Replies
sheik arif hussain October 24, 2014 at 4:17 AM
ARM IS Von Neumann Architecture and pipelining are there.
Reply

Owais Hakeem March 4, 2014 at 1:21 PM

nice nd simple
Reply

Ankush Gangreddiwar April 14, 2014 at 10:14 AM

thanks for helping me , , ,
but yet add some more poins.
Reply

April 26, 2014 at 11:33 PM

great!!!
Reply

jegathesan Jegadezz June 1, 2014 at 8:54 AM

yeah...i got sme details about this nd i understood...thanq.but xplain y pipelining not used n von
neumann,any reason for that????
Reply

Swaminathan Vembu July 15, 2014 at 1:22 AM

Program Memory - Stores Instructions.
Data Memory - Stores Data and their corresponding addresses.
Von Neumann Architecture - Basic Operation.
a. Same area for Program and Data memory.
b. No or Single Pipe-line stage.
c. 2 clock cycles to complete the execution of an instruction.
d. Initially, the instruction is fetched from the program memory - 1st clock cycle.
e. Then the corresponding data is fetched from the data memory. The data address is decoded from
the instruction (here the function of the instruction can also be determined) - 2nd clock cycle.
If pipe-lining where applicable to Von Neumann architecture then wouldn't a set of instruction fetch
and address decode happen in a span of a single clock cycle ? No it would not. How ?
At the start of clock cycle 1 a. Hardware performs first an instruction fetch,decodes the instruction and puts the required data
address on the bus and determines the function to be performed.
At start of clock cycle 2 b. The corresponding data would be fetched based on the address that was obtained from the
instruction.
But since pipe - Lining is not applicable/possible in the Von Neumann case as per the explanation,
there is no question of multiple instruction fetch and address decoding.
The same principle can be applied to the Harvard architecture, but with pipe lining (as per the
explanation) the luxury of multiple instruction fetches and address decodes becomes possible.
Therefore is is now possible to build multiple pipeline stage capable architectures.
Harvard Architecture - Basic Operation.
a. Separate areas for program and data memories.
b. Pipe-lining is possible hence an instruction decode and data fetch may be executed within the
span of a single clock cycle.
c. Initially the instruction is fetched from the program memory.
d. The data address is then decoded along with the functionality and the data is fetched from the
data memory.
e. Pipe-lining ensures that multiple program memory and data memory accesses overlap.
Reply
Replies
Arup October 28, 2014 at 10:11 PM
I don't agree to your statement. If we look at the architecture of ARM7 TDMI based
processor, it's architecture is of Von-Neumann type and still has 3 stage pipe-lining
implemented. You might need to review on this.

Ankur verma January 9, 2015 at 3:32 AM

thnkss, oits hlpful
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