TLE8110EE

SPI and Daisy-Chain

Application Note
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

Automotive Power

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Abstract
Note: The following information is given as a hint for the usage of the device only and shall not be regarded as a
description or warranty of a certain functionality, condition or quality of the device.
This Application Note is intended to describe the TLE8110EE daisy-chain capability and to provide the right
instruments in order to implement a reliable SPI communication in a daisy-chain environment.

Table of Contents
1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2
2.1
2.2
2.3

SPI communication and compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Complete SPI cycle (normal 16-bit protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Complete SPI cycle with compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-bit commands and compactCONTROL (2x8-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2

Daisy-Chain connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TLE8110EE in daisy-chain environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Rule #1: all TLE8110EE routed at the beginning of the daisy-chain . . . . . . . . . . . . . . . . . . . . . . . . 10
Rule #2: do not use compactCONTROL (2x8-bit protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Rule #3: avoid compactCONTROL patterns as first 8-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Rule #4: if DRA/DRACL is issued, NOP command must be sent to next device . . . . . . . . . . . . . . 10
Rule #5: if DRA/DRACL is issued, response of next device must be ignored . . . . . . . . . . . . . . . . . 10
Case of several TLE8110EE connected in daisy-chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5
5.1
5.2
5.3
5.4
5.4.1
5.5
5.5.1

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLE8110EE - normal 16-bit SPI cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLE8110EE - SPI cycle issuing a compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLE8110EE in a daisy-chain - normal SPI cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Issue: daisy-chain cycle with first 8-bit as compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Solution: 8-bit (00H) upfront extention of the SPI frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Issue: DRACL to device.n, response=compactCONTROL for device.n+1 . . . . . . . . . . . . . . . . . . . . .
Solution: NOP to device.n+1, next response ignored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Application Note
2
This document is subject to changes without further notice to customer

4
4
5
6

15
16
18
20
22
24
26
28

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Introduction

Introduction

The TLE8110EE is equipped with a 16-bit Serial Peripheral Interface (SPI), for controlling the device and to query
the diagnosis status. The use of a modulo-8 counter, for checking the SPI frame length, makes the device capable
of daisy-chaining with other devices as long as the total SPI frame is a multiple of 8-bit. Furthermore the
TLE8110EE implements an efficient communication feature called compactCONTROL (or 2x8-bit protocol) which
allows a significant reduction of the Controller workload.
Attention: The 2x8-bit protocol is not intended for a daisy-chain operation and might, under certain
conditions, interfere with the 16-bit protocol, making the daisy-chain impracticable. In this
document a solution will be presented which allows to reliably operate the device in a daisychain environment.
Note: From now on, in this document, the bits 15 to 8 of an SPI word will be referred to as high-byte and the bits
7 to 0 as low-byte, for more flexibility.
Note: Fictitious names, instead of boolean values, will be used for SPI commands/responses that may not
correspond to the names used in the data sheet.
Note: All the figures will show a data flow from the right to the left, in order to have the same view as we would
observe on the oscilloscope measurement and avoid any confusion, see Figure 1.
data flow
MISO (to master)

MSB

Output data

MOSI (from master)

LSB

Input data

MSB

SO

LSB

SI

SI

time

Slave
CS
TLE8110
1

CLK

Master

CS

XC2700
16/32-bit C

CLK

AUDO MAX
TriCore
32-bit C

time
SO

SPI data flow

Figure 1

SPI data flow

Application Note
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Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

SPI communication and compactCONTROL

SPI communication and compactCONTROL

2.1

Complete SPI cycle (normal 16-bit protocol)

In Figure 1 a complete SPI cycle is shown, where in 16 clock pulses a complete command is shifted from
Controller into the TLE8110EE and a complete response is shifted out from the TLE8110EE to the C. The SPI
cycle is composed of the following steps:
1. Cycle-1: CS high-to-low
the reponse to the previous cycle-0 command is made available in the TLE8110EE shift register
2. Cycle-1: Clock 1 to 16
response to cycle-0 is shifted from SO pin to the C (1 bit each clock pulse)
command of cycle-1 is shifted from C into SI pin (1 bit each clock pulse)
3. Cycle-1: CS low-to-high
command of cycle-1 is interpreted by the device
4. Cycle-2: CS high-to-low
the reponse to cycle-1 command is made available in the TLE8110EE shift register
5. etc.
For detailed visual description please refer to Chapter 5.1.

command
(of cycle-0)

command
(of cycle-1)
cycle-1 CS high-to-low:
response to previous cycle-0 made available

TLE8110
response
(to cycle-0)

command
(of cycle-1)
SPI cycle-1

command
(of cycle -1)
cycle-1 Clock=16:
complete response to cycle-0 shifted out
complete command of cycle-1 shifted in

high-byte
TLE8110
response
(to cycle -0)

16-clocks

cycle-1 Clock=8:
8-bit of response to cycle -0 shifted out
8-bit of command of cycle -1 shifted in

TLE8110
response
(to cycle-0)

16-bit

CLK

MOSI (from C)

TLE8110

CS

data flow

MISO (to C)

command
(of cycle-1)

low-byte

cycle-1 CS low-to-high:
command of cycle-1 interpreted

TLE8110
response
(to cycle -0)

command
(of cycle-1)
cycle-2 CS high-to-low:
response to previous cycle-1 made available

TLE8110

command
(of cycle-2)
cycle-2 Clock=8:
8-bit of response to cycle -1 shifted out
8-bit of command of cycle -2 shifted in

TLE8110
response
(to cycle-1)

SPI cycle-2

response
(to cycle-1)

command
(of cycle -2)

time

high-byte

SPI cycle

Figure 2

Normal 16-bit SPI cycle

Application Note
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Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

2.2

SPI communication and compactCONTROL

Complete SPI cycle with compactCONTROL

In Figure 2 a complete SPI cycle is shown, where the 2x8-bit protocol (compactCONTROL) is used for the
TLE8110EE. The SPI cycle is composed of the following steps:
1. Cycle-1: CS high-to-low
the reponse to the previous cycle-0 command is made available in the TLE8110EE shift register
2. Cycle-1: Clock 1 to 8
high-byte of the response to cycle-0 is shifted from SO pin to the Controller
high-byte of compactCONTROL is shifted from Controller into SI pin
low-byte of the response to cycle-0 is overridden with Diagnosis Output Register content (DOx)
3. Cycle-1: Clock 9 to 16
modified response to cycle-0 is shifted from SO pin to C (low-byte overridden)
complete compactCONTROL command is shifted from C into SI pin
4. Cycle-1: CS low-to-high
complete compactCONTROL command of cycle-1 is interpreted by the device
5. Cycle-2: CS high-to-low
Output Pin Feedback Register content (OPF) is provided as high-byte of the reponse
6. etc.
For detailed visual description please refer to Chapter 5.2.

compactCONTROL

response
(to cycle-0)

TLE8110

cycle-1 Clock=16:
modified response shifted out

compactCONTROL

low-byte
TLE8110

cycle-1 CS low-to-high:
full compactCONTROL interpreted

compactCONTROL

TLE8110
00H

TLE8110
DOx

cycle-2 CS high-to-low:
OPF made available as response high-byte
compactCONTROL

SPI cycle-2

OPF

OPF

cycle-1 Clock=8:
8-bit of compactCONTROL shifted in
low-byte of response overridden with DOx

compactCONTROL

high-byte

response
(to cycle -0)

compactCONTROL

SPI cycle-1

response
DOx
(to cycle-0)

cycle-1 CS high-to-low:
response to previous cycle-0 made available

16-clocks

TLE8110

CS

command
(of cycle-0)

16-bit

TLE8110

response
DOx
(to cycle -0)

MOSI (from C)

TLE8110

CLK

data flow

MISO (to C)

cycle-2 Clock=8:
DOx content as response low-byte

compactCONTROL

time

high-byte

SPI cycle - compactCONTROL

Figure 3

SPI cycle with compactCONTROL

Application Note
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Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

2.3

SPI communication and compactCONTROL

16-bit commands and compactCONTROL (2x8-bit)

The use of the highly efficient compactCONTROL communication can interfere with the standard 16-bit response
related to the previous frame, as can be deducted from the above paragraphs. Therefore, as also suggested in
the TLE8110EE data sheet, it is required to issue a NOP command to the device any time that there is a switch
between 16-bit and 2x8-bit protocol. Sending a NOP command before switching to 2x8-bit protocol will have the
effect of ignoring the response related to the SPI cycle immediately before a compactCONTROL command is
issued, please refer to the device data sheet for more details.

Application Note
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Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Daisy-Chain connection

Daisy-Chain connection

The TLE8110EE is designed to be connected in a daisy-chain configuration, the first device output (SO) being
connected to the second device input (SI) etc, Figure 4. Devices designed for daisy-chaining, after having
transferred their own response data on the SO, basically shift through the data as seen on the SI input. In this
configuration the entire SPI chain acts as a shift register. The Controller will send, in cascade, the data addressed
to each device on the MOSI line (Master-Out Slave-In), first the data to the last device (cmd.n, cmd.n-1, etc.). At
the same time all the responses will be shifted on the MISO line (Master-In Slave-Out), first the response of the
last device (resp.n, resp.n-1 etc.), Figure 5. For a detailed visual description please refer to Chapter 5.3.
data flow

SO

SI

slave.3
Other

CS

SO

CLK

SI

slave.2
TLE8110

CS

SO

CLK

slave.1
TLE8110

CS

SI

SI

XC2700
16/32-bit C

CLK
CS
CLK
SO

AUDO MAX
TriCore
32-bit C

daisy -chain connection

Figure 4

Daisy-Chain Connection

slave.1
TLE8110

rsp.2
(to cycle -0)

rsp.1
(to cycle-0)

slave.2
TLE8110

slave.1
TLE8110

from slave.1
rsp.1
(to cycle-0)

rsp.1
(to cycle-0)

cmd.2
(of cycle-1)

cmd.2
(of cycle -1)

cmd.1
(of cycle-1)

slave.2
TLE8110

slave.1
TLE8110

cmd.2
(of cycle -1)

cmd.1
(of cycle-1)

slave.2
TLE8110

slave.1
TLE8110

rsp.2
(to cycle -1)

rsp.1
(to cycle-1)

slave.2
TLE8110

slave.1
TLE8110
rsp.1
(to cycle-1)

cmd.1
(of cycle-1)
cycle-1 Clock=32:
complete rsp.0 to cycle-0 shifted out
complete cmd.1 of cycle-1 shifted in

cycle-1 CS low-to-high:
cmd.1 of cycle-1 interpreted

cycle-2 CS high-to-low:
rsp.0 to previous cycle-1 made available
cmd.2
(of cycle-2)

cmd.1
(of cycle-2)

SPI cycle-2

slave.1
TLE8110

cmd.1
(of cycle-1)

cycle-1 Clock=8:
8-bit of rsp.0 to cycle-0 shifted out
8-bit of cmd.1 of cycle-1 shifted in
cmd.2
(of cycle -1)

slave.2
TLE8110

rsp.2
(to cycle-1)

cycle-1 CS high-to-low:
rsp.0 to previous cycle-0 made available

SPI cycle-1

slave.2
TLE8110

to slave.1
cmd.1
(of cycle-1)

32-clocks

cmd.1
(of cycle-0)

CLK

cmd.2
(of cycle -0)

32-bit
to slave.2
cmd.2
(of cycle-1)

slave.1
TLE8110

rsp.2
(to cycle-0)

from slave.2
rsp.2
(to cycle-0)

MOSI (from C)

slave.2
TLE8110

CS

data flow

MISO (to C)

cycle-2 Clock=8:
8-bit of rsp.0 to cycle-1 shifted out
8-bit of cmd.1 of cycle-2 shifted in
cmd.2
(of cycle-2)

cmd.1
(of cycle-2)

time
SPI cycle - Daisy-Chain

Figure 5

TLE8110EE in daisy-chain, SPI cycle

Application Note
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Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

3.1

Daisy-Chain connection

TLE8110EE in daisy-chain environment

Due to its immediate reaction to the first 8-bit shifted at the input, if coinciding with compactCONTROL bit-patterns,
the TLE8110EE requires a special care when connected in a daisy-chain environment.
Note: No unwanted device operation can be set due to an interference of daisy-chain data with compactCONTROL
commands, but only wrong responses can be expected from the TLE8110EE.
Note: The user must ensure that the first 8-bit shifted into the SI input of each TLE8110EE, after the CS high-tolow transition, are not coinciding with any of the compactCONTROL bit-patterns.
This opens up to a list of basic rules to follow in order to have a reliable SPI communication in a daisy-chain
environment, these few rules are explained in the next paragraphs and some detailed pictures are shown in the
Chapter 5. The full command set with related responses of the TLE8110EE is provided in Figure 6.

Application Note
8
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

Application Note
9
This document is subject to changes without further notice to customer

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TLE8110EE
SPI and Daisy-Chain
Daisy-Chain connection

TLE8110 full command set, highlighted daisy-chain critical bit-patterns

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

3.1.1

Daisy-Chain connection

Rule #1: all TLE8110EE routed at the beginning of the daisy-chain

The TLE8110EE can be connected in daisy-chain with any other device (if equipped with 8-bit multiple SPI):

In general the user has no control of the other devices output

The C output can instead be controlled via software

Therefore, in order to have a full control of the bit-patterns shifted into the SI of the TLE8110EE, all TLE8110EE
must be routed at the beginning of the chain and other devices afterward.

3.1.2

Rule #2: do not use compactCONTROL (2x8-bit protocol)

Of course the compactCONTROL feature is not compatible with the daisy-chain connection, therefore it must
not be used.

3.1.3

Rule #3: avoid compactCONTROL patterns as first 8-bit

In general, if other devices are also connected, according to the rule #1, the first slave on the chain will be a
TLE8110EE, therefore the first 8-bit of the complete SPI frame, even though addressed to the last slave on the
chain, can be interpreted as compactCONTROL, depending on the command set of the last slave. In that case
the response expected from the first TLE8110EE will be altered (low-byte overridden) as shown in Figure 7.
Please refer to Figure 6 for bit patterns to avoid as first 8-bit. Since the command set of non-TLE8110EE devices
is not given, the most general solution is to extend the SPI frame with additional 8-bit, all zeros (00H), at the
beginning. This way there will be no command misinterpretation for the first TLE8110EE on the chain. The last
8-bit of the SPI response has to be thrown away cause they do not represent any useful information, see Figure 7.
For detailed visual description please refer to Chapter 5.4.

3.1.4

Rule #4: if DRA/DRACL is issued, NOP command must be sent to next device

The response of a TLE8110EE (slave.n), which is shifted to the next TLE8110EE (slave.n+1) on the chain, can
also be interpreted as a compactCONTROL if two specific commands are issued:

Diagnosis Register A Read command (DCC_DRA as per data sheet) issued

Diagnosis Register A Clear command (DCC_DRACL as per data sheet) issued

Those two commands are the only ones, in the TLE8110EE command set, that, together with specific
combinations of the channels diagnosis status, can trigger a response which might coincide with a
compactCONTROL command, see Figure 6 and refer to device data sheet for more details. Since there is no
control of the channels diagnosis status, such combinations cannot be avoided: the solution is to send a NOP
command to the next TLE8110EE (slave.n+1) any time a DRA/DRACL command is issued to the previous
TLE8110EE (slave.n), see Figure 8.

3.1.5

Rule #5: if DRA/DRACL is issued, response of next device must be ignored

As a completion of the rule #4, when a DRA/-CL command is issued to the TLE8110EE (slave.n), in the next
SPI cycle the response of the TLE8110EE (slave.n+1) must be ignored, see Figure 8. For detailed visual
description please refer to Chapter 5.5.

3.2

Case of several TLE8110EE connected in daisy-chain

If several TLE8110EE are connected in daisy-chain and a DRA/-CL command has to be sent to all devices in the
chain, the most efficient way to apply the rules #4 and #5 requires 3 SPI cycles, see Figure 9:
1. Cycle 1: Issue DRA/-CL to all odd devices and NOP command to all even devices on the chain
2. Cycle 2:
Ignore responses of all even devices
Issue DRA/-CL to all even devices and NOP command to all odd devices on the chain (opposite of point 1)
3. Cycle 3: Ignore responses of all odd devices
Application Note
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Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Daisy-Chain connection

Issue: first-8-bit of SPI frame (to slave .n) can be interpreted as compactCONTROL by slave .1
data flow

MISO (to C)

rsp.n
(cycle-0)

MOSI (from C)

slave.n
Other
rsp.n
(cycle-0)

slave.1
TLE8110
rsp.1
(cycle-0)

slave.n
Other

slave.1
TLE8110

rsp.1
DOx
(cycle-0)

daisy-chain SPI frame

cmd.n
(cycle -1)

cycle-1: as first 8-bit slave.1 sees a

compactCONTRL
cmd.n
(cycle-1)

cmd.1
(cycle-1)

if first 8-bit are a

compactCONTROL

rsp.n
(cycle -0)

rsp.1
DOx
(cycle -0)
wrong response
from slave.1

slave.n
Other
cmd.n
(cycle-1)

cmd.1
(cycle -1)

cycle-1: end of transfer, wrong

response from slave.1

slave.1
TLE8110
cmd.1
(cycle-1)

Solution: 8-bit (00 H) upfront extension of the SPI frame

SPI data Flow

MISO (to C)

MOSI (from C)
slave.1
TLE8110
rsp.1
(cycle-0)

slave.n
Other
rsp.n
(cycle-0)

daisy-chain SPI frame

cmd.n
(cycle-1)

00H

cmd.1
(cycle-1)

8-bit extension

rsp.n
(cycle-0)

slave.n
Other

rsp.1
(cycle-0)

slave.1
TLE8110
00H

cycle-1: 00H as first 8-bit

cmd.n
(cycle -1)

cmd.1
(cycle -1)

no issue

rsp.n
(cycle -0)

rsp.1
(cycle -0)

00H

slave.n
Other
cmd.n
(cycle-1)

slave.1
TLE8110
cmd.1
(cycle-1)

cycle-1: end of transfer, right

response from slave.1

to be ignored
First 8-bit as compactCONTROL

Figure 7

First 8-bit as compactCONTROL

Application Note
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Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Daisy-Chain connection

Issue: Response of slave .n to DRA/-CL interpreted as compactCONTROL by slave .n+1

data flow

MISO (to C)

rsp.n+1
(cycle-0)

rsp.n
(cycle -0)

MOSI (from C)

slave.n+1
TLE8110
rsp.n+1
(cycle-0)

slave.n
TLE8110
rsp.n
(cycle-0)

slave.n+1
TLE8110
cmd.n+1
(cycle-1)

slave.n
TLE8110

slave.n+1
TLE8110
rsp.n+1
(cycle-1)

slave.n
TLE8110

DRA_DAT

DRA/-CL

cycle-1: DRA/-CL to slave.n

cycle-2: response available upon

CS high-to-low
cmd.n+1
(cycle-2)

DRA_DAT

slave.n
TLE8110

DRA_DAT

if rsp.n to DRA/-CL is a
compactCONTROL

rsp.n+1
DOx
(cycle-1)
wrong response
from slave.n+1

cmd.n+1
(cycle-1)

DRA/-CL

slave.n+1
TLE8110

rsp.n+1
DOx
(cycle-1)

daisy-chain SPI frame

slave.n+1
TLE8110
cmd.n+1
(cycle-2)

slave.n
TLE8110
cmd.n
(cycle-2)

cmd.n
(cycle-2)

cycle-2: slave.n+1 sees slave .n

response as compactCONTRL
cmd.n+1
(cycle -2)

cmd.n
(cycle-2)

cycle-2: end of transfer, wrong

response from slave.n+1

Solution: NOP command sent to slave .n+1 and next frame response ignored
data flow

MISO (to C)

rsp.n+1
(cycle-0)

MOSI (from C)

slave.n+1
TLE8110
rsp.n+1
(cycle-0)

slave.n
TLE8110
rsp.n
(cycle-0)

slave.n+1
TLE8110

slave.n
TLE8110

NOP

DRA/-CL

slave.n+1
TLE8110

slave.n
TLE8110

0000H

DRA_DAT

slave.n+1
TLE8110

slave.n
TLE8110

rsp.n
(cycle -0)

0000HDOx

NOP response
overridden

0000HDOx
NOP response to
be ignored

Figure 8

DRA_DAT

NOP

slave.n
TLE8110
cmd.n
(cycle-2)

DRA/-CL

cycle-1: NOP to slave.n+1

DRA/-CL to slave.n

cycle-2: response available upon

CS high-to-low
cmd.n+1
(cycle-2)

cmd.n
(cycle-2)

cycle-2: slave.n+1 sees slave .n

response as compactCONTRL
cmd.n+1
(cycle -2)

DRA_DAT

slave.n+1
TLE8110
cmd.n+1
(cycle-2)

daisy-chain SPI frame

cmd.n
(cycle-2)

cycle-2: end of transfer, NOP

response ignored by C

Response to DRA -CL as compactCONTROL

DRA/-CL response of slave.n as compacatCONTROL for slave.n+1

Application Note
12
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Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Daisy-Chain connection

Issuing DRA/-CL command to several TLE 8110 in daisy-chain

data flow

MISO (to C)

rsp
(cycle-0)

rsp
(cycle-0)

even

odd

DOx
0000
DRA_DAT
H
to be ignored

even

rsp
(cycle-0)

even

odd

DOx
0000
DRA_DAT
H

odd
2k-1
TLE8110
rsp
(cycle-0)

even
2
TLE8110
rsp
(cycle-0)

odd
1
TLE8110
rsp
(cycle -0)

even
2k
TLE8110

odd
2k-1
TLE8110

even
2
TLE8110

odd
1
TLE8110

NOP

DRA/-CL

NOP

DRA/-CL

even
2k
TLE8110

odd
2k-1
TLE8110

even
2
TLE8110

odd
1
TLE8110

0000H

DRA_DAT

0000H

DRA_DAT

even
2k
TLE8110

odd
2k-1
TLE8110

even
2
TLE8110

odd
1
TLE8110

DRA/-CL

NOP

DRA/-CL

NOP

even
2k
TLE8110

odd
2k-1
TLE8110

even
2
TLE8110

odd
1
TLE8110

DRA_DAT

0000H

DRA_DAT

0000H

even
2k
TLE8110

odd
2k-1
TLE8110

even
2
TLE8110

odd
1
TLE8110

MOSI (from C)
daisy-chain SPI frame
even

odd

even

odd

NOP

DRA/-CL

NOP

DRA/-CL

cycle-1:
NOP to even devices
DRA/-CL to odd devices

cycle-2: response available upon

CS high-to-low
even
odd
even
DRA/-CL

NOP

odd

DRA/-CL

NOP

cycle-2: even devices resp. ignored

NOP to odd devices
DRA/-CL to even devices

to be ignored

odd

DRA_DAT

rsp
(cycle -0)

even
2k
TLE8110
rsp
(cycle -0)

DOx
0000
H

to be ignored

even

odd

DRA_DAT

cycle-3: response available upon

CS high-to-low

cycle-3: odd devices resp. ignored

DOx
0000
H

to be ignored
DRA-CL to several TLE 8110

Figure 9

Issuing DRA/-CL to several device in a chain

Application Note
13
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Conclusion

Conclusion

Text...

Application Note
14
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Appendix

Appendix

In this Appendix a detailed description of the SPI communication between TLE8110EE and C is presented.
Several circumstances are taken in consideration and for each condition the devices registers content are shown
at different time intervals of the communication.
Note: Fictitious names, instead of boolean values, will be used for SPI commands/responses that may not
correspond to the names used in the device data sheet, see Figure 11 for a command/respone names
description.

high-byte

low-byte

15 14 13 12 11 10
16-bit command/response R

Other Used names

CMD = Command

DOX_DAT_ = Diagnosis Output content

RSP = Response

OPF_DAT_ = Output Pin Feedback content

XXX = other used names

CPCTxxx_ = compactCONTROL command

A = to/from device A

DRACL_x_ = Diagnosis Register A Clear

H=upper, L=lower

DRA_DAT_ = Response to DRA/-CL command

00 = related to cycle-0
01 = related to cycle-1 etc.

Figure 10

Commands/Responses names description

Application Note
15
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

5.1

Appendix

TLE8110EE - normal 16-bit SPI cycle

Requested Data
R

Shift Register

Output Register
SI

SI

Loaded Command

SO

SO

High

CS

CLK

CS

CLK

TLE8110

Figure 11

Input Register

Controller

CS=High - Starting condition

Requested Data

Shift Register
R

Output Register
_

SI

SI

Loaded Command

SO

SO

High

CS

CLK

CS

CLK

TLE8110

Figure 12

Input Register

Controller

CS high-to-low - response to cycle-0 is made available at shift register

Requested Data

Shift Register
S

Output Register

SI

SI

Loaded Command

Input Register
R
SO

SO

High

CS

Low

CLK

CLK
1

TLE8110

Figure 13

CS

Controller

Clock=1 - first bit transferred (shifted through)

Requested Data

Shift Register
H

Output Register
_

SI

SI

Loaded Command

Input Register
R
SO

CS

High

Low

Figure 14

CS

CLK

TLE8110

SO

CLK
1

Controller

Clock=4 - first 4 bits transferred (shifted through)

Application Note
16
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Appendix

Requested Data

Shift Register
R

Output Register
_

SI

SI

Loaded Command

Input Register
R
SO

CS

Low

Figure 15

CS

CLK

CLK
1

TLE8110

SO

Controller

Clock=8 - first 8 bits transferred TLE8110EE checks for compactCONTROL (not found)

Requested Data

Shift Register
C

Output Register
_

SI

SI

SO

SO

Loaded Command

Input Register
R

Low

CS

Figure 16

CS

CLK

CLK
9

TLE8110

10 11 12 13 14 15 16

Controller

Clock=16 - data transfer completed

Requested Data
R

Shift Register

Output Register
SI

SI

SO

SO

Loaded Command
C

Input Register
0

CS

Low

CLK

TLE8110

Figure 17

CS

CLK
10 11 12 13 14 15 16

Controller

CS low-to-high - Command interpreted by the TLE8110EE

Application Note
17
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

5.2

Appendix

TLE8110EE - SPI cycle issuing a compactCONTROL

Requested Data

Shift Register
R

Output Register
_

SI

SI

Loaded Command

SO

_ Diagnosis Output Register

SO

High

CS

CS

_ Output Pin Feedback Register

CLK

CLK

TLE8110

Figure 18

Input Register

Controller

CS high-to-low - response to previous cycle made available at shift register

Requested Data

Shift Register
H

Output Register
_

SI

SI

Loaded Command
SO

_ Diagnosis Output Register

SO

High

CS

Low

CS

_ Output Pin Feedback Register

CLK

CLK
1

TLE8110

Figure 19

Input Register

Controller

Clock=4 - 4 bits transferred (shifted through)

Requested Data
compactCONTROL

Shift Register
D

Output Register
0

SI

SI

Loaded Command

Input Register
R
SO

_ Diagnosis Output Register

CS

Low

CS

_ Output Pin Feedback Register

CLK

CLK
1

TLE8110

Figure 20

SO

Controller

Clock=8 - first 8 bits recognized as compactCONTROL, DOx overrides response low-byte

Requested Data
compactCONTROL

Shift Register
C

Output Register
0

SI

SI

SO

SO

Loaded Command

Input Register
R

_ Diagnosis Output Register

Low

CS

CS

_ Output Pin Feedback Register

CLK

TLE8110

Figure 21

CLK
9

10 11 12 13 14 15 16

Controller

Clock=16 - data transfer completed

Application Note
18
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Appendix

Requested Data
O

Shift Register

Output Register
SI

SI

SO

SO

Loaded Command
C

Input Register
0

_ Diagnosis Output Register

_ Output Pin Feedback Register

CS

Low

CLK

TLE8110

Figure 22

CS

CLK
10 11 12 13 14 15 16

Controller

CS low-to-high - compactCONTROL interpreted, OPF set as response high-byte

Application Note
19
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

5.3

Appendix

TLE8110EE in a daisy-chain - normal SPI cycle

Requested Data
R

Shift Register
R

Output Register

SI

SI

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Loaded Command

Input Register

15 14 13 12 11 10 9

SO

SO

High

CS

CLK

CS

CLK

TLE8110 device B

Controller

Requested Data
R

SI

15 14 13 12 11 10 9

SO

Shift Register
R

Loaded Command

CS

CLK

TLE8110 device A

Figure 23

CS high-to-low - each device put the response to previous cycle in the shift register

Requested Data

Shift Register
H

Output Register
_

SI

SI

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Loaded Command

Input Register

15 14 13 12 11 10 9

SO

CS

SO

High

Low

CLK

CS

CLK
1 2 3 4

TLE8110 device B

Controller

Requested Data

Shift Register
P

SI

15 14 13 12 11 10 9

SO

Loaded Command

CS

CLK

TLE8110 device A

Figure 24

Clock=4 - first 4 bits transferred (shifted through)

Application Note
20
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Appendix

Requested Data

Shift Register
C

Output Register
H

15 14 13 12 11 10 9

SI

SI

SO

SO

Loaded Command
C

Input Register
R

CS

L H

CLK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

CS

CLK
26 27 28 29 30 31 32

TLE8110 device B

Controller

Requested Data

Shift Register
C

15 14 13 12 11 10 9

SI

Loaded Command
C

SO

CS

CLK

TLE8110 device A

Figure 25

CS low-to-high - each device interprets its command

Application Note
21
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

5.4

Appendix

Issue: daisy-chain cycle with first 8-bit as compactCONTROL

Requested Data

Shift Register
R

Output Register

SI

SI

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Loaded Command

Input Register

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SO

SO

High

CS

CLK

CS

CLK

TLE8110 device B

Controller

Requested Data

Shift Register
0

SI

15 14 13 12 11 10 9

SO

Loaded Command

CS

CLK

OTHER device A

Figure 26

CS high-to-low - responses made available

if first 8-bit addressed to device A
coincides w ith compactCONTROL

Requested Data

Shift Register
D

Output Register
_

SI

SI

Loaded Command

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Input Register

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SO

CS

SO

Low

CLK

CS

CLK
1 2 3 4 5 6 7 8

TLE8110 device B

Controller

Requested Data

Shift Register
0

SI

15 14 13 12 11 10 9

SO

Loaded Command

CS

CLK

OTHER device A

Figure 27

Clock=8 - first 8-bit addressed to device.A represent a compactCONTROL for device.B

Application Note
22
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Appendix

Requested Data

Shift Register
C

Output Register

SI

SI

SO

SO

Loaded Command
C

Input Register
1

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

CS

L H

CLK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

CS

CLK
26 27 28 29 30 31 32

TLE8110 device B

Controller

Requested Data

Shift Register
C

15 14 13 12 11 10 9

SI

Loaded Command
C

SO

CS

CLK

OTHER device A

Figure 28

CS low-to-high - wrong response from device.B is retrieved

Application Note
23
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

5.4.1

Appendix

Solution: 8-bit (00H) upfront extention of the SPI frame

Requested Data
additional 8-bit 00H
Shift Register
R

Output Register

SI

SI

Loaded Command

Input Register

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SO

SO

CS

CS

CLK

CLK

High

TLE8110 device B

Controller

Requested Data

Shift Register
0

SI

15 14 13 12 11 10 9

SO

Loaded Command

CS

CLK

OTHER device A

Figure 29

CS high-to-low - responses made available

no issue

Requested Data
additional 8-bit 00H
Shift Register
R

Output Register

SI

SI C

Loaded Command

Input Register

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SO

SO

CS

CSLow

CLK

TLE8110 device B

CLK
1 2 3 4 5 6 7 8

Controller

Requested Data

Shift Register
0

SI

15 14 13 12 11 10 9

SO

Loaded Command

CS

CLK

OTHER device A

Figure 30

Clock=8 - no misinterpretation as first 8-bit are all zeros (00H)

Application Note
24
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Appendix

Requested Data

Shift Register
C

Output Register

15 14 13 12 11 10 9

SI

SI

SO

SO

Loaded Command
C

Input Register
R

last 8-bit to be ignored

_ Diagnosis Output Register

_ Output Pin Feedback Register

CS

CS

CLK

CLK

TLE8110 device B

L H

34 35 36 37 38 39 40

Controller

Requested Data

Shift Register
C

15 14 13 12 11 10 9

SI

Loaded Command
C

SO

CS

CLK

OTHER device A

Figure 31

CS low-to-high - correct response from device.B is retrieved

Application Note
25
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

5.5

Appendix

Issue: DRACL to device.n, response=compactCONTROL for device.n+1

Requested Data

Shift Register
R

Output Register

SI

SI

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Loaded Command

Input Register

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SO

SO

High

CS

CLK

CS

CLK

TLE8110 device B (n)

Controller

Requested Data

Shift Register
0

SI

15 14 13 12 11 10 9

SO

_ Diagnosis Output Register

_ Output Pin Feedback Register

Loaded Command

CS

CLK

TLE8110 device A (n+1)

Figure 32

Cycle-1 - CS high-to-low - DRACL issued to device.n (B)

response to DRA/DRACL
can coincide w ith compactCONTROL

Requested Data
R

Shift Register

Output Register
SI

SI

Loaded Command
D

Input Register

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

R
SO

CS

SO

L H

CLK

CS

CLK
26 27 28 29 30 31 32

TLE8110 device B (n)

Controller

Requested Data
R

Shift Register
SI
Loaded Command
1

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SO

CS

CLK

TLE8110 device A (n+1)

Figure 33

Cycle-1 - CS high-to-low - DRACL interpreted, response represents compactCONTROL

Application Note
26
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Appendix

Requested Data

Shift Register
R

Output Register

SI

SI

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Loaded Command

Input Register

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SO

CS

SO

Low

CS

CLK

CLK
1 2 3 4 5 6 7 8

TLE8110 device B (n)

Controller

interpreted as compactCONTROL
Requested Data

Shift Register
T

SI

15 14 13 12 11 10 9

SO

_ Diagnosis Output Register

_ Output Pin Feedback Register

Loaded Command

CS

CLK

TLE8110 device A (n+1)

Figure 34

Cycle-2 - Clock=8 - device.n+1 (A) sees response of device.n (B) as a compactCONTROL

Requested Data

Shift Register
C

Output Register

SI

SI

SO

SO

Loaded Command
C

Input Register
2

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

CS

L H

CLK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

CS

CLK
26 27 28 29 30 31 32

TLE8110 device B (n)

Controller

Requested Data

Shift Register
C

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SI

Loaded Command
C

SO

CS

CLK

TLE8110 device A (n+1)

Figure 35

Cycle-2 - CS low-to-high - wrong response retrieved from device.n+1 (A)

Application Note
27
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Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

5.5.1

Appendix

Solution: NOP to device.n+1, next response ignored

Requested Data

Shift Register
H

Output Register
_

SI

SI

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Loaded Command

Input Register

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SO

CS

SO

High

Low

CS

CLK

CLK
1 2 3 4

TLE8110 device B (n)

Controller

Requested Data

Shift Register
P

SI

15 14 13 12 11 10 9

SO

_ Diagnosis Output Register

_ Output Pin Feedback Register

Loaded Command

CS

CLK

TLE8110 device A (n+1)

Figure 36

Cycle-1 - Clock=4 - DRACL issued to device.n (B) and NOP command to device.n+1 (A)

Requested Data
R

Shift Register
R

Output Register

SI

SI

Loaded Command

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Input Register

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SO

CS

SO

L H

CLK

CS

CLK
27 28 29 30 31 32

TLE8110 device B (n)

Controller

Requested Data
0

SI

15 14 13 12 11 10 9

SO

_ Diagnosis Output Register

_ Output Pin Feedback Register

Shift Register
0

Loaded Command

CS

CLK

TLE8110 device A (n+1)

Figure 37

Cycle-2 - CS high-to-low - Response to DRACL is a compactCONTROL

Application Note
28
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Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Appendix

Requested Data

Shift Register
R

Output Register

SI

SI

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Loaded Command

Input Register

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SO

CS

SO

Low

CS

CLK

CLK
1 2 3 4 5 6 7 8

TLE8110 device B (n)

0
7

Controller

Requested Data

Shift Register
T

SI

15 14 13 12 11 10 9

SO

_ Diagnosis Output Register

_ Output Pin Feedback Register

Loaded Command

CS

CLK

TLE8110 device A (n+1)

Figure 38

Cycle-2 - Clock=8 - device.n+1 (A) sees response of device.n (B) as a compactCONTROL

Requested Data

Shift Register
C

Output Register

SI

SI

SO

SO

Loaded Command
C

Input Register
2

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

response to be ignored
CS

L H

CLK

CS

CLK
26 27 28 29 30 31 32

TLE8110 device B (n)

Controller

Requested Data

Shift Register
C

15 14 13 12 11 10 9

_ Diagnosis Output Register

_ Output Pin Feedback Register

SI

Loaded Command
C

SO

CS

CLK

TLE8110 device A (n+1)

Figure 39

Cycle-2 - CS low-to-high - response from device.n+1 (A) has to be ignored

Application Note
29
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Additional Information

Additional Information

Description ...

Existing App. Note (Title)

For further information you may contact http://www.infineon.com/

Application Note
30
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

TLE8110EE
SPI and Daisy-Chain
CONFIDENTIAL

Revision History

Revision History

Revision

Date

Changes

0.2

2011-06-14

Improved quality of Figure 6 and Figure 10, colors fixed

Changed device to slave in daisy-chain description, use of high/low-byte
Mentioned C examles (XC2700, AUDO MAX)

0.1

2011-06-10

Draft

Application Note
31
This document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14

Edition 2011-06-14
Published by
Infineon Technologies AG
81726 Munich, Germany
2011 Infineon Technologies AG
All Rights Reserved.
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