Lecture-32

Problem 1:
An output port with an 8-bit register latch driver is interfaced
using isolated I/O PORT address 30H. This register latch driver o/p
driver

o LED (0-0ff, 1-on) write a software programmed in MLP to

simulate a 8-bit ring counter as the PORT 30h. Ring counter

Must go from one state to the nest in 10 sec k m sec delay
subroutine

programmed is available to you from the starting

address, 0430h, write your programmed from 0800h,

Note: For 1 T.T.T load when at is high current dram is 40 u amp
called sourcing currant when logical 0 wits then Io1 = -10ma (sinking
current) most of the J.C chip can take 10 T.T.L load,

In the ring counter only one F/F is set at a time

NEXT:

LXI

B. 10000D

MVI

A,

OUT

30 H

CALL

KDLEY

80 H

RRC
JMP

NEXT

Problem 2:
Simulate a BCD counter for up counting, the creating should be
MOP-@% BCD up counting this should go from one state to other in
10-sec,
Sample:
Write a SUBROUTINE programmed to multiply two unsigned number,
the multiply is inputted as a 16-bit number through (D,E) pain, the
multiplier is inputted to the subtractive through the accuse emulator
in the (HC) pain register on RETURN, in the process of multiplication
no register should be destroyed except (H,L) pain the a longtime
used for unsigned multiplication can be best on explained by taking a
simple example consider 4 bit multiplication.
(7x10)D

= 70D

Multiplication =
Multiplication =
Partial

Sum=

0111

B=

1010

0000

0111

B=

0000

ADD MULITIPLICAND

0000
0000

0000

0000

0111

0000
SHIFT LEFT

0000

0111
0111

NO ADDITION
SHIFT LEFT

0000
0001

ADD MULITIPLICAND
SHIFT LEFT
NO
NO

ADDTION
SHIFITING

1110
1110

0000

0111

0100

0110

0100
0100

0110
0110 =

70D
From this simple up see dearly the algorithm chook the multiplier bit
starting from MSB, if Multiplier bit is 1, add the multiplicand to correct
partial production and them shift the partial production by one bit to
the left if the current multiplier bit is zero, do not add the multiplicand
only shift left the partial production by one bit repeat this number of
times for n bit multiplier few more refinements nil be done when we
draw the flow chart is shown in fig -18,

Fig -19 given the ALP for subroutine programmed

UNS MUL:

LIX

H, OOOOH

ANA

RZ
POSHB
MVI
NEXT:

B, 08 H

DAD H
RLC
JNC

TEST

DAD D
TEST:

DCR B
JNZ NEXT
POP B
RET

The fig-20 give is the summary of the subtraction

is the proper

format, proper formatting of subroutine is necessary because once

the subroutine is satisfaction fig tested, it can be used as library for a
further use, if can be used by anybody having access to this library
provided the relevant information are given as per fig-20,
SUBROUTINE NAME:

UNSMUL

INPUT:
In this we should give the parameter passed from the main
programmed to the subtraction Programmed in this case multiplicand
in (O, E) pair & multiplier is ACC.

OUTPUT:
CALLS:

PRODOCT IN (H, L)
NOTHING

DESTROYS: (H, L) PAIR

DESCRIPTION:

THIS SUBRCOTION MULTIPLTES A 16-BIT

MULTIPLICAND BY AN 8 - BIT MULTIPLTE TO GIVE 16- BIT

PRODCT.
Example: write a subroutine to obtain
SUM =
It is assumed that 80M can be accounted in 16-bit, the coefficients ,
DTN are the +ve integers and stored is a look up table from the
starting address COEFF.
The variable X is an unsigned 8-bit integer inputted from PORT
whose symbolic address is PRTX through isolated I/O. the subroutine
is entered in this all the coefficients entered is the look up take as
explained and the starting address COEFF, namely

available in memory location CLP to (qp+1) and the no is available in

B register,

On return from the subroutine the SUM should be available is (H, L)

pain. If is the only register destroyed by the subroutine we can make
use of the subroutine cretin earlier for aligned, multiplication of two
numbers,
SUBROUTINE:
INPUT

USMUL
:

MULTIPLIER=(A)
MULTIPLICAND= (D,E)

OUTPUT

(H,L)= PRODUCT

CALLS

NOTHING

DESTROY

(H, L) pain

Description of the subroutine to be written is given following format,

SUBROUTINE: SUM

(POLSM)

INPUT

: (I) Coefficients are arranged in the starting

address COERF

is parsed through two memory location CLP

and (CLPH),
OUTPUT: SUM=
CALLS

x is (H, L) pain

: USMUL

DESTRCYS : (H, L)
Algorithm: SUM
POLSM:
WORD

POSH

PSW

; SAVE PROCESSOR STATOS

POSH

; SAVE (D, E) PAIR

POSH

; SAVE (B, C) PAIR

LXI

D, 0000H; INITIALIZE RONNING SUM

IN PRTX

INPUT X VALUE PROMPRTX IN

10ACC
NEXT:

LHLD CLP

; LOAD (H, L) WITH CLP

MOV.C, M

; BRING CORRENT COEFF INTOC

INX H

; (H, L) POINTS TO NEXT COEFF.

SHLD CLP

; SAVE THE NEXT COFEE ADDR IN

CLP
MOV L, C

; BRING

MVI H, 004

CURRENT COEFF IN (L)

; EXTEND THE COEFF TO

RONNING
SUM, RUNNING SUM IS NOW IN
(H,L)
XCHG

; CURRENT MULTIPLICAND IS NOW

IN
PROPER POSITION
CALL USMUL; CURRENT PRODUCT IS IN (H,L)
PAIR
XCHG

; UPDATE THE RUNNING SUM IN

(DF)
DCR

JNA NEXT

; ALL PONE
; NO

LHLD CLP

; (H, L) PAIR NOW POINTS TO ao

MOV L, M

; BRING ao TO

MVI H, OOH

; EXTEND IT TO 16-BITS

(L)

DAD D

; (H, L) NOW CONTAINS

TOTAL

SUM
POP B
POP D
POP PSW
RET
EXAMPLE; It is desired to divide a

16 bit number in locations 2000

and 2001 (HIGH BXTE IN 2001) by an 8-bit number is location 2002

using the division algorithm
a)

Flowchart the problem

b)

Convert the flowchart to an 8085 MLP

2000

DATA

2001

DATA

2002

DATA

2003

DATA

2004

MVI D, 00

; INITIALIZE

2006

LIX

;( H,L) points to 20004

2009

MOV A, M, LOWER BYSE OF DIVIDEND IN

H, 2000

D= 00

(A)
200A

LXI 4, 2002

; (4, U POINT

TO

2002H
200D

ANA

To CLEAR THE or

(Dividend L200F

SBB

Davison-L)
200F

LXI

M, 2000H

same the serum of

subtract in 2000h
2012

MOV

M,

2013

LXI

H, 2001H,

(Dividend h-Divisor CY)

2016

MOV

A, M

save it is 200 TH

2019

LIX H, 2000H

201A

SBBM

201 B

LIX H, 2001H

201E

MOV M,A

201F

JP 2026

2022

LIX H, 2000

(A)

(Dividend L)

2025

MOVA, M

2026

LXI H, 2002

2029

ADD

202A

MOV D, A

202B

HLT

202C

INRD

202D

JMP 2006

L)

(A)-1(M)

00001010
0011

(M) (Divison

0011

(E) A

- increment D.

0100

0000

0011

0010
00

0000

0001

0001

0010/10

0010

00001000/0000000101
0101
0011
0010/0000

0001 0000
000000011

0010
00100
0000