Professional Documents
Culture Documents
Data Sheet
HDG104
WiFi SIP component
Data Sheet
HDG104
Revision History
Revision
Revision date
Description
PA1
2009-08-24
First issue
PA2
2009-09-18
Reference designs
PA6
2009-11-13
PA7
2009-11-13
Review edits
2009-11-15
First release
All trade names, trademarks and registered trademarks mentioned in this document are property of their respective
owners, and are hereby acknowledged.
Copyright 2009 H&D Wireless AB. All rights reserved.
Rev. A. 11/2009
page 2 ( 35)
Data Sheet
HDG104
INTRODUCTION ........................................................................................................... 5
1.1
Overview ......................................................................................................................................................... 5
1.2
2.1
2.2
ELECTRICAL DATA..................................................................................................... 7
3.1
3.2
ESD ................................................................................................................................................................. 7
3.3
3.4
3.5
RF Performance ............................................................................................................................................. 9
3.6
4.1
4.2
5.1
5.2
Clock ............................................................................................................................................................. 17
5.3
Reset .............................................................................................................................................................. 20
5.4
Shutdown ...................................................................................................................................................... 20
5.5
5.6
5.7
Shutdown sequence...................................................................................................................................... 22
5.8
5.9
Interfaces ...................................................................................................................................................... 24
5.10
RF interface .................................................................................................................................................. 24
Rev. A. 11/2009
page 3 ( 35)
Data Sheet
5.11
HDG104
5.13
6.1
6.2
6.3
6.4
7.1
IEEE/IETF ................................................................................................................................................... 32
7.2
WiFi .............................................................................................................................................................. 32
7.3
Regulatory .................................................................................................................................................... 32
9.1
Rev. A. 11/2009
page 4 ( 35)
Data Sheet
HDG104
1 INTRODUCTION
1.1 Overview
HDG104 is a complete WLAN System In Package, SIP, solution specifically designed to address
the proliferation of Wi-Fi technology into embedded devices. HDG104 enables a cost efficient ultra
low power, high performance and feature rich client solution. It provides up to 54 Mbit/s data rate
when operating in the OFDM mode and up to 11 Mbit/s data rate when operating in the DSSS/CCK
mode.
HDG104 integrates RF IC, baseband/MAC IC, EEPROM and RF filters into a highly integrated and
optimized SIP (System In Package) solution with high quality and reliability. This minimizes the
need of external components, simplifying assembly and test.
The integrated circuits are implemented in state of the art processes like SiGe in 0.35um for the
radio and 0.13um 1.2V CMOS for the baseband/MAC. This highly integrated solution is optimized
for customer applications running on a host CPU.
The host interface supports SDIO/SPI and UART. Internal RAM comprises both code and data
memory eliminating the need for external RAM, Flash or ROM memory interfaces. Baseband
firmware, FW, is stored on the host and downloaded at start up. MAC address, trimming values etc
are stored in the on board EEPROM.
Data Rates: 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54Mbps
Modulation: QPSK, 16QAM, 64QAM DBPSK, DQPSK, CCK, OFDM with BPSK
WEP and AES hardware encryption accelerator up to 128 bits
Adjustable output power. Max +18dBm (CCK).
Advanced on-chip RF filter
Selection (DFS) for spectrum management and Transmit Power Control (TPC).
Low power consumption due to efficient class AB PA design
LDO:s for RF-VCO and crystal oscillator for lower pushing
An internal 32 kHz oscillator maintains real time in power save mode, allows the high
frequency clock to be turned off.
Support for an external 32kHz real time clock
Extensive DMA hardware support for data flow to reduce CPU load.
External clocks 16.8, 19.2, 26, 38,4 and 40MHz supported
With external 40MHz crystal internal trimming capacitors allows the use of low cost crystal
On-board 160 kB SRAM and 1 kB EEPROM eliminates need for external FLASH, RAM and
EEPROM.
Internal Boot-ROM. This allows firmware to be downloaded into SRAM from the host
Advanced power management for optimum power consumption at varying load.
Bluetooth Coexistence support
External interfaces SDIO/SPI and UART
Power Supplies 2.75-3.6 V and 1.2 V
Small footprint 7.1x7.7 mm (55 mm2), height 1.4 mm max
RoHS Compliant
Rev. A. 11/2009
page 5 ( 35)
Data Sheet
HDG104
2 HARDWARE ARCHITECTURE
2.1 Block Diagram
Clock option
Package
Shipment package
HDG104/2
HDG104/3
Tray
Rev. A. 11/2009
page 6 ( 35)
Data Sheet
HDG104
3 ELECTRICAL DATA
3.1 Absolute maximum ratings
Rating
Min
Max
Unit
Supply voltage
10
dBm
+125
260
Input RF level
Storage temperature
-50
C
C
Table 3.1: Abolute maximum ratings. Exceeding any of the maximum ratings, even briefly lead to deterioration in performance
or even destruction. Values indicates condition applied one at the time.
*Ref. IPC/JEDEC J-STD-020C, July 2004
3.2 ESD
HDG104 withstands ESD voltages up to 2000 V tested with HBM (Human Body Model)
according to JESD22-A114 and up to 300 V tested with MM (Machine Model) according to
JESD22-A115.
Min
Typ
Max
Unit
2.75
3.3
3.6
2.7
VBAT_P0.6
3.3
3.6
3.3
3.6
1.15
1.20
1.25
1.7
3.3
3.6
Operating temperature
Operating temperature, reduced spec, no
damage.
-20
+25
+70
-30
+25
+85
C
C
Rev. A. 11/2009
page 7 ( 35)
Data Sheet
HDG104
Conditions
Parameter
Voltage
All modes
VBAT_P+VCC+
VPA+VBAT_32K
All modes
Min
Typ
Max
Unit
3.6 V
250
mA
VPA
3.6 V
150
mA
All modes
VBAT_P+VCC
3.6 V
150
mA
All modes
DVDD
1.2 V
100
mA
All modes
25C
VBAT_32K
3.3 V
10
Tx
25C
DVDD
1.2 V
15
mA
Rx
25C
1.2 V
60
mA
Sleep
25C
DVDD
VBAT_P+VCC+
VPA+VBAT_32K
3.3 V
30
Sleep
Soft
Shutdown
Soft
Shutdown
25C
DVDD
VBAT_P+VCC+
VPA+VBAT_32K
1.2 V
110
3.3 V
20
1.2V
70
Shutdown,
DVDD
VBAT_P+VCC+
VPA+VBAT_32K
3.3 V
15
25C
25C
Comments
TX 802.11b
+17 dBm
725 mW
1, 2, 5.5, 11 Mbit/s
TX 802.11g
+14 dBm
590mW
RX 802.11b
N/A
220mW
RX 802.11g
N/A
230mW
Power Save
Sleep
N/A
0,4 mW
N/A
0,2mW
Soft Shutdown
N/A
0,15 mW
Shutdown
N/A
0,05 mW
Rev. A. 11/2009
page 8 ( 35)
Data Sheet
HDG104
Electrical data
3.5 RF Performance
VCC=VPA= 2.75 3.6V, DVDD=1.15 - 1.25V External supply, Tamb= -20 +70C
Parameter
Conditions
Min
Frequency range
Typical
2400
RF impedance
Max
Units
2500
MHz
50
ohm
Transmitter performance
Output power
Output power
QPSK, Calibrated.
OFDM 54Mbit/s,
Calibrated.
+16,5
+17
+17,5
dBm
+13,5
+14
+14,5
dBm
EVM at +15dBm
QPSK
30
35
EVM at +11dBm
OFDM 54MBit/s
3.5
Receiver sensitivity
DPSK 1Mbit/s
-96
dBm
Receiver sensitivity
-92
dBm
-91
dBm
Receiver sensitivity
QDPSK 2Mbit/s
CCK/DPSK
5.5Mbit/s
CCK/BPSKK
11Mbit/s
-88
dBm
Receiver sensitivity
OFDM 6Mbit/s
-91
dBm
Receiver sensitivity
OFDM 9Mbit/s
-90
dBm
Receiver sensitivity
OFDM 12Mbit/s
-88
dBm
Receiver sensitivity
OFDM 18Mbit/s
-86
dBm
Receiver sensitivity
OFDM 24Mbit/s
-83
dBm
Receiver sensitivity
OFDM 36Mbit/s
-80
dBm
Receiver sensitivity
OFDM 48Mbit/s
-76
dBm
Receiver sensitivity
OFDM 54Mbit/s
-74
dBm
Receiver performance
Receiver sensitivity
Rev. A. 11/2009
page 9 ( 35)
Data Sheet
HDG104
Electrical data
Symbol
Min
tISU
ns
tIH
ns
tTHL
10
ns
tTLH
10
ns
tODLY
40
ns
Max
ns
Parameter
Comments
Rev. A. 11/2009
dat
page 10 ( 35)
Data Sheet
HDG104
Parameter
Symbol
Min
Max
ns
tTHL
ns
tTLH
ns
tODLY
2,5
14
ns
tOH
2.5
Comments
ns
Figure 3.3: Function schematics of the IPU and IPD input pad configurations.
Parameter
Symbol
Min
VIL
VIO
Typ
Max
Units
-0.3
0.25*VIO
VIH
0.625*VIO
VIO+0.3
IIL
-1
CIP
2,5
1.7
Comments
pF
3,6
Electrical data
Rev. A. 11/2009
page 11 ( 35)
Data Sheet
HDG104
Parameter
Symbol
Min
VIL
VOL
VOH
VDDIO, VDD_SDIO
VIO
Typ
Max
Units
-0.3
0.25*VIO
VIH
0.625*VIO
VIO+0.3
IIL
-1
0.125*VIO
Iout<1mA
Iout>-1mA
0.75*VIO
2.5
CIP
1.7
Comments
pF
3.6
Rev. A. 11/2009
page 12 ( 35)
Data Sheet
HDG104
.
Figure 3.5: Schematics of analogue inputs A1 and A2
Two digital inputs, DCDC_ENABLE and SHUTDOWN use the analog pad A1.
DCDC_ENABLE is a dedicated pin used for controlling the internal DC/DC converter. SHUTDOWN is a
dedicated pin used for controlling the shutdown function.
For pin data see table: 3.10 and table: 3.11 respectively.
Parameter Symbol Min Typ Max
Parameter
Symbol
Min
VIL
Typ
Max
Units
-0.3
0.3
VIH
VBAT_P+0.3
IIL
-1
Input capacitance
IIN
pF
Parameter
Symbol
Min
VIL
Typ
Max
Units
-0.3
0.2
VIH
1.5
VBAT_32K+0.3
IIL
-1
+1
Input current
IIN
mA
Comments
During low to
high transition
Rev. A. 11/2009
page 13 ( 35)
Data Sheet
HDG104
4 PIN CONFIGURATIONS
4.1 Pin Configuration
Function
Type
Description
SDIO DAT0
I/O
SDIO DAT1
I/O
GND
Ground
ANT_WLAN
RF
COEX4
I/O
ICE_TDI
IPU
ICE_TRST
IPU
ICE_TCK
IPU
SPI_EN0 I/O
I/O
10
ICE_TMS
IPU
11
VPA
12
ICE_TDO
I/O
Rev. A. 11/2009
page 14 ( 35)
Data Sheet
HDG104
13
COEX3
I/O
14
COEX2
I/O
15
RF_CTRL_ANT0
I/O
16
RF_CTRL_ANT1
I/O
17
DVDD
18
HFC_EN
I/O
19
VCC_REG_VCO
20
VCC
21
COEX0
I/O
22
VCC_REG_PLL
23
SHUTDOWN
A1
24
25
40MHz IN/EXT_REF_IN
40MHz OUT/
EXT_REF_OP
26
DCDC_ENABLE
A1
27
VDD_CKL_12
28
VDD_CKL_26
29
VBAT_32K
30
TEST_EN
IPD
31
DCO
32
COEX1
I/O
33
VBAT_P
34
RESET_N
IPU
35
I/O
36
EXT_PWR_EN
LFC(Sleep CLK)_IN/
GPIO0
I/O
37
VDD_IO
38
HOST_WAKEUP
I/O
39
SDIO DAT3
I/O
40
SDIO CMD
I/O
41
VDD_MAC_BB
42
VDD_SDIO
43
SDIO DAT2
I/O
44
SDIO CLK
IPU
Rev. A. 11/2009
page 15 ( 35)
Data Sheet
HDG104
45
GND
Ground
45
GND
Ground
45
GND
Ground
45
GND
Ground
Rev. A. 11/2009
page 16 ( 35)
Data Sheet
HDG104
5 APPLICATION INFORMATION
5.1 Power Supply
HDG104 should be powered by dual supplies 3.3V and 1.2V (typ).
The device has an on board DC/DC converter to generate a 1.2 V supply from the 3.3V supply
but the reccomendation is to use an external 1.2 V supply.
5.2 Clock
The circuit has an internal oscillator driver that only needs a 40 MHz external crystal and one
capacitor to generate the clock signal. The crystal is connected between the pins 40MHz_IN and
40MHz_OUT. A 0.5 pF capacitor should be connected between the 40MHz_IN and 40MHz_OUT
pins. The crystal should be placed as close as possible to the circuit pins. Stray capacitances to
GND for crystal interconnect traces should be as small as possible. See Fig. 5.1.
Rev. A. 11/2009
page 17 ( 35)
Data Sheet
Parameter
HDG104
Condition
Min
Typ
Max
Unit
Frequency
40
MHz
CL
pF
Cm
3.5
6.0
fF
C0 (shunt cap)
0.5
2.0
pF
Equiv Rs
60
ohm
Frequency tolerance
Ta=25 C
-15
15
ppm
Freq vs temp
-15
15
ppm
Paramete
r
Condition
Min Max
Unit
Figure 5.2: External reference clock connection. (a) best noise performance.(b) for best PSRR performance.
Rev. A. 11/2009
page 18 ( 35)
Data Sheet
HDG104
Min
Load resistive
10
Typ
Max
Unit
Note
Kohm
Load capacitive
10
pF
Clipped sine wave
AC-level
0.5
1.2
Vp-p
-15
15
ppm
+/- 1kHz
+/-10kHz
+/-10kHz +/-100kHz
16.8MHz
-124
-144
dBc/Hz
19.2MHz
-123
-143
dBc/Hz
26MHz
-121
-135
38.4MHz
-117
-137
-140
Unit
dBc/Hz
dBc/Hz
Min
Typ
Max
Unit
LFC frequency
30
32
34
kHz
Clock accuracy
-2000
2000
ppm
Duty cycle
30
70
50
Note
Rev. A. 11/2009
page 19 ( 35)
Data Sheet
HDG104
5.3 Reset
The RESET_N pin is active low. It has an internal pullup, can be left unconnected. Pulling the
RESET_N pin low resets all digital logic.
Note: An internal RESET is generated at Power On with the same function as pulling the
RESET_N pin low. All VBAT power supply pins must be discharged close to GND, typically below
0.2 Volt, for this Power On Reset to be generated at a following Power On.
5.4 Shutdown
HDG104 can use two shutdown modes HW SHUTDOWN and Soft SHUTDOWN.
5.4.1 HW Shutdown
The SHUTDOWN pin shall be set high during normal operation. Pulling the SHUTDOWN pin low,
sets HDG104 in Shutdown mode. This turns OFF most parts of the circuit and minimizes the
current consumption. All I/O interface pins are set to predefined states (high, low or high-z) when in
Shutdown mode. For minimum power consumption keep VBAT_P and VCC ON but turn DVDD,
external 1.2 V, OFF while the SHUTDOWN pin is low.
To end Shutdown mode set SHUTDOWN pin high and reload FW and MIB.
The state of all interface pins during Shutdown mode can be defined in a MIB setting to suite a
particular application. Due to HW limitations some I/O-pin setting combinations are not possible. In
these cases use instead Soft Shutdown. For more information regarding the use of SHUTDOWN
refer to Power On sequence and Shutdown sequence.
Note: During Power ON, with SHUTDOWN low, before loading of FW, pin EXT_PWR_EN is high
and all other I/O-pins are high-z. With SDHUTDOWN high, load FW and let it start, then when
SHUTDOWN is set low all I/O-pins will be set according to their FW defaults or MIB settings.
Application Information
Rev. A. 11/2009
page 20 ( 35)
Data Sheet
HDG104
Application Information
.
Figure 5.3: Start up sequence with 40 MHz crystal and FW loaded from host via SDIO.
Parameter
Symbol
Min
tVDDIO
tSHUTDOWN
tVBAT_SU
-0.2 )
tSHUTDOWN
tVDD_P_SU
-0.2 )
tSHUTDOWN
Reset time
SPI_EN0 turn low
time
40 MHz OSC start
up time2.5
BB1 HW start up
time 1
BB2 HW start up
time 2
Firmware loading
delay time
Firmware loading
time
Typ
Max
Unit
Comment
ms
ms
ms
ms
External 1.2 V supply
ms
tRESET
tSPIEN_L
0.02
tXTAL_ST
2.5
tBB1
ms
ms
ms
At 32.768 kHz
ms
tBB2
At HFC 40 MHz
ms
tFW_LOAD_D
20
ms
tFW_LOAD
Rev. A. 11/2009
100
At HFC 40 MHz
SDIO clock and host
SW
page 21 ( 35)
Data Sheet
HDG104
dependent
tMIB_LOAD_D
ms
20
ms
tMIB_LOAD
At HFC 40 MHz
Value at 16 MHz SDIO
clock.
Application Information
Figure 5.4: Shut down and start up sequence with 40 MHz crystal osc. and FW loaded from host.
Parameter S
Rev. A. 11/2009
page 22 ( 35)
Data Sheet
HDG104
Parameter
Symbol
Min
FW loading delay
time
tFW_LOAD_D
20
FW loading time
tFW_LOAD
tMIB_LOAD_D
tMIB_LOAD
Typ
Max
Unit
Comment
ms
100
20
5
ms
ms
At HFC 40 MHz
ms
At HFC 40 MHz
Table 5.6: Shutdown timing with external 1.2 V supply, crystal and FW load from host. Max Unit Comment
Parameter
Symbol
Min
Typ
tVDDIO_OFF
tVBAT_OFF
tVDDIO_OFF
tDVDD_OFF
tVBAT_OFF
Max
Unit
Comment
s
s
s
ms
tINPUTS_OFF
tIO_Z
Rev. A. 11/2009
page 23 ( 35)
Data Sheet
HDG104
5.9 Interfaces
The HDG104 is equipped with a number of interfaces that can be set up in various ways.
5.9.2 SPI
The SPI interface is only used on board HDG104 to connect to a small EEPROM, that stores
individual data (MAC address, calibration data etc.). SPI_EN0 is however available on pin 9. It is
sampled by onboard Boot ROM FW at Power On Reset. A high level selects SDIO-mode, a low
levels selects UART-mode. HDG104 has an onboard pull-up resistor, 100k, to select SDIO-mode.
Connect a resistor,1k, to GND to select UART mode
5.10 RF interface
The RF output pin impedance is 50 ohm and shall be connected to an antenna with VSWR much
better than 2:1.
RF_CTRL_ANT_0 and RF_CTRL_ANT1 pins are GPIO pins suitable for controlling an external
antenna switch. These pins are powered by the VCC-supply. Function is defined by FW. It may be
used in a Bluetooth coexistence application with one antenna. FW can then connect the WLAN or
the BT to the antenna at appropriate times.
Rev. A. 11/2009
page 24 ( 35)
Data Sheet
HDG104
Application Information
5.11.1
Time Division Multiplexing, TDM, is a way to control the coexistence between 802.11b/g WLAN and
Bluetooth. Enhanced 3-wire is a scheme used to get the best possible performance on both the WLAN and
BT side. This system is used by CSR Bluetooth IC BSC06.
5.11.2
ST PTA (4-wire)
Packet Traffic Arbitration, PTA, is used with ST Microelectronics Bluetooth IC STLC 2500D on the EMP
Mobile Phone platform.
HDG104 pin
I/O
Signal
CSR
BC06
ST
LC2500
Comment
COEXO
WLAN_ACTIVE
PIO9
GPIO_0
COEX1
BT_RF_ACTIVE
PIO7
GPIO_11
COEX2
BT_STATE
PIO5
GPIO_8
COEX3
BT_FREQ
N/A
GPIO_16
SCO-link indicator
COEX4
Not used
Design directions
The design using the HDG104 must be performed according to good RF design considerations. All
the leads shall be as short as possible between the circuit pins and the external components.
Highest priority has the RF-port to antenna strip line, the 40MHz x-tal connections and the VBAT_P
decoupling capacitor.
5.12.2
Soldering
The HDG104 uses a QFN package. The recommended solder profile is pictured in Figure 5.6
HDG104
Pin I/O Signal
Rev. A. 11/2009
page 25 ( 35)
Data Sheet
HDG104
CSR
Type
Rising Zone
PSR
125C-Peak
No
PRS +
Cooldown
125C-Peak
No
TENT +
cooldown
5.12.3
125-217C
< 1C/s
Preheat
Zone
150180C
60-120 s
150180C
60-120 s
125217C
150-210 s
Reflow
Zone
Peak
Zone
Cooldown
Zone
>220C
30-60 s
240255C
>220C
30-60 s
240255C
Peak-125C
No
Peak-125C
< 1C/s
>217C
60-90 s
240255C
Comment
O2< 500ppm
Peak-125C
< 1C/s
Environmental statement
The HDG104 is designed and manufactured to comply with the RoHS and Green directives.
Rev. A. 11/2009
page 26 ( 35)
Data Sheet
HDG104
Application Information
Rev. A. 11/2009
page 27 ( 35)
Data Sheet
5.13.1
HDG104
Package specifications
Rev. A. 11/2009
page 28 ( 35)
Data Sheet
HDG104
6 PACKAGE SPECIFICATIONS
6.1 Mechanical outline QFN 44pin
Figure 6.1: Mechanical drawing, 44 pin Quad Flat No-Lead (QFN) package.
Package specifications
A
C
HDG104
YYMMDD
ZZ
Ref
Marking
Description
H&D Wireless
Company Logo
HDG104
Product name
YYMMDD
ZZ
Production lot
Arrow
Package specification
Rev. A. 11/2009
page 29 ( 35)
Data Sheet
HDG104
Package specifications
Rev. A. 11/2009
page 30 ( 35)
Data Sheet
HDG104
.
Figure 6.4: Recommended land pattern on the PCB, top view
Standards compliance
Rev. A. 11/2009
page 31 ( 35)
Data Sheet
HDG104
7 STANDARDS COMPLIANCE
7.1 IEEE/IETF
Standard
Revision
Description
802.11
802.11 R2003
802.11b
802.11 R2003
802.11d
802.11 R2003
802.11e
QoS enhancements
802.11g
-2003
802.11i
-2004
Security enhancements
802.11k
802.11r
802.11h
1997 edition
Bridge tunneling
RFC1023
Inherent
Frame encapsulation
802.15.2
Bluetooth coexistence
7.2 WiFi
Specification
Description
Revision
2.1
2.0
Ver 1.1
7.3 Regulatory
Country
Approval
authority
Regulatory
Frequency band
USA
FCC
FCC ID X02HDG104
Canada IC
RSS
EU
ETSI*
National
Rev. A. 11/2009
page 32 ( 35)
Data Sheet
HDG104
The HGD104 module has been certified for use in European union countries according to ETSI EN
300 328 (Electromagnetic compatibility and Radio spectrum matters for equipment operating in the
2,4 GHz ISM band using spread spectrum modulation techniques). This standard is harmonized
within the European Union and covering essential requirements under article 3.2 of the R&TTEdirective.
If the HGD104 module are incorporated into a product, the manufacturer must ensure compliance
of the final end-user product to the European harmonized EMC and low voltage/safety standards.
A declaration of conformity must be issued for the product including compliance references to
these standards. Underlying the declaration of conformity a technical construction file (TCF),
including all relevant test reports and technical documentation, must be issued and kept on file as
described in Annex II of the R&TTE-directive.
Furthermore, the manufacturer must maintain a copy of the HGD104 module documentation and
ensure the final product does not exceed the specified power ratings, antenna specifications,
and/or installation requirements as specified in the user manual. If any of these specifications are
exceeded in the final product, a complete re-test must be made in order to comply with all relevant
standards as basis for CE-marking. A submission to notified body must be used only if deviations
from standards have been found or if non-harmonized standards have been used.
Rev. A. 11/2009
page 33 ( 35)
Data Sheet
HDG104
8 SALES OFFICES
Global Sales Office Sweden
H&D Wireless AB
H&D Wireless AB
Sjvgen 17
169 55 Solna, Sweden
H&D Wireless will be adding distributors and sales representatives throughout Q4 in USA, EU and
Asia 2009.
Rev. A. 11/2009
page 34 ( 35)
Data Sheet
HDG104
9 Reference designs
Rev. A. 11/2009
page 35 ( 35)