THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

ECNG 3016
ADVANCED DIGITAL ELECTRONICS
http://myelearning.sta.uwi.edu/course/view.php?id=686
Semester II 2009
1.

GENERAL INFORMATION
Lab #:
Name of the Lab:

1 Part D
Introduction to StateCAD

Lab Weighting:

0%

Delivery mode:

Lecture

Online
 Lab

Other

Venue for the Lab:

Microprocessor Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 3016

Theoretical content link: given at top of page
Pre-Requisites ECNG 2004
To undertake this lab, students should be able to:
1. Use of Xilinx ISE and Modelsim in the implementation of digital
system
2. VHDL programming

Recommended
prior knowledge
and skills3:

Course Staff
Lucien Ngalamou
Marcus George

Position/Role
Lecturer
Instructor

Estimated total
study hours1:

E-mail

lucien.ngalamou@sta.uwi.tt
marcus.george@sta.uwi.tt

Phone


Office

Office
Hours

room 202
room 203

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

2.

LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Understand the basics of StateCAD
2. Use StateCAD to create the state diagram of state machine.
3. Use the state diagram created to generate the corresponding VHDL code for
the state machine.

Cognitive
Level
C
C, Ap
C, Ap

3. PRE-LAB
Due Date:
Submission
Procedure:
Estimated time to
completion:
3.1. Required Reading Resources
3.2. Recommended Reading Resources
3.3. Other Resources
3.4. Pre-Lab Exercise

Lab 1d: Introduction to StateCAD

4.

IN-LAB

Allotted Completion 3 hours

Time:
1 Computer
Required lab
1 Spartan 3 Toolkit
Equipment:
4.1. In-Lab Procedure

4.1.1 Creating the State Diagram

In the Xilinx environment, select Project => New Source and select State Diagram. Give the file a
name and click Next and then Finish.

After StateCAD starts select File => Design Wizard or click on the Draw State Machine button

Click Yes!

Click on Next

Lab 1d: Introduction to StateCAD

Select each of the four Shapes of state machines given(column, multi-coulumn,row and
geometric). Do you observe any changes in the state diagram?

Now vary the Number of states. Do you observe any changes in the state diagram?

Let us now select the shape of the state machine as Geometric and the number of states as 4.
Click on Next

Lab 1d: Introduction to StateCAD

Select Asynchronous reset then Next

Click Next
The Optimization Wizard will open at this point. Click Cancel we will do optimization later.

Lab 1d: Introduction to StateCAD

4.1.2 Adding the State Transitions

Now we need to add the transitions from state to state. Click on the transition from State0 to State1
and add EN=1 as shown:

Click OK

Lab 1d: Introduction to StateCAD

Lab 1d: Introduction to StateCAD

Repeat for the other transitions:

Lab 1d: Introduction to StateCAD

4.1.3 Adding the Output Conditions

Now we need to set the output conditions: Double-click on State0 and add C <= 0; as shown

Click OK and repeat for the other states

Lab 1d: Introduction to StateCAD

4.1.4 Optimization
You can go straight to Generate HDL (Options => Compile), but first click on the Optimize button.

Click Next

Select FPGA and then click Next

Select Manual and then click Next

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Lab 1d: Introduction to StateCAD

Select Guarantee coverage(implied else) then click Next

Click Next

Highlight VHDL and then click Next

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Lab 1d: Introduction to StateCAD

Highlight Xilinx XST and then click on Next to end the Optimize wizard.

4.1.5 Generation of HDL

Click on the Generate HDL button:

Click on Close and the HDL code generated is shown:

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Lab 1d: Introduction to StateCAD

4.1.6 Simulation of Generated HDL

Click on the State Bench button

Then click on Automatic Test Bench

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Lab 1d: Introduction to StateCAD

Click Begin
You obtain the following:

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Lab 1d: Introduction to StateCAD

4.1.2.7 Adding the Generated HDL to the project

In the Xilinx environment, select Project => Add Source and select .vhd file consisting of the
generated HDL.

Select VHDL Design File and click OK. The .vhd file should appear in the source window.

Proceed to post-lab exercise.

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Lab 1d: Introduction to StateCAD

5.

POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date:
Submission
Procedure:
Deliverables:

N/A
N/A
N/A

5.1. Assignment:
Students are required to complete the following exercise below:

5.1.1 Design Specification

A digital system A utilizes FPGA technology for the purpose of digital control. The system is
controlled by an FSM Controller Unit with the block diagram as shown in figure 1 below. When the
system is reset, the FSM controller unit goes into state reset_state where the output transmit_req
is initialized to zero. The controller then goes into state idle where transmit_req remains
unchanged. However when a neighboring system wishes to obtain data from the digital system A it
asserts the port receive_req to HIGH. The controller then goes into the state receive_data in order
to receive the information from the neighboring system on what data is required. The controller unit
then goes into state transmit_data where it asserts the port transmit_req to HIGH in order to
transmit the required data to the neighboring system on the next clock cycle. The system then goes
back into the state idle where it again awaits stimuli from the neighboring system.

Figure 1: Datapath block diagram of the FSM Controller Unit for the system

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Lab 1d: Introduction to StateCAD

The system operation is best described by the incomplete state diagram of figure 2 below.

receive_req = 1

reset state

receive data

idle

anything else

transmit data

Figure 2: Incomplete State Diagram for the FSM Controller Unit

This laboratory exercise consist of the design, implementation and testing an FSM Controller Unit
(Moore Type) for the digital system.

5.1.2 Design of the Finite State Machine

Design the FSM Controller Unit by completing the following steps:


The complete state table for the FSM Controller Unit

5.1.3 Implementation of the Finite State Machine

a. Implement the FSM Controller Unit using StateCAD
b. Optimize and Generate HDL as done in the lab. Using StateCAD, find the following:
i. The number of lines of VHDL code generated
ii. K-Bytes Memory used
iii. Transitions

5.1.4 Testing of the Finite State Machine

Test the FSM controller unit by simulation using the following:
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Lab 1d: Introduction to StateCAD

1. State Bench from StateCAD

2. Modelsim 6.0XE/SE. The following test must be conducted:
a. Functional simulation (Simulate Behavioural Model)
b. Timing Simulation (Simulate Post-Translate VHDL Model)

End of Lab 1d: Introduction to StateCAD

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Lab 1d: Introduction to StateCAD

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