Final Document

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE
EFFICIENCY AND REDUCE COST OF MULTILEVEL INVERTER FOR SOLAR POWER

HARVESTING
CHAPTER 1
INTRODUCTION
1.1 INTRODUCTION
Energy is the key input to drive and improve the life cycle. Primarily, it is the gift of the nature to
the mankind in various forms. The consumption of the energy is directly proportional to the
progress of mankind. With ever growing population, improvement in the living standard of
humanity, industrialization of the developing countries, the global demand for energy is expected
to increase rather significantly in the near future. Fossil fuels supply most of energy consumed
today. However the reserves of fossil fuels are limited. Hence the need was felt to explore and
develop renewable energy sources to meet with ever growing demand of energy.
Most renewable forms of energy are: solar, wind, tidal, geothermal, biomass, biogas. In this
project solar energy is used to produce electric energy to meet the present increasing demands of
the mankind.
1.2 SOLAR ENERGY CONVERSION

Solar power is the conversion of sunlight into electricity, either directly using photo
voltaic (PV), or indirectly using concentrated solar power (CSP). CSP systems use lenses or
mirrors and tracking systems to focus a large area of sunlight into a small beam. PV converts
light into dc electric current using the photoelectric effect. The output of pv panel is regulated by
charge controller and sent to the battery, where the dc energy is stored. This dc power is
converted to ac power by using inverter circuit to supply the power to consumer loads.
Dept. of MECH, JNTUCEA.
Page 1

HARVESTING
1.3 BLOCK DIAGRAM AND ITS DESCRIPTION
Charg
e
Contr
oller
Batter
y
Invert
er
Loa
d
Figure: 1.1 BLOCK DIAGRAM
1.3.1 PHOTO VOLTAIC SYSTEM

Photovoltaics (PV) is a method of generating electrical power by converting sunlight into direct
current electricity using semiconducting
materials that
exhibit
the photovoltaic
effect.
A photovoltaic system employs solar panels composed of a number of solar cells to supply
usable solar power. Power generation from solar PV has long been seen as a clean sustainable
energy
technology
which
draws
upon
the
planets
most
plentiful
and
widely
distributed renewable energy source the sun. The direct conversion of sunlight to electricity
occurs without any moving parts or environmental emissions during operation. It is well proven,
as photovoltaic systems have now been used for fifty years in specialized applications, and gridconnected PV systems have been in use for over twenty years.
Page 2

HARVESTING
Driven by advances in technology and increases in manufacturing scale and sophistication, the
cost of photovoltaics has declined steadily since the first solar cells were manufactured, [2][3] and
the levelised cost of electricity (LCOE) from PV is competitive with conventional electricity
sources in an expanding list of geographic regions. Net metering and financial incentives, such as
preferential feed-in tariffs for solar-generated electricity; have supported solar PV installations in
many countries.[5] Solar PV is now, after hydro and wind power, the third most important
renewable energy source in terms of globally installed capacity. More than 100 countries use
solar PV. Installations may be ground-mounted (and sometimes integrated with farming and
grazing) or built into the roof or walls of a building (either building-integrated photovoltaics or
simply rooftop).
In 2013, the fast-growing capacity of worldwide installed solar PV increased by 38 percent to
139 gigawatts (GW). This is sufficient to generate at least 160 terawatt hours (TWh) or about
0.85 percent of the electricity demand on the planet
FIGURE: 1.2 SOLAR CELL
1.3.1.1Solar cell
Solar cells generate electricity directly from sunlight photovoltaics are best known as a method
for generating electric power by using solar cells to convert energy from the sun into a flow of
electrons. The photovoltaic effect refers to photons of light exciting electrons into a higher state
of energy, allowing them to act as charge carriers for an electric current. The photovoltaic effect
was first observed by Alexandre-Edmond Becquerel in 1839. The term photovoltaic denotes the
Page 3

HARVESTING
unbiased operating mode of a photodiode in which current through the device is entirely due to
the transduced light energy. Virtually all photovoltaic devices are some type of photodiode.
Solar cells produce direct current electricity from sun light which can be used to power
equipment or to recharge a battery. The first practical application of photovoltaics was to power
orbiting satellites and other spacecraft, but today the majority of photovoltaic modules are used
for grid connected power generation. In this case an inverter is required to convert the DC to AC.
There is a smaller market for off-grid power for remote dwellings, boats, recreational vehicles,
electric
cars,
roadside
emergency
telephones, remote
sensing,
and
cathodic
protection of pipelines.
Cells require protection from the environment and are usually packaged tightly behind a glass
sheet. When more power is required than a single cell can deliver, cells are electrically connected
together to form photovoltaic modules, or solar panels. A single module is enough to power an
emergency telephone, but for a house or a power plant the modules must be arranged in multiples
as arrays.
Photovoltaic power capacity is measured as maximum power output under standardized test
conditions (STC) in "Wp" (Watts peak). The actual power output at a particular point in time
may be less than or greater than this standardized, or "rated," value, depending on geographical
location, time of day, weather conditions, and other factors. [18] Solar photovoltaic array capacity
factors are typically under 25%, which is lower than many other industrial sources of electricity.
Several companies have begun embedding power optimizers into PV modules called "smart
modules". These modules perform maximum power point tracking (MPPT) for each module
individually, measure performance data for monitoring, and provide additional safety. Such
modules can also compensate for shading effects, wherein a shadow falling across a section of a
module causes the electrical output of one or more strings of cells in the module to fall to zero,
but not having the output of the entire module fall to zero.
1.3.2 CHARGE CONTROLLER

Page 4

HARVESTING
A charge controller may be used to power DC equipment with solar panels. The charge controller
provides a regulated DC output and stores excess energy in a battery as well as monitoring the
battery voltage to prevent under/over charging. More expensive units will also perform
maximum power point tracking. An inverter can be connected to the output of a charge controller
to drive AC loads.
Figure: 1.3 A typical solar charge controller kit
1.3.3 SOLAR INVERTER

A solar inverter, or PV inverter, converts the variable direct current (DC) output of
a photovoltaic (PV) solar panel into utility alternating current (AC) that can be fed into a
commercial electrical grid or used by a local, off-grid electrical network. It is a critical
component in a photovoltaic system, allowing the use of ordinary AC-powered equipment. Solar
inverters have special functions adapted for use with photovoltaic arrays, including maximum
power point tracking and anti-islanding protection.
Page 5

HARVESTING
Figure 1.4 Internal view of a solar inverter..
Solar inverters may be classified into three broad types
Stand-alone inverters, used in isolated systems where the inverter draws its DC energy
from batteries charged by photovoltaic arrays. Many stand-alone inverters also incorporate
integral battery chargers to replenish the battery from an AC source, when available.
Normally these do not interface in any way with the utility grid, and as such, are not required
to have anti-islanding protection.
Grid-tie inverters, which match phase with a utility-supplied sine wave. Grid-tie
inverters are designed to shut down automatically upon loss of utility supply, for safety
reasons. They do not provide backup power during utility outages.
Battery backup inverters are special inverters which are designed to draw energy from
a battery, manage the battery charge via an onboard charger, and export excess energy to the
Page 6

HARVESTING
utility grid. These inverters are capable of supplying AC energy to selected loads during a
utility outage, and are required to have anti-islanding protection.
1.3.3.1 INVERTER FAILURE
Solar inverters may fail due to transients from the grid or the PV panel, component aging and
operation beyond the designed limits. Following are some common reasons specific components
of inverters age quickly or fail:
Capacitor failure
Electrolytic materials age faster than polycarbonate and other dry dielectric materials
Voltage stress
Continuous operation under maximum voltage conditions
Frequent short-term voltage transients
Current stress
High current increases the internal temperature
Thermal stress on component terminals
Improper Charge and discharge rates
Not operating in ambient temperatures
Mechanical stress
Vibrations
Page 7

HARVESTING
Inverter bridge failure
Usage beyond its rated operating limit
Over current and overvoltage
Other malfunctioning components
Thermal shock
Thermal overload
Extremely cold operating temperature
Electro-mechanical wear
Component stress
Contamination at contacts
Extreme temperature conditions
Ultrasonic vibration originating in (magnetic cores of) inductive components.
Page 8

HARVESTING
CHAPTER II
MULTILEVEL INVERTERS
2.1 CLASSIFICATION OF MULTILEVEL INVERTERS:
Several combinational designs have also emerged some involving cascading the
fundamental topologies. These designs can create higher power quality for a given number of
semiconductor devices than the fundamental topologies alone due to a multiplying effect of the
number of levels. The most actively developed of multilevel topologies are listed below.
Page 9

HARVESTING
Fig: 2.1 Multilevel Converter Topologies

All three multilevel inverters can be used in reactive power compensation without having
the voltage unbalance problem. Table below compares the power component requirements per
phase leg among the three multilevel voltage source inverter mentioned below. It shows that the
number of main switches and main diodes, needed by the inverters to achieve the same number
of voltage levels. Clamping diodes were not needed in flying-capacitor and cascaded-inverter
configuration, while balancing capacitors were not needed in diode clamp and cascaded inverter
configuration. Implicitly, the multilevel converter using cascaded-inverters requires the least
number of components.
Page 10

HARVESTING
Table 2.1 Comparison of Power Component Requirements per Phase Leg among Three
Multilevel Inverters
In General, the multilevel inverters are classified as Single DC source and Multiple DC
sources or Several Separate DC Sources (SDCS).Both the Diode Clamped Multilevel Inverter
and the Flying Capacitor inverter comes under the category of Single DC source where the input
supply is taken from a single DC source.
2.2 MODULATION TOPLOGIES OF MULTI LEVEL INVERTERS:
The multilevel topology involves several modulation techniques. Each technique involves
different modulation methods. The well-known modulation topologies for multi level inverters as
follows:
Sinusoidal or Sub harmonic Natural Pulse Width Modulation (SPWM).
Selective Harmonic Eliminated Pulse Width Modulation (SHE PWM) or ProgrammedWaveform Pulse Width Modulation (PWPWM).
Optimized Harmonic Stepped-Waveform Technique (OHSW).
The advent of the transformer less multilevel inverter topology has brought forth various pulse
width modulation (PWM) schemes as a means to control the switching of the active devices in
each of the multiple voltage levels in the inverter. The most efficient method of controlling the
output voltage is to incorporate pulse width modulation control (PWM control) within the
inverters. In this method, a fixed d.c. input voltage is supplied to the inverter and a controlled
A.C. output voltage is obtained by adjusting the on andoff periods of the inverter devices.
Voltage-type PWM inverters have been applied widely to such fields as power supplies and
motor drivers. This is because: (1) such inverters are well adapted to high-speed self turn-off
switching devices that, as solid-state power converters, are provided with recently developed
advanced circuits; and (2) they are operated stably and can be controlled well.
Page 11

HARVESTING
Fig: 2.2 Multilevel Modulation Techniques

From the above all mentioned PWM control methods, the Sinusoidal pulse width
modulation (SPWM) is applied in the proposed inverter since it has various advantages over
other techniques. Sinusoidal PWM inverters provide an easy way to control amplitude, frequency
and harmonics contents of the output voltage. Sinusoidal pulse width modulation (SPWM) is one
of the primitive techniques, which are used to suppress harmonics presented in the quasi-square
wave. In the modulation techniques, there are two important defined parameters: 1) the ratio P =
fc/fm known as frequency ratio, and 2) the ratio Ma = Am/Ac known as modulation index, where
fc is the reference frequency, fm is the carrier frequency, Am is reference signal amplitude and
Ac is carrier signal amplitude. For NPC multilevel inverters, most carrier based modulation
strategies derive from disposition techniques developed by Carrara et al, where for an M level
inverter, M-1 carriers of identical frequency and amplitude are arranged to occupy contiguous
bands between +VDC and -VDC. These carriers can be arranged in:
Alternative Phase Opposition Disposition (APOD), where each carrier is phase shifted
by 1800 from its adjacent carriers.
Phase Opposition Disposition (POD) where the carriers above the reference zero point is
out of phase with those below the zero point by 1800.
Phase Disposition (PD) where all carriers are in phase.
Page 12

HARVESTING
For Cascaded Inverters, the common modulation strategy is to use continuous three levels PWM
within each individual inverter, with phase shifted carriers between the cascaded inverters of
each phase leg to achieve optimum harmonic cancellation within the phase leg. Recent work has
shown that this modulation strategy achieves the same harmonic performance as the APOD
technique for NPC inverters when the switching frequencies are normalized so as to achieve the
same overall number of switching transitions per fundamental cycle. From this understanding, an
improved modulation strategy for Cascaded inverters has been developed using a discontinuous
three level PWM strategy with 1800 phase shifted carriers within each full bridge inverter, which
achieves the same harmonic performance on a line- to-line basis as does PD modulation for a
NPC inverter. Since the Hybrid inverter topology is derived from the Cascaded structure it is
reasonable to expect that a similar situation exists for the Hybrid inverter.
2.3 INVERTER TOPOLOGIES:
2.3.1 Diode-Clamped Inverter
In this circuit, the dc-bus voltage is split into three levels by two series-connected bulk
capacitors, C1 and C2 the middle point of the two capacitors n can be defined as the neutral
point. The output voltage Van has three states:Vdc/2, 0, and
-Vdc/2 For voltage level
Vdc/2,switches S1 and S2need to be turned on; for -Vdc/2, switches S1 and S2 need to be
turned on; and for the 0 level, S2 and S1 need to be turned on.
The key components that distinguish this circuit from a conventional two-level inverter
are D1 and D1. These two diodes clamp the switch voltage to half the level of the dc-bus
voltage. When both S1 and S2 turn on, the voltage across a and 0 is Vdc, i.e., Vao=Vdc . In this
case, D1 balances out the voltage sharing between S1 and S2 blocking the voltage across C1
and S2 blocking the voltage across C2 . Notice that output voltage is ac, and is dc. The
difference between Van and Vdo is the voltage across C2, which is Vdc/2. If the output is
removed out between a and 0, then the circuit becomes a dc/dc converter, which has three output
voltage levels: Vdc, Vdc/2 and 0. a five-level diode-clamped converter in which the dc bus
consists of four capacitors, C1,C2,C3, and C4 . For dc-bus voltage Vdc, the voltage across each
Page 13

HARVESTING
capacitor is Vdc/4, and each device voltage stress will be limited to one capacitor voltage level
Vdc/4 through clamping diodes. To explain how the staircase voltage is synthesized, the neutral
point n is considered as the output phase voltage reference point. There are five switch
combinations to synthesize five level voltages across a and n. Assuming that each blocking diode
voltage rating is the same as the active device voltage rating, the number of diodes required for
each phase will be (m-1)*(m-2). This number represents a quadratic increase in m. When m is
sufficiently high, the number of diodes required will make the system impractical to implement.
If the inverter runs under PWM, the diode reverse recovery of these clamping diodes becomes
the major design challenge in high-voltage high-power applications.
Page 14

HARVESTING
Fig: 2.3 Diode-clamped multilevel inverter circuit topologies. (a) Three-level. (b) Five-level.
Page 15

HARVESTING
Output VAO
Switch state
Sa1 Sa2 Sa3
Sa4
Sa1
Sa2
Sa3
Sa4
V5=Vdc
V4=3Vdc /4
V3=Vdc/2
V2=Vdc/4
V1=0.
Table 2.2 Diode-clamped five-level inverter voltage levels and their switch states
Features
High-Voltage Rating Required for Blocking Diodes. Although each active switching
device is only required to block a voltage level of Vdc/(m - l), the clamping diodes
Advantages:
All of the phases share a common dc bus, which minimizes the capacitance
requirements of the converter. For this reason, a back-to-back topology is not only
possible but also practical for uses such as a high-voltage back-to-back interconnection or an adjustable speed drive.
The capacitors can be pre-charged as a group.
Efficiency is high for fundamental frequency switching.
Disadvantages:
Real power flow is difficult for a single inverter because the intermediate dc levels will
tend to overcharge or discharge without precise monitoring and control.
The number of clamping diodes required is quadratically related to the number of
levels, which can be cumbersome for units with a high number of levels.
2.3.2 Capacitor-Clamped Inverter:
Page 16

HARVESTING
The circuit below of Capacitor-Clamped Inverter has been called the flying capacitor
inverter with independent capacitors clamping the device voltage to one capacitor voltage level.
The proposed inverter provides a three-level output across a and n, i.e.,Van=Vdc/2,0, or Vdc/2.
For voltage level Vdc/2 ,switches S1 and S2 need to be turned on; for Vdc/2 switches S1and
S2 need to be turned on, and for the 0 level, either pair (S1,S1) or (S2,S2 ) needs to be turned
on. Clamping capacitor C1 charged when S1,S1 are turned on, and is discharged when S2,S2
are turned on. The charge of C1 can be balanced by proper selection of the 0-level switch
combination.
The voltage synthesis in a five-level capacitor-clamped converter has more flexibility
than a diode-clamped converter. The voltage of the five-level phase-leg a output with respect to
the neutral point n, can be synthesized by the following switch combinations.
In the preceding description, the capacitors with positive signs are in discharging mode,
while those with negative sign are in charging mode. By proper selection of capacitor
combinations, it is possible to balance the capacitor charge. Similar to diode clamping, the
capacitor clamping requires a large number of bulk capacitors to clamp the voltage. Provided that
the voltage rating of each capacitor used is the same as that of the main power switch, an m
-level converter will require a total of (m-1)*(m-2)/2 clamping capacitors per phase leg in
addition to (m-1)main dc-bus capacitors.
Page 17

HARVESTING
Fig: 2.4 Capacitor-clamped multilevel inverter circuit topologies. (a) Three-level. (b) Fivelevel .
Switch state
Sa1
Sa2
Sa3
Sa4
Sa1
Sa2
Sa3
Sa4
V5=Vdc
V4=3Vdc /4
V3=Vdc/2
V2=Vdc/4
V1=0.
Output VAO
Table 2.3 Switching States of Five level Capacitor MLI
Page 18

HARVESTING
Advantages:
Phase redundancies are available for balancing the voltage levels of the capacitors.
Real and reactive power flow can be controlled.
The large number of capacitors enables the inverter to ride through short duration outages
and deep voltage sags.
Disadvantages:
Control is complicated to track the voltage levels for all of the capacitors. Also,
recharging all of the capacitors to the same voltage level and startup are complex.
Switching utilization and efficiency are poor for real power transmission.
The large numbers of capacitors are both more expensive and bulky than clamping diodes
in multilevel diode-clamped converters. Packaging is also more difficult in inverters with
a high number of levels.
2.3.3 Cascaded Multi level Inverters:
A different converter topology is introduced here, which is based on the series connection
of single-phase inverters with separate dc sources . The power circuit for one phase leg of a ninelevel inverter with four cells in each phase. The resulting phase voltage is synthesized by the
addition of the voltages generated by the different cells. Each single-phase full-bridge inverter
generates three voltages at the output:+Vdc,0 and Vdc. This is made possible by connecting the
capacitors sequentially to the ac side via the four power switches. The resulting output ac voltage
swings from -4Vdc to +4Vdc with nine levels, and the stair case waveform is nearly sinusoidal,
even without filtering.
Another version of cascaded multilevel inverters using standard three-phase two-level
inverters has recently been proposed . It uses an output transformer to add the different voltages.
In order for the inverter output voltages to be added up, the inverter outputs of the three modules
need to be synchronized with a separation of 120 between each phase. For example, obtaining a
three-level voltage between outputs a and b, the voltage is synthesized by Vab=Va1-b1+Vb1Dept. of MECH, JNTUCEA.
Page 19

HARVESTING
a2+Va2-b2. The phase between b1and a2 is provided by and through an isolated transformer.
With three inverters synchronized, the voltages Va1-b1,Vb1-a2,Va2-b2 are all in phase; thus, the
output level is simply tripled.
Fig: 2.5 Cascaded inverter circuit topology and its associated waveform
2.4 Symmetrical Cascaded H-Bridge multilevel Inverter
Page 20

HARVESTING
If all the input sources are of equal magnitude, it is known as Symmetrical H-Bridge
inverter and the switching sequence. Here both the full bridge inverters are fed with different
sources of equal magnitude.
Fig: 2.6 Symmetrical five level Cascaded H-Bridge inverter

In the above fig, each SDCS of equal magnitude is associated with a single-phase fullbridge inverter. The ac terminal voltages of different level inverters are connected in series. By
different combinations of the four switches, S1-S4, each inverter level can generate three
different voltage outputs, +Vdc, -Vdc, and zero. The ac output of each of the different level of
full-bridge inverters are connected in series such that the synthesized voltage waveform is the
sum of the inverter outputs. In this topology, the number of output phase voltage levels is defined
by m = 2s+1, where s is the number of dc sources.
A 5-level cascaded-inverters will have two SDCSs and two full-bridge cells. The
switching table for the five level cascaded inverter is shown below. Here, 2 Full Bridges are used
and are cascaded to each other. The Switches S1, S2, S3,and S4 are from upper H-Bridge and
Switches S5 S6 S7 and S8 are from lower H-Bridge .By giving correct switching patter n ,we get
5 voltage levels i.e 2Vdc,Vdc,0,-2Vdc,- Vdc, S1,S2,S5,D7 are on .To get 2Vdc, S1,S2,S6,S5 are
kept on .The switching table is shown below to get 5 levels with a Symmetrical DC source.
Page 21

HARVESTING
Switches ON
Voltage level
S1, S2, S5 and D7

S1, S2, S6and S5
S1, S2, S6 and D8
S1, D3, S6 and D8
S3, S4, S6 and D8
S3, S4, S7 and S8
S3, S4, D6 and S8
S1, S3, D6 and S8
Vdc/2
Vdc
Vdc/2
0
-Vdc/2
-Vdc
-Vdc/2
0
Table 2.4 Switching states of Symmetrical five level cascaded H-Bridge inverter
Vdc
Vdc/2
0
-Vdc/2
-Vdc
Fig: 2.7 Output waveform of Symmetrical Cascaded H-Bridge multilevel Inverter

2.5 Asymmetrical Cascaded H-Bridge multilevel Inverter:
The cascaded H-Bridge multilevel inverter with two SDCS with unequal magnitude is
known as Asymmetrical Cascaded H-Bridge multilevel Inverter. The following is figure of
Asymmetrical Cascaded H-Bridge multilevel Inverter where it is having 2 unequal DC sources
+2Vdc/3 and +Vdc/3.
Page 22

HARVESTING
Fig 2.8 Asymmetrical Cascaded H-Bridge multilevel Inverter

By using this type of Asymmetrical configuration, for a n bridge inverter we can get
3n+1 voltage levels and n Capacitors of each rating nVdc/(n+1), Vdc/(n+1) to get Vdc max and
6n switches of
each voltage rating is Vdc/(n+1).The following is the switching table of
Asymmetrical Cascaded H-Bridge multilevel Inverter.

Switches ON
S4, S2, S5 and S6
S1, S2, S8 and S6
S1, S2, S5and S6
S4, S2, S7 and S8
S3, S4, S6 and S8
S3, S4, S7 and S8
S4, S2, S8 and S6
Voltage level
Vdc/3
2Vdc/3
Vdc
-Vdc/3
-2Vdc/3
-Vdc
0
Table 2.5 Switching states of Asymmetrical five level cascaded H-Bridge inverter
Page 23

HARVESTING
Fig: 2.9 Single-phase structure of a multilevel cascaded inverter.

Depending on the number of levels, the bridges are cascaded. In this topology, the
number of output phase voltage levels is defined by m = 2s+1, where s is the number of dc
sources. The following is the generalized structure of Cascaded H-Bridge multilevel inverter.
Page 24

HARVESTING
CHAPTER 3
PROPOSED TOPOLOGY
3.1 INTRODUCTION
Fig. 1 shows the proposed topology for a sub multilevel converter, which consists of the basic
unit and a full-bridge converter. The basic unit consists of n dc voltage sources. Each dc voltage
source is connected to the output by two switches and can produce a zero or positive polarity
voltage. As shown in Fig. 1, each switch is composed of an insulated gate bipolar transistor
(IGBT) with an antiparallel diode. Both switches, Si and Si (for i = 1, 2 . . . n), are
complementary controlled on the entire operation cycle. The basic unit produces a voltage
waveform with positive polarity. The output voltage of the basic unit can be equal to each dc
voltage source.
Figure. 3.1. (a) Proposed sub multilevel topology
Page 25

HARVESTING
Page 26

HARVESTING
Figure3.1.b Typical output waveforms of V0
The output side of the basic unit is connected to a single-phase full-bridge converter, which
alternates the input voltage polarity and provides a positive or negative staircase waveform at the
output. The full-bridge switches, T1, T2, T3, and T4, are also complementary controlled. The
typical output waveforms of vo and v0 are shown in Fig.3.1.b. Table I gives the values of voltages
v0 and v0 for different states of the switches S1, S2. Sn, T1, and T2. For simplicity, the on-state
voltage drops of the switches have been neglected. As can be seen, 2 n+1 1 different values can
be obtained for v0. It can be mentioned that there are different switching states to generate the
zero-voltage level at the output voltage.
3.2 GENERALIZED STRUCTURE OF PROPOSED TOPOLOGY

The proposed multilevel converter topology is constituted by a cascade connection of sub
multilevel converters as shown in Fig.3.2. The structure of the first, second . . . and Nth basic
Unit have two switches each (S1, S2), (S3, S4), (Sn, Sn+1) respectively.
Page 27

HARVESTING
Figure: 3.2 generalized structure of proposed topology

Page 28

HARVESTING
The full-bridge converters provide positive or negative stepped voltage waveforms between the
output terminals. The overall output voltage of the proposed cascaded multilevel converter is the
sum of output voltages of the sub multilevel converters as follows:
V= V1+V2++Vn
(1)
The different output voltage levels can be determined by combinations of switching states of
each unit. If proper values for the dc voltage sources are selected, then the output voltage of
n
Vi ) and (+
the converter can be obtained between (-
i=1
Vi
i=1
). If the number of dc voltage
sources in basic units is considered equal to 1, then there is no need for switches in basic units. In
this state, the dc voltage source is directly connected to the full-bridge converter. In other words,
this topology is equivalent to the CHB converter. Although the latter topology requires multiple
dc sources, but these may be suitable for the cases, which have possible combination of
photovoltaic panels, fuel cells, or energy storage devices, such as capacitors or batteries. When
ac voltage is available, multiple dc sources can be generated using isolated transformers and
rectifiers. It is important to mention that this topology requires less dc voltage sources
considering variety and number compared to topologies.
Page 29

HARVESTING
3.3 PROPOSED TOPOLOGY OF CASCADED MULTILEVEL INVERTER
Figure: 3.3 proposed 15 level multilevel inverter
Page 30

HARVESTING
Fig: 3.3 shows the proposed 15 level inverter topology, which is based on a cascaded connection
of three single phase sub multilevel inverter units and H-bridge converter. Compared to the
conventional multilevel inverter, the number of dc voltage sources, switches, installation area
and converter cost is significantly reduced as the number of voltage steps increases to 15 level.
The different output voltage levels can be determined by combinations of switching states of
each unit. As can be seen, 15 different values can be obtained for V 0. Table 3.1 shows the
different voltage levels for different combinations of switching states of each unit.
TABLE:3.1: Values of V0 for different states of the switches

Page 31

HARVESTING
CHAPTER 4
SIMULATION
4.1 SIMULINK MODEL OF MULTI LEVEL INVERTER WITH SOLAR PANEL
Figure: 4.1 simulink model of multilevel inverter with solar panel
Page 32

HARVESTING
4.2 SIMULATION MODEL OF SUBSYSTEM
Figure: 4.2 simulink model of subsystem
Page 33

HARVESTING
4.3 PULSES FOR THE SYSTEM

Fig
ure: 4.3 pulses for the system
Page 34

HARVESTING
4.4 PULSES FOR H-BRIDGE
Page 35

HARVESTING
Figure:
5.4 pulses for the h bridge
4.5 OUTPUT VOLTAGE
Page 36

HARVESTING
Figure: 4.5 output voltage
4.6 OUTPUT CURRENT

Page 37

HARVESTING
Figure: 4.6 output current
Page 38

HARVESTING
4.7 BLOCK FUNCTIONS

4.7.1 SUB SYSTEM
Subsystem is a block which is used to represent the pulse generator. It is used to give triggering
pulses to the switching devices like IGBT. The internal structure of subsystem consists of
repeating sequence block which outputs a periodic scalar signal having a waveform that
specified time values and output value parameters. This will be given with the rounding function
block to give round input pulses to the switches. For the positive pulses this will be directly
given to the switch and for negative pulses it will be given to the switch through NOT gate.
4.7.2 PV Array
PV array block is used to supply the input of solar panel to the proposed topology. As the input
of solar panel is light and heat, here this block is given with radiance and ambient temperature as
input. In series with this a saturation block will be given to impose upper and lower bounds on a
signal within a specified range as the PV array output is not constant.
4.7.3 SINGLE PHASE MULTILEVEL CONVERTER UNIT
Page 39

HARVESTING
Single phase multilevel inverters synthesize a desired stepped output voltage waveform by the
proper arrangement of the power semiconductor devices from several lower DC voltage sources.
The connection is such that for positive half cycle switches t1 and t3 will conduct and for
negative half cycle switches t2 and t4 will conduct.
4.7.4 SWITCH
The IGBT/Diode block is a simplified mode of an IGBT (or GTO or MOSFET)/Diode pair
where the forward voltages of the forced-commutated device and diode are ignored. The internal
resistance Ron of the IGBT device, in ohms ().The snubber resistance, in ohms (). Set the
Snubber resistance Rs parameter to inf to eliminate the snubber from the model.The snubber
capacitance in farads (F). Set the Snubber capacitance Cs parameter to 0 to eliminate the
snubber, or to inf to get a resistive snubber.
Page 40

HARVESTING
CHAPTER 5
CONCLUSION
5.1 CONCLUSION
A new configuration for multilevel converter has been proposed, which is based on the cascaded
connection of sub multilevel converters. The suggested structure extends the design flexibility
and possibilities to optimize it for various objectives. The proposed topology has been optimized
in this paper for utilizing a minimum number of switches and voltage sources. A comparison
among the proposed converter and other topologies has been provided. It is shown that the
proposed topology, not only has lower number of switches and components, compared to other
topologies, but also the full-bridge converters operate at a lower voltage. This extends the
applications of the proposed converter for high voltages. The operation and performance of the
proposed topology has been simulated and experimentally verified on a single-phase 49-level
converter prototype. It is shown that the simulations and measurements had a good agreement
with each other.
Page 41

HARVESTING
REFERENCES
1. k. Corzine and Y. Familiant, A new cascaded multi level H-bridge drive, IEEE Trans.
Power Electron., vol. 17 , no. 1, pp. 125-131, jan. 2002.
2. J. Wang and F. z. Peng, Unified power flow controller using the cascaded multi level
inverter, IEEE Trans. Power Electron, vol. 19, no. 4, pp. 1077-1084, jul.2004.
3. B. P. McGrath and D.G Holmes, Natural capacitor voltage balancing for a flying
capacitor converter induction motor drive, IEEE Trans. Power Electron. , vol. 24, no. 6,
pp. 1554-1561, jun. 2009.
4. Q. Song and W. Liu, Control of a cascaded STATCOM with star configuration under
unbalanced conditions, IEEE Trans. Power Electron, vol. 24, no. 1, pp. 45-58, jan. 2009.
5. M. Hagiwara, K. Nishimura, and H. Agaki, A medium-voltage motor drive with a
modular multilevel PWM inverter, IEEE Trans. Power Electron, vol. 25, no. 7, pp. 17866.
1799, jul. 2010.

J. Rodriguez, J. S. Lai, and f. Z. Peng, multilevel inverters: A survey of topologies,
controls, and applications, IEEE Trans. Ind. Electron. , vol. 49, no. 4, pp. 724-738, Aug.
2002.
7. K. A. Corzine , M. W. Wielebski, F. Z. Peng, and J. Wang, Control of cascaded multi
level inverters, IEEE Trans. Power Electron, vol. 19, no. 3, pp. 732-738, May 2004.
8. E. Babaei, S. H Hosseini, G. B. Gharehpetian, M. Tarafdar Haque, and M. Sabahi,
Reduction of dc voltage sources and switches in assymetrical multilevel converters
using a novel topology, Elsevier J. Electric Power Syst. Res. , vol. 77, no. 8, pp.. 10731085, Jun 2007.
9. S. Mekhilef and M. N. Kadir, voltage control of three-atage hubrid multilevel inverter
using vector transformation, IEEE Trans. Power Electron, vol. 25, no. 10, pp. 25992606, oct. 2010.
10. A. Nabae, I. Takahashi, and H. Agaki, A new neutrsl-point-clamped PWM inverter,
IEEE Trans, Ind. Appl. , vol. IA-17, no. 5, pp. 518-523, sep/oct. 1981.
11. T. A. Meynard and H. Foch, multilevel choppers for high voltage applications, in Proc.
Eur. Conf. Power Electron. Appl. , 1992, v0l. 2, pp. 45-50.
Page 42

HARVESTING
12. F. Z. Peng, J. S. Lai, J. W. McKeever, and J. Van Coevering,A multilevel voltage source
inverter with separate Dc sources for static var generation, IEEE Trans . Ind. Appl. , vol.
32, no. 5, pp. 1130-1138, sep./oct. 1996.
13. B. P. McGrath, T. Meynard, G. Gateau, and D. G. Holmes, optimal modulation of flying
capacitor and stacked multicell converters using a state machine decoder, IEEE Trans.
Power Electron. , vol. 22, no. 2, pp. 508-516, mar. 2007.
14. A. M. Lienhardt, G. Gateau, and D. G. Holmes , Stacked multicell converter(SMC):
Reconstruction of flying capacitor voltages, in Proc. Conf. Ind. Electron. , 2005, pp.
691-696.
15. S. S. Fazel , S. Bernet, D. Krug, and K.Jalili, Design and comparision of 4-kv neutralpoint-clamped, flying capacitor voltages, and series connected H-bridge multi level
converters, IEEE Trans. Ind. Appl. , vol.43, no. 4, pp. 1032-1040, Jul/Aug. 2007.
Page 43

Final Document

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Final Document

Uploaded by

Copyright:

Available Formats

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

EFFICIENCY AND REDUCE COST OF MULTILEVEL INVERTER FOR SOLAR POWER

1.2 SOLAR ENERGY CONVERSION

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

1.3 BLOCK DIAGRAM AND ITS DESCRIPTION

Figure: 1.1 BLOCK DIAGRAM

1.3.1 PHOTO VOLTAIC SYSTEM

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

FIGURE: 1.2 SOLAR CELL

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

1.3.2 CHARGE CONTROLLER

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Figure: 1.3 A typical solar charge controller kit

1.3.3 SOLAR INVERTER

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Figure 1.4 Internal view of a solar inverter..

Solar inverters may be classified into three broad types

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Continuous operation under maximum voltage conditions

Frequent short-term voltage transients

High current increases the internal temperature

Thermal stress on component terminals

Improper Charge and discharge rates

Not operating in ambient temperatures

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Inverter bridge failure

Usage beyond its rated operating limit

Over current and overvoltage

Other malfunctioning components

Extremely cold operating temperature

Extreme temperature conditions

Ultrasonic vibration originating in (magnetic cores of) inductive components.

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Fig: 2.1 Multilevel Converter Topologies

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Sinusoidal or Sub harmonic Natural Pulse Width Modulation (SPWM).

Optimized Harmonic Stepped-Waveform Technique (OHSW).

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Fig: 2.2 Multilevel Modulation Techniques

Phase Disposition (PD) where all carriers are in phase.

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

-Vdc/2 For voltage level

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Dept. of MECH, JNTUCEA.

REDUCED POWER ELECTRONIC COMPONENTS BY NEW TOPOLOGY TO IMPROVE

Table 2.3 Switching States of Five level Capacitor MLI