Lab 1 Half Adder and Full Adder

Overview
In this lab, student has three exercises to do. The first exercise will introduce
the one bit half adder. Student need to build a structural half adder file.
Student will know the theory of adder. And then use the adder to do some
binary adding. And then the second exercise will introduce the one bit full
adder. Student will know the different of half adder and full adder. Student
need to build a behavioral full adder file. And then use the full adder to do
some binary adding. After that, the third exercise will introduce the four bit
full adder. Student will learn the connection between the adder. At the end
of the lab, student must able to know the concept for half adder and full
adder. Student knows the difference between the structural and behavior
Verilog file.

Objective
The objectives of this lab are:
1. To write the Verilog HDL module for these exercise
2. Student should be able to understand the concept for half adder, full
adder.

3. Student should be able to difference the structural and behavioral Verilog

file.

Part 1: one bit half adder

1. Create a new Quartus II project for the circuit. Select Cyclone IV E, and
choose EP4CE115F29C7 as the target chip, which is the FPGA chip on the
Altera DE2-115 board.
2. Create a structural Verilog module for the 1bit_half_adder (for example)
and include it in the project. In this project, student needs use some slide
switches as input of binary number and LEDs for output of binary answer.
3. Simulate the Verilog HDL.
4. Include in the project the required pin assignments for the DE2 board.
Compile the project.
5. Download the compiled circuit into the FPGA chip.
6. Please show the result when the input is 01, 10, and 11.

Part 2: one bit full adder

1. Create a new Quartus II project for the circuit. Select Cyclone IV E, and
choose EP4CE115F29C7 as the target chip, which is the FPGA chip on the
Altera DE2-115 board.
2. Create a behavioral Verilog module for the 1bits_full_adder (for example)
and include it in the project. In this project, student use some slide switches
as input of binary number and LEDs for output of binary answer.
3. Simulate the Verilog HDL.
4. Include in the project the required pin assignments for the DE2 board.
Compile the project.
5. Download the compiled circuit into the FPGA chip. Test the functionality of
the circuit.
6. Please show the result when the inputs (A, B, C_in) are 001, 101, and 011.

Part 3: 4 bits full adder

1. Create a new Quartus II project for the circuit. Select Cyclone IV E, and
choose EP4CE115F29C7 as the target chip, which is the FPGA chip on the
Altera DE2-115 board.
2. Create a RTL Verilog module for the 4_bits_fulladder (for example) and
include it in the project. In this project, student use some slide switches as
input of binary number and LEDs for output of binary answer.
3. Simulate the Verilog HDL.
4. Include in the project the required pin assignments for the DE2 board.
Compile the project.
5. Download the compiled circuit into the FPGA chip. Test the functionality of
the circuit.
6. Please show the result when the input is:
C_in

Input

0
1
1

01011101
11101110
01111101

Report
1.

Access

student

own

email

and

submit

project

zip

file

to

hohhangtak88@outlook.com before end of the day.

2. The project zip file includes three project .v file and a report. The
report should at least 3 pages. (Tahoma, front size 12, line spacing 1.5) The
report must include the output of the DE2 board, all related information that
supports the analysis and discussion. The report can be in the form of
.doc / .docx / .pdf.
3. The zip file MUST submit on time. Late submission will decrease the mark
for this single lab automatically.