CHAPTER 6

REGISTER

6.0

Introduction
In our life today, calculator play very important role in every calculation.
Do you know how calculator makes a calculation for us? For example to
mix two numbers as 18 + 11.
Now you press key 1, number 1 will be displayed. When second number,
8 is pressed, then number 1 would be shifted left and number 18 will be
displayed. From example above, we find out logic circuit resides within
calculator will keep first the number and then that number would be
shifted if second number included.
This mean during this calculation, when number 18 is pressed, this
number must be kept first in its memory. When number 11 is pressed,
this number will going to add up with number in its memory.
Digital circuit that will be act as a memory in calculator was shift register.
Shift register was the memory constructed from a few flip-flop. Shift
register usually used as temporary memory before arithmetic operations
have been made.
Similarly inside data transmission system, shift register used as
temporary memory before data sent anywhere. It also functions as
changing the data from parallel to serial or instead follow system
requirement.
Look at the data transmission system below:

MODEM

MODEM

Data processed by computer in serial form. When this data want to be

sent through phone line it would be sent by serial. Vice versa, if data from
phone line sent to computer, then data which entered by series need to
be changed to serial before it will be read by computer. To replace data
from parallel to serial or otherwise, interfacing circuit is needed. For your
information this interfacing circuit is built from registers.
In short, circuit which functions to keep the data and then shifted the data
known as SHIFT REGISTER.
Shift register may be defined as device or a group of flip-flop used to
keep and shift data.

6.1

Shift Register Basic Circuit

Shift register is one tool that can keep and shift data, the suitable flip-flop
to be used was D's flip-flop. As we study previously one D's flip-flop could
keep one bit data either bit 0 or 1 depends on entry given.
If we refer to figure 6.1, we find out that when bit 1 gave to the input, after
clock pulse given then data 1 would be kept, likewise when bit 0 gave to
the input, then data 0 would be kept.

1
clk

1 kept

0 kept

clk

Figure 6.1: D Flip-flops as memory tool

Because one flip-flop could only keep a bit data, then register capacity or
memory tool is equal to flip-flop number used. This mean when we want
build 2-bit shift register then 2 flip-flops needed. This is shown in figure
6.2.

Data input

Q0

Q1

clk

Figure 6.2: 2-bit Shift Register

6.2

Types of Shift Register

Shift register is the key component in most digital system thus it has
classified as input and data output method. There are 4 types of shift
register.
a) serial input - serial output shift register,
b) serial input - parallel output,
c) parallel input - serial output and
d) parallel input - parallel output.
In example below, suppose shift register applies in 8-bit digital system.
And data will be entered here is 10010110.

Serial Input - Serial Output Shift Register (SISO)

First shift

0
SISO's Concept:

1 0 0 1 0 1 1 0
Second shift

1 0 0 1 0 1 1 0
Third shift

Data shifted in and out

one bit each time
through one input and
one output

1 0 0 1 0 1 1 0
Fourth shift

1 0 0 1 0 1 1 0
Fifth shift
1 0 0 1 0 1 1 0
Sixth shift
1 0 0 1 0 1 1 0
Seventh shift
1 0 0 1 0 1 1 0
Eight shift

0 first data out

1 0 0 1 0 1 1 0

After 8 shifts, all data would be kept, and first

data (0) will be out.

Serial Input/ Parallel Output Shift Registers (SIPO)

Input serial
10010110

Output parallel

SIPOs Concept:
Data shift in one bit at a
time, after all bit shift in, it
would be shifted out
simultaneously

Parallel Input/ Serial Output Shift Registers(PISO)

Parallel input
0 1 0 1

PISOS Concept:

Serial output
0

All bit data shift in

simultaneously, and
shifted out a bit at every
time.

Parallel Input/ Parallel Output Shift Registers (PIPO)

Input Parallel
0 1 0 1

PIPOs Concept:

All bit data shift in

and shift out
simultaneously

Output Parallel

6.3

Serial Input-Serial Output Shift Registers

Figure 6.3 below show a serial input / serial output shit registers built
using D flip-flop . This shift register having 4 stages (4 flip-flop) thus it
can keep 4 bits data. If we used serial input / serial output shitf registers
it means we only used one line input and one line output .

Serial input
1000

clk

Q0

Serial output

Q1

Q2

Figure 6.3: serial input / serial output shit registers

Q3

After CLK4, the last bit data (1) would be kept in FF0, original data in FF0 will
shift to FF1, data in FF1 shift to FF2 and data in FF2 shift to FF3. Data would
be kept until power supply stopped.

Example 6.1

clk
Input data

Solutio
n
Circuit diagram:
Draw a 5 bit SISO shift register circuit by using flip-flop D. Also draw the time
diagram and truth table for this register. Assumed Qearly= 0.

SI

QA

QB

QC

QD

QE

SOUT

klok

Time diagram:
clk
All the
output
from QA
until QE is
start from
0.
(Qearly= 0)

Input

1
1

Qearly= 0

QA copy
from input
data

data
QA
QB
QC
QD

QE 0

Input
series
1
1
0
1
0
Truth table:

clock
0
1
2
3
4
5

QA
0
1
1
0
1
0

QB
0
0
1
1
0
1

Output series
QC
0
0
0
1
1
0

QD
0
0
0
0
1
1

QE
0
0
0
0
0
1

Output
SISO

6.4

Serial Input-Parallel Output Shift Registers (SIPO)

Do you still remember SIPO

shift registers concept?

Output
SISO

Qearly= 0.

Now we will look into Figure 6.4 to look how this shift registers operating.

Output data (Q0 Q3)

Q0

Q1

Q3

Q2

Input data

Q0

Q1

clk

Q2

Q3

(a)
Input data

D
C

Clk

Q0 Q1 Q2 Q3
(b)
Figure 6.4: 4 bit Serial input- Parallel output shift registers

(a)
(b)

Logic circuit
Symbol

Example 6.2
Draw output SIPO for time diagram below. Write the truth table. Assumed Q early=
0.

Clk

Input data

Solution:
Time diagram:
Clk

Input data

2
1

3
0

4
1

5
0

0
0

QA

All the
QB
output
from QA
to QE start QC
from 0.

QD

(Qearly= 0)

QA copy
from input
data

QE

Output
SIPO

Input
series

clock
0

QA
0

QB
0

Output series
QC
0

QD
0

QE
0

1
0
1
0
0
Truth table:

6.5

1
2
3
4
5

1
0
1
0
0

0
1
0
1
0

0
0
1
0
1

0
0
0
1
0

0
0
0
0
1

Parallel Input-Parallel /Serial Output Shift Registers

Do you still remember PISO shift registers concept?
Yes! All bit data shift in simultaneously, and
shifted out a bit at every time.

Q0
Clear

Q1

Parallel output
Q2

Q3

1
0

J clr Q0

J clr Q1

J clr Q2

K pr

K pr

K pr

K pr

clk
1

Controller
Parallel
input

P1
P2
P3
P4
Figure 6.5: 4 bit Parallel input- Parallel/Serial output shift
register

Q3

Serial output
(Q3)

Output
SIPO

Circuit operation:
1. By referring to Figure 6.5, input J and K given, J 0=0 and K0=1, this to
ensure circuit operating such as required.
2. Control line would control input for parallel data. When control line = 1,
then parallel data will be shift to the register.
3. If control line = 0, data in register will be shifted out in series at (Q3).
When control line = 0, any change of input parallel data will not change
the register state. Register now is in shift to the right mode (shift out data
by serial mode).
Example 6.3
The register has already data 101102. If the new data 001002 entering the
register, built the truth table and time diagram for this register.
Solution:
Assumed 101102 is data input for parallel (Qearly) and 001002 is new data for
serial. PISO also needs serial input to complete the shift register.
Time diagram:
Clk

2
0

QA

QB

Parallel input

QC

QD

3
0

4
1

5
0

Serial
input

QE

Input
series
0
0
1
0
0
Truth table:

6.6

clock
0
1
2
3
4
5

QA
1
0
0
1
0
0

QB
0
1
0
0
1
0

Output series
QC
1
0
1
0
0
1

Output
PISO

QD
1
1
0
1
0
0

QE
0
1
1
0
1
0

Parallel Input-Parallel Output Shift Registers

Figure 6.6 show a parallel input-parallel output shift register using flipflop D. All data will transfer simultaneously to destination.
Parallel input

Output
PISO

Parallel output
Figure 6.6: Parallel Input-Parallel Output Shift Registers

6.7

Application of Shift Registers

After you understanding the concept and types of shift register, we

move on to application of shift register in arithmetic operation. Shift
register also used in data conversion series to parallel, parallel to series
and shift register counter.
6.7.1 Arithmetic operation
One of shift register application is to operate arithmetic
operation which is multiplier and divider. To operate this function, two
types of shift register will be used which is shift register to the right and
shift register to the left.
The function of shift registers to the right as a divider. The first
step is shift MSB number (most significant bit) to LSB number (least
significant bit) which is shifted from left to the right. Second step is
applying bit 0 to the MSB number.
Example:
Binary
01011000LSB
00101100
00010110

Origin number
First shift
Second shift

Serial input

MSB

Decimal
88
44
22

Serial output
Daftar
anjakan ke kiri pula akan berfungsi sebagai Pendarab-2.
D
Qa
D

Qb

Qc

Qd

clk

Figure 6.7: Shift registers to the right

The function of shift registers to the left as a multiplier. The first step is shift LSB
number (least significant bit) to MSB number (most significant bit). Second step
is applying bit 0 to the LSB number.
Example:
Binary

Decimal

Origin number
First shift
Second shift

MSB

00010110LSB
00101100
01011000

22
44
88

Serial output

Qa

Serial input

Qb

Qc

Qd

clk

Figure 6.8: Shift registers to the left

6.7.2

Shift register counters

One of shift registers application is as a sequencer, which is the
circuit will produce wave state sequentially. The output is not count in
real binary but produce special number sequence. Therefore it can be
used to control program which occurred consecutively in digital system.
This circuit is called counter because it produced special number.
Two shift register counter that commonly used is Ring counter and
Johnson counter.

Ring Counter
1
J PR QA

J PR QB

J PR QC

J PR QD

K clr

K clr

K clr

K clr

clk

+5V
1 k

low

0.001F

Figure 6.9: 4-bit Ring counter using Flip-Flop JK

high

As stated before, the output for Ring Counter is not in real binary
counting sequence but it produce special number sequence. For
example, 4 bit ring counter in figure 6.9, the output will be high in one
hour trigger and low in 3 hour trigger subsequence then returns. This is
shown in figure 6.10.
clock

QA

QB

QC

QD

Figure 6.10 : 4-bit Ring counter time diagram

Johnson counter
1
J PR QA

J PR QB

J PR QC

J PR QD

K clr

K clr

K clr

K clr

clk

+5V
1 k
low

0.001F

Figure 6.11: 4-bit Johnson counter using Flip-Flop JK

high

Jam

1
0

1
1

1
2

1
3

Table 6.2: Sequence Table for Johnson Counter

QA
QB
QC
QD

Jam
0
1
2
3
4
5
6
7
8

QA
QB
QC
QD
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0 Figure 6.120: Johnson counter
0 time diagram
0

Circuit operation
RC circuit will reset four flip-flops to 0 when power supply on.
During first clock, QA was high because JA connected to Q and KA are
joined at QD. QB, QC and QD will follow flip-flop state before.
4 bit Johnson counter produce 8 mode (Table 6.2 and figure 6.12)
and if 8 bit it produced 16 modes, so if n-bit it will produce 2n modulo.
.

SELF-ASSESSMENT
1. State 4 (FOUR) methods for data shifted into the shift register.
2. Draw the symbol and logic circuit for register that shift the data using
PISO and PIPO format.
3. State 2 (TWO) advantages for shifted format parallel data compared to
shifted format serial data.

1
4

1
5

4. Give the differences between register and counter based on output data.
5. i) Sketch a SISO (serial input serial output) register that will be
able to shift in the data 11100110012 by using 5 JK flip-flop.
(Assume the LSB data enter first).
ii) How much time needed to enter the data 3(i) to the register if
clock frequency input are 100kHz
iii) Draw the truth table and time diagram until CLK 10 shows the
process above. Assume that the early data register is 0000 2
6.

If input data 11001 are entering to the register

i) How many clock pulses needed to enter all the data.
ii) With the truth table, show the shifted register happened if
Qearly=0.
iii) Find the series output produced for each clock.
6. Built truth table and time diagram until CLK 6 if input data in parallel
entering PISO register is 1111. Assumed Qearly is 0000 and series output
controlled are activated.