FPGA Questions

7/26/2015
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FPGAInterviewquestions
runningeggs
https://sites.google.com/site/fpgawiki/interviewquestions
1)Whatisminimumandmaximumfrequencyofdcminspartan3
seriesfpga?
Spartanseriesdcmshaveaminimumfrequencyof24MHZandamaximum
of248
2)Tellmesomeofconstraintsyouusedandtheirpurposeduring
yourdesign?
Therearelotofconstraintsandwillvaryfortooltotool,Iamlistingsomeof
Xilinxconstraints
a)TranslateonandTranslateoff:theVerilogcodebetweenTranslateonand
Translateoffisignoredforsynthesis.
b)CLOCK_SIGNAL:isasynthesisconstraint.Inthecasewhereaclocksignal
goesthroughcombinatoriallogicbeforebeingconnectedtotheclockinputof
aflipflop,XSTcannotidentifywhatinputpinorinternalnetistherealclock
signal.Thisconstraintallowsyoutodefinetheclocknet.
c)XOR_COLLAPSE:issynthesisconstraint.Itcontrolswhethercascaded
XORsshouldbecollapsedintoasingleXOR.
Formoreconstraintsdetaileddescriptionrefertoconstraintguide.
3)Supposeforapieceofcodeequivalentgatecountis600andfor
anothercodeequivalentgatecountis50,000willthesizeofbitmap
change?inotherwordswillsizeofbitmapchangeitgatecount
change?
Thesizeofbitmapisirrespectiveofresourceutilization,itisalwaysthe
same,forSpartanxc3s5000itis1.56MBandwillneverchange.
4)WhataredifferenttypesofFPGAprogrammingmodes?whatare
youcurrentlyusing?howtochangefromonetoanother?
2014(19)
(19)
BooleanAlgebra
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SynthesisFAQ
FPGASynthesisveryinformative
document
VeriloginterviewQuestions4
DIGITALDESIGNINTERVIEW
QUESTIONS
BeforepoweringontheFPGA,configurationdataisstoredexternallyina
PROMorsomeothernonvolatilemediumeitheronorofftheboard.After
applyingpower,theconfigurationdataiswrittentotheFPGAusinganyof
fivedifferentmodes:MasterParallel,SlaveParallel,MasterSerial,Slave
Serial,andBoundaryScan(JTAG).TheMasterandSlaveParallelmodes
Modeselectingpinscanbesettoselectthemode,referdatasheetfor
furtherdetails.
5)TellmesomeoffeaturesofFPGAyouarecurrentlyusing?
Iamtakingexampleofxc3s5000toansweringthequestion.
Verylowcost,highperformancelogicsolutionfor
highvolume,consumerorientedapplications
http://athpc.blogspot.in/2014_03_01_archive.html
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Densitiesashighas74,880logiccells
Upto784I/Opins
622Mb/sdatatransferrateperI/O
18singleendedsignalstandards
6differentialI/OstandardsincludingLVDS,RSDS
TerminationbyDigitallyControlledImpedance
Signalswingrangingfrom1.14Vto3.45V
DoubleDataRate(DDR)support
Logicresources
Abundantlogiccellswithshiftregistercapability
Widemultiplexers
Fastlookaheadcarrylogic
Dedicated18x18multipliers
Upto1,872KbitsoftotalblockRAM
Upto520KbitsoftotaldistributedRAM
DigitalClockManager(uptofourDCMs)
Clockskewelimination
Eightglobalclocklinesandabundantrouting
6)Whatisgatecountofyourproject?
Wellminewas3.2million,Idontknowyours.!
7)Canyoulistoutsomeofsynthesizableandnonsynthesizable
constructs?
notsynthesizable>>>>
initial
ignoredforsynthesis.
delays
ignoredforsynthesis.
events
notsupported.
real
Realdatatypenotsupported.
time
Timedatatypenotsupported.
forceandrelease
Forceandreleaseofdatatypesnotsupported.
forkjoin
Usenonblockingassignmentstogetsameeffect.
userdefinedprimitives
Onlygatelevelprimitivesaresupported.
synthesizableconstructs>>
assign,forloop,GateLevelPrimitives,repeatwithconstantvalue...
8)Canyouexplainwhatstruckatzeromeans?
ThesestuckatproblemswillappearinASIC.Sometimes,thenodeswill
permanentlytieto1or0becauseofsomefault.Toavoidthat,weneedto
providetestabilityinRTL.Ifitispermanently1itiscalledstuckat1Ifitis
permanently0itiscalledstuckat0.
9)Canyoudrawgeneralstructureoffpga?
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10)DifferencebetweenFPGAandCPLD?
FPGA:
a)SRAMbasedtechnology.
b)Segmentedconnectionbetweenelements.
c)Usuallyusedforcomplexlogiccircuits.
d)Mustbereprogrammedoncethepowerisoff.
e)Costly
CPLD:
a)FlashorEPROMbasedtechnology.
b)Continuousconnectionbetweenelements.
c)Usuallyusedforsimplerormoderatelycomplexlogiccircuits.
d)Neednotbereprogrammedoncethepowerisoff.
e)Cheaper
11)Whataredcm's?whytheyareused?
Digitalclockmanager(DCM)isafullydigitalcontrolsystemthat
usesfeedbacktomaintainclocksignalcharacteristicswitha
highdegreeofprecisiondespitenormalvariationsinoperating
temperatureandvoltage.
ThatisclockoutputofDCMisstableoverwiderangeoftemperatureand
voltage,andalsoskewassociatedwithDCMisminimalandallphasesof
inputclockcanbeobtained.TheoutputofDCMcomingformglobalbuffer
canhandlemoreload.
12)FPGAdesignflow?
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Also,Pleaserefertopresentationsectionsynthesispptonthissite.
13)whatisslice,clb,lut?
Iamtakingexampleofxc3s500toanswerthisquestion
TheConfigurableLogicBlocks(CLBs)constitutethemainlogicresourcefor
implementingsynchronousaswellascombinatorialcircuits.
CLBareconfigurablelogicblocksandcanbeconfiguredtocombo,ramorrom
dependingoncodingstyle
CLBconsistof4slicesandeachsliceconsistoftwo4inputLUT(lookup
table)FLUTandGLUT.
14)Canaclbconfiguredasram?
YES.
Thememoryassignmentisaclockedbehavioralassignment,Readsfromthe
memoryareasynchronous,Andalltheaddresslinesaresharedbytheread
andwritestatements.
15)Whatispurposeofaconstraintfilewhatisitsextension?
TheUCFfileisanASCIIfilespecifyingconstraintsonthelogicaldesign.You
createthisfileandenteryourconstraintsinthefilewithatexteditor.You
canalsousetheXilinxConstraintsEditortocreateconstraintswithina
UCF(extention)file.Theseconstraintsaffecthowthelogicaldesignis
implementedinthetargetdevice.Youcanusethefiletooverrideconstraints
specifiedduringdesignentry.
16)WhatisFPGAyouarecurrentlyusingandsomeofmainreasons
forchoosingit?
17)DrawaroughdiagramofhowclockisroutedthroughoutFPGA?
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18)Howmanyglobalbuffersarethereinyourcurrentfpga,whatis
theirsignificance?
Thereare8oftheminxc3s5000
AnexternalclocksourceenterstheFPGAusingaGlobalClockInputBuffer
(IBUFG),whichdirectlyaccessestheglobalclocknetworkoranInputBuffer
(IBUF).ClocksignalswithintheFPGAdriveaglobalclocknetusingaGlobal
ClockMultiplexerBuffer(BUFGMUX).Theglobalclocknetconnectsdirectly
totheCLKINinput.
19)Whatisfrequencyofoperationandequivalentgatecountofur
project?
20)Tellmesomeoftimingconstraintsyouhaveused?
21)Whyismaptimingoptionused?
Timingdrivenpackingandplacementisrecommendedtoimprovedesign
performance,timing,andpackingforhighlyutilizeddesigns.
22)Whataredifferenttypesoftimingverifications?
Dynamictiming:
a.Thedesignissimulatedinfulltimingmode.
b.Notallpossibilitiestestedasitisdependentontheinputtestvectors.
c.Simulationsinfulltimingmodeareslowandrequirealotofmemory.
d.Bestmethodtocheckasynchronousinterfacesorinterfacesbetween
differenttimingdomains.
Statictiming:
a.Thedelaysoverallpathsareaddedup.
b.Allpossibilities,includingfalsepaths,verifiedwithouttheneedfortest
vectors.
c.Muchfasterthansimulations,hoursasopposedtodays.
d.Notgoodwithasynchronousinterfacesorinterfacesbetweendifferent
timingdomains.
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23)ComparePLL&DLL?
PLL:
PLLshavedisadvantagesthatmaketheiruseinhighspeeddesigns
problematic,particularlywhenbothhighperformanceandhighreliabilityare
required.
ThePLLvoltagecontrolledoscillator(VCO)isthegreatestsourceof
problems.Variationsintemperature,supplyvoltage,andmanufacturing
processaffectthestabilityandoperatingperformanceofPLLs.
DLLs,however,areimmunetotheseproblems.ADLLinitssimplestform
insertsavariabledelaylinebetweentheexternalclockandtheinternal
clock.Theclocktreedistributestheclocktoallregistersandthenbackto
thefeedbackpinoftheDLL.
ThecontrolcircuitoftheDLLadjuststhedelayssothattherisingedgesof
thefeedbackclockalignwiththeinputclock.Oncetheedgesoftheclocks
arealigned,theDLLislocked,andboththeinputbufferdelayandtheclock
skewarereducedtozero.
Advantages:
precision
stability
powermanagement
noisesensitivity
jitterperformance.
24)GiventwoASICs.onehassetupviolationandtheotherhashold
violation.howcantheybemadetoworktogetherwithoutmodifying
thedesign?
Slowtheclockdownontheonewithsetupviolations..
Andaddredundantlogicinthepathwhereyouhaveholdviolations.
25)Suggestsomewaystoincreaseclockfrequency?
Checkcriticalpathandoptimizeit.
Addmoretimingconstraints(overconstrain).
pipelinethearchitecturetothemaxpossibleextentkeepinginmindlatency
req's.
26)WhatisthepurposeofDRC?
DRCisusedtocheckwhethertheparticularschematicandcorresponding
layout(especiallythemasksetsinvolved)catertoapredefinedruleset
dependingonthetechnologyusedtodesign.Theyareparameterssetaside
bytheconcernedsemiconductormanufacturerwithrespecttohowthemasks
shouldbeplaced,connected,routedkeepinginmindthatvariationsinthe
fabprocessdoesnoteffectnormalfunctionality.Itusuallydenotesthe
minimumallowableconfiguration.
27)WhatisLVsandwhydowedothat.Whatisthedifference
betweenLVSandDRC?
Thelayoutmustbedrawnaccordingtocertainstrictdesignrules.DRChelps
inlayoutofthedesignsbycheckingifthelayoutisabidebythoserules.
Afterthelayoutiscompleteweextractthenetlist.LVScomparesthenetlist
extractedfromthelayoutwiththeschematictoensurethatthelayoutisan
identicalmatchtothecellschematic.
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28)WhatisDFT?
DFTmeansdesignfortestability.'DesignforTestorTestability'a
methodologythatensuresadesignworksproperlyaftermanufacturing,
whichlaterfacilitatesthefailureanalysisandfalseproduct/piecedetection
Otherthanthefunctionallogic,youneedtoaddsomeDFTlogicinyour
design.Thiswillhelpyouintestingthechipformanufacturingdefectsafterit
comefromfab.Scan,MBIST,LBIST,IDDQtestingetcareallpartofthis.(this
isahotfieldandwithlotsofopportunities)
29)TherearetwomajorFPGAcompanies:XilinxandAltera.Xilinx
tendstopromoteitshardprocessorcoresandAlteratendsto
promoteitssoftprocessorcores.Whatisthedifferencebetweena
hardprocessorcoreandasoftprocessorcore?
Ahardprocessorcoreisapredesignedblockthatisembeddedontothe
device.IntheXilinxVirtexIIPro,someofthelogicblockshavebeen
removed,andthespacethatwasusedfortheselogicblocksisusedto
implementaprocessor.TheAlteraNios,ontheotherhand,isadesignthat
canbecompiledtothenormalFPGAlogic.
30)Whatisthesignificanceofcontaminationdelayinsequential
circuittiming?
Lookatthefigurebelow.tcdisthecontaminationdelay.
Contaminationdelaytellsyouifyoumeettheholdtimeofaflipflop.To
understandthisbetterpleaselookatthesequentialcircuitbelow.
Thecontaminationdelayofthedatapathinasequentialcircuitiscriticalfor
theholdtimeattheflipflopwhereitisexiting,inthiscaseR2.
mathematically,th(R2)<=tcd(R1)+tcd(CL2)
ContaminationdelayisalsocalledtminandPropagationdelayisalsocalled
tmaxinmanydatasheets.
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31)WhenareDFTandFormalverificationused?
DFT:
manufacturingdefectslikestuckat"0"or"1".
testforsetofrulesfollowedduringtheinitialdesignstage.
Formalverification:
Verificationoftheoperationofthedesign,i.e,toseeifthedesignfollows
spec.
gatenetlist==RTL?
usingmathematicsandstatisticalanalysistocheckforequivalence.
32)WhatisSynthesis?
Synthesisisthestageinthedesignflowwhichisconcernedwithtranslating
yourVerilogcodeintogatesandthat'sputtingitverysimply!Firstofall,
theVerilogmustbewritteninaparticularwayforthesynthesistoolthatyou
areusing.Ofcourse,asynthesistooldoesn'tactuallyproducegatesitwill
outputanetlistofthedesignthatyouhavesynthesisedthatrepresentsthe
chipwhichcanbefabricatedthroughanASICorFPGAvendor.
33)Weneedtosampleaninputoroutputsomethingatdifferent
rates,butIneedtovarytherate?What'sacleanwaytodothis?
Many,manyproblemshavethissortofvariableraterequirement,yetweare
usuallyconstrainedwithaconstantclockfrequency.Onetrickisto
implementadigitalNCO(NumericallyControlledOscillator).AnNCOis
actuallyverysimpleand,whileitismostnaturallyunderstoodashardware,it
alsocanbeconstructedinsoftware.TheNCO,quitesimply,isan
accumulatorwhereyoukeepaddingafixedvalueoneveryclock(e.g.ata
constantclockfrequency).WhentheNCO"wraps",yousampleyourinputor
doyouraction.Byadjustingthevalueaddedtotheaccumulatoreachclock,
youfinelytunetheAVERAGEfrequencyofthatwrapevent.Nowyoumay
haverealizedthatthewrappingeventmayhavelotsofjitteronit.True,but
youmayusethewraptoincrementyetanothercounterwhereeach
additionalDivideby2bitreducesthisjitter.TheDDSisarelatedtechnique.
IhavetwoexamplesshowingbothanNCOsandaDDSinmyFileArchive.
Thisistrickytograspatfirst,buttremendouslypowerfulonceyouhaveitin
yourbagoftricks.NCOsalsorelatetodigitalPLLs,TimingRecovery,TDMA
andother"variablerate"phenomena
34)HowarefpgasdifferentthanASICs?
Hint:FPGAs(FieldProgrammableGateArrays)caneasilybere
programmedtoadifferentcircuitwithinfewhours.ASICsarecustomcircuits
whicharemanufacturedonlyonce(noreusefordifferentpurposes).
35)ExplainCLBs,LUTsofFPGAs?Hint:LUTs,CLBsorPLBsdiscussion
next:FPGALookUPTables(LUT).LUTisamultiinputandsingleoutput
blockthatiswidelyusedforlogicmappingintruthtableformat.ALUTcan
usevarioussizeRAMblockstostorelogic.
AtypicallayoutoftheFPGAisanarrayofinterconnectedprogrammable
LogicBlocks(PLB)orconfigurablelogicblocks(CLB).APLBorCLBcanitself
consistsofmultipleLUTs,oneormoreofAddersandmanyRegisters
runningeggs9:01
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BooleanAlgebra
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http://fullchipdesign.com/bohundual.htm
DualityPrinciple
ThedualitypropertyofBooleanalgebrastatethatallbinaryexpressions
remainvalidwhenfollowingtwostepsareperformed:
Step1:InterchangeORandANDoperators.
Step2:Replaceall1sby0sand0sby1s
HuntingtonPostulates
Addinganumberto0:
P1.Postulate:x+0=x,nextFromdualityofP1
P2.Postulate:x*1=x
SumofanumberanditscomplementfromaSetis1
P3.Postulate:x+x=1,nextFromdualityofP3
P4.Postulate:x*x=0
P5.Postulate:x+y=y+x
FromdualityofP5
P6.Postulate:x*y=y*x
Fromdistributivepropertyofbinarynumberswehave:
P7.Postulate:x(y+z)=xy+xz
FromdualityofP7
a+bc=(a+b)(a+c)
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http://fullchipdesign.com/digitalbasicstut.htm
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Google
http://fullchipdesign.com/fpga_interview_questions.htm
Q.ExplainCLBs,LUTsofFPGAs?
Hint:LUTs,CLBsorPLBsdiscussionnext:
FPGALookUPTables(LUT).
LUTisamultiinputandsingleoutputblockthatiswidelyusedforlogic
mappingintruthtableformat.ALUTcanusevarioussizeRAMblocksto
storelogic.
FPGAPLBsorCLBs.
AtypicallayoutoftheFPGAisanarrayofinterconnectedprogrammable
LogicBlocks(PLB)orconfigurablelogicblocks(CLB).APLBorCLBcanitself
consistsofmultipleLUTs,oneormoreofAddersandmanyRegisters.
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Q.WhatinformationfromthetargetedfpgadeviceisrequiredinRTL
synthesis?Hint:Device/partnumber,Speedgradeetc.Deviceoptions:
partnumber,technology,package,Speedgradeetc.Mappingoptions:
resource_sharing1(forOn)frequency10.000(10MHzoperation)
fanout_limit10000pipe1retiming1.Manymoreoptionsarepossibleand
theyaredependentontechnology.
Q.Duringwhichpartofthefpgaflowyouspecifytheclock
frequencyforthedesign?Hint:Bothsynthesisandlayout..
Q.Howtoconstrainasyncclockcrossingpathsindesign?
Hint:Falsepathit.Noneedtospecifytiminginformationforthesepaths.
Q.Howtocontrolresetsdeassertionindesignwhenclocksare
generatedfromPLLsonfpga?Hint:LogicalANDofexternalhardware
resetandPLLlocksignal.
Q.Whatkindofsanitychecksaregoodtolookforinrtlsynthesis
logs?Hint:Lookforlatches,feedbackmuxs,combinationalloops,tristate
logic,blackboxesetc.
QCanclockgatingcells(latchbased)foradesigntargetedforASIC
canbeportedtoFPGAs?Hint:Maybe,usefpgaspecificfunctions.Altera
FPGAsuseALT_CLKCTRLblockforclockgating.Itsalsousedforclock
multiplexing.
Q.HowtoimplementsynchronousMemoryimplementationtoinfer
FPGAsyncRAMblocks.Hint:Accessfollowinglink.
Q.WhatkindofsanitychecksoneshoulddofromPlaceandroute
logs?
Hint:
1.Lookatthedesignutilization.2.LookforunconnectedIOs.
3.Timingreportshouldnothaveanyfailingpaths.Nosetupandhold
violations.
QWhatarethedifferentfpgaflowsprimarilyusedinindustry?
Hint:Altera,Xilinx,LatticeSemiconductor,etc.
QwhataredifferentProgrammabilityoptionsforFPGAs?Hint:SRAM
basedXilinx,alteraAntifusebasedActel,QuicklogicEPROM/EEPROM
basedNotcommonlyused
QWhataremajordifferencesinSRAMandAntifuseProgramming?
Hint:Antifuse:nonreprogrammable,highspeed,lowarea.SRAMbased:
reprogrammable,moredelay,morearea.
runningeggs8:45
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DigitaldesignInterviewQuestions
http://basicsofvlsi.blogspot.com/2011/01/digitaldesigninterview
questions.html
IfinvertedoutputofDflipflopisconnectedtoitsinputhowtheflipflopbehaves?
Designacircuittodivideinputfrequencyby2?
DesignadividebytwocounterusingDLatch.
Designadivideby3sequentialcircuitwith50%dutycycle.
Whatarethedifferenttypesofadderimplementation?
DrawaTransmissionGatebasedDLatch?
GivethetruthtableforaHalfAdder.Giveagatelevelimplementationofthe
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same.
DesignanORgatefrom2:1MUX.
WhatisthedifferencebetweenaLATCHandaFLIPFLOP?
DesignaDFlipFlopfromtwolatches.
Designa2bitcounterusingDFlipFlop.
Whatarethetwotypesofdelaysinanydigitalsystem
DesignaTransparentLatchusinga2:1Mux.
Designa4:1Muxusing2:1Mux's.
Whatismetastablestate?Howdoesitoccur?
Whatismetastablity?
Designa3:8decoder
DesignaFSMtodetectsequence"101"ininputsequence
ConvertNANDgateintoInverterintwodifferentways.
DesignaDandTflipflopusing2:1muxonly.
DesignDLatchfromSRflipflop.
DefineClockSkew,NegativeClockSkew,PositiveClockSkew?
Whatisracecondition?Howitoccurs?Howtoavoidit?
Designa4bitGrayCounter?
Design4bitsynchronouscounter,asynchronouscounter?
Designa16byteasynchronousFIFO?
WhatisthedifferencebetweenaEEPROMandFLASH?
WhatisthedifferencebetweenaNANDbasedFlashandNORbasedFlash?
Whichoneisgood:asynchronousresetorsynchronousreset?Why?
Designasimplecircuitbasedoncombinationallogictodoubletheoutputfrequency.
Whatisthedifferencebetweenflipflopandlatch?
Implementcomparatorusingcombinationallogic,thatcomparestwo2bitnumbers
AandB.Thecomparatorshouldhave3outputs:A>B,A<a="B.">
GivetwowaysofconvertingatwoinputNANDgatetoaninverter?
Whatisthedifferencebetweenmealyandmoorestatemachines?
Whatisthedifferencebetweenlatchbaseddesignandflipflopbaseddesign?
Whatismetastabilityandhowtopreventit?
DesignafourinputNANDgateusingonlytwoinputNANDgates.
Whyaremostinterruptsactivelow?
Howdoyoudetectiftwo8bitsignalsaresame?
7bitringcounter'sinitialstateis0100010.Afterhowmanyclockcycleswillit
returntotheinitialstate?
DesignallthebasicgatesNOT,AND,OR,NAND,NOR,XOR,XNORusing2:1
Multiplexer.
Howwillyouimplementafullsubtractorfromafulladder?
Ina3bitJohnson'scounterwhataretheunusedstates?
WhatisdifferencebetweenRAMandFIFO?
WhatisanLFSR?Listafewofitsindustryapplications.
Implementthefollowingcircuits:
(a)3inputNANDgateusingminimumnumberof2inputNANDgates
(b)3inputNORgateusingminimumnumberof2inputNORgates
(c)3inputXNORgateusingminimumnumberof2inputXNORgatesassuming3
inputsA,B,C?
DesignaDlatchusing(a)using2:1Mux(b)fromSRLatch?
HowtoimplementaMasterSlaveflipflopusinga2to1mux?
Howmany2inputxor'sareneededtoinplement16inputparitygenerator?
Convertxorgatetobufferandinverter.
Differencebetweenonehotandbinaryencoding?
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Whataredifferentwaystosynchronizebetweentwoclockdomains?
Howtocalculatemaximumoperatingfrequency?
Howtofindoutlongestpath?
Howtoachieve180degreeexactphaseshift?
WhatissignificanceofrasandcasinSDRAM?
Tellsomeofapplicationsofbuffer?
ImplementanANDgateusingmux?
Whatwillhappenifcontentsofregisterareshifterleft,right?
Whatisthebasicdifferencebetweenanaloganddigitaldesign?
Whatadvantagesdosynchronouscountershaveoverasynchronouscounters?
Whattypesofflipflopscanbeusedtoimplementthememoryelementsofa
counter?
Whataretheadvantagesofusingamicroprocessortoimplementacounterrather
thantheconventionalmethod(flipflopandlogicgates)?
WhatistheprincipaladvantageofGrayCodeoverstraight(conventional)binary?
WhatdoesPipeliningdo?
Designdivideby2,divideby3circuitwithequaldutycycle.
Howmany4:1muxdoyouneedtodesigna8:1mux?
WhatisDWord,Qword?
DefineMoore,Mealystatemachines.Whichoneisgoodfortiming?
DesignaFSMtodetect10110.Whatistheminimumnumberofflopsrequired?
Designasimplecircuitbasedoncombinationallogictodoubletheoutputfrequency.
Designa2bitup/downcounterwithclearusinggates.(Noverilogorvhdl)
Designafinitestatemachinetogiveamodulo3counterwhenx=0andmodulo4
counterwhenx=1.
Minimize:S=A'+AB
WhatisthefunctionofaDflipflop,whoseinvertedoutputsareconnectedtoits
input?
Howtosynchronizecontrolsignalsanddatabetweentwodifferentclockdomains?
Describeafinitestatemachinethatwilldetectthreeconsecutivecointosses(ofone
coin)thatresultsinheads.
Inwhatcasesdoyouneedtodoubleclockasignalbeforepresentingittoa
synchronousstatemachine?
Howmanybitcombinationsarethereinabyte?
WhatarethedifferentAddercircuitsyoustudied?
GivethetruthtableforaHalfAdder.Giveagatelevelimplementationofthe
same.
Convert65(Hex)toBinary
Convertanumbertoitstwo'scomplimentandback.
Whatisthe1'sand2'scomplementofthedecimalnumber25.
IfA?B=CandC?A=Bthenwhatisthebooleanoperator?
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VLSIFPGADesign&VerificationQuestions
http://basicsofvlsi.blogspot.com/2011/10/vlsifpgadesignverification
questions.html
1.WhatisFPGA?
2.WhatisthesignificanceofFPGAsinmoderndayelectronics?
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3.WhatisSynthesis?
4.FPGAdesignflow?
5.TellmesomefeaturesofFPGAyouarecurrentlyusing?
6.WhatisLUT?
7.Whatvalueisinferredwhenmultipleproceduralassignmentsmadetothe
sameregvariableinanalwaysblock?
8.Canyouexplainwhatstuckatzeromeans?
9.HowtogenerateclocksonFPGA?
10.WhatareDCMs?Whytheyareused?
11.HowdoyouimplementDCM?
12.Whyismaptimingoptionused?
13.Whataredifferenttypesoftimingverifications?
14.WhatisFPGAyouarecurrentlyusingandsomeofmainreasonsfor
choosingit?
15.GiventwoASICs.onehassetupviolationandtheotherhashold
violation.howcantheybemadetoworktogetherwithoutmodifyingthe
design?
16.WhatisLVsandwhydowedothat.WhatisthedifferencebetweenLVS
andDRC?
17.WhatisminimumandmaximumfrequencyofDCMinspartan3series
fpga?
18.Whatisthepurposeofaconstraintfilewhatisitsextension?
19.Tellmesomeoftimingconstraintsyouhaveused?
20.Canyoulistoutsomeofsynthesizableandnonsynthesizableconstructs?
21.WhenareDFTandFormalverificationused?
22.Canyoudrawgeneralstructureoffpga?
23.WhataredifferenttypesofFPGAprogrammingmodes?whatareyou
currentlyusing?howtochangefromonetoanother?
24.Howmanyglobalbuffersarethereinyourcurrentfpgawhatistheir
significance?
25.Whatisgatecountofyourproject?
26.Canyousuggestsomewaystoincreaseclockfrequency?
27.Whatisthesignificanceofcontaminationdelayinsequentialcircuit
timing?
28.Supposeforapieceofcodeequivalentgatecountis600andforanother
codeequivalentgatecountis50,000willthesizeofbitmapchange?Inother
wordswillsizeofbitmapchangeitgatecountchange?
29.Whatdoconditionalassignmentsgetinferredinto?
30.WhataredifferenttypesofFPGAprogrammingmodes?Whatareyou
currentlyusing?Howtochangefromonetoanother?
31.Whatlogicisinferredwhentherearemultipleassignstatements
targetingthesamewire?
32.ComparePLL&DLL?
33.Howtoachieve180degreeexactphaseshift?
34.Weneedtosampleaninputoroutputsomethingatdifferentrates,butI
needtovarytherate?Whatsacleanwaytodothis?
35.Whatisslice?WhatisCLB?
36.CanaCLBconfiguredasram?
37.WhatisthepurposeofDRC?
38.Whatisfrequencyofoperationandequivalentgatecountofurproject?
39.WhatarethedifferencesbetweenFPGAandCPLD?
40.DrawaroughdiagramofhowclockisroutedthroughoutFPGA?
41.WhatisDFT?
42.WhatisFPGAyouarecurrentlyusingandsomeofmainreasonsfor
choosingit?
43.DrawaroughdiagramofhowclockisroutedthroughoutFPGA?
44.WhatisSOPCBuilder?
45.HowdoyouimplementtheGCLKwhenthereislackofSource?
46.WhatarethelatestFPGAsyoulike?Why?
47.WhatisaSoC(SystemOnChip),ASIC,fullcustomchip,andanFPGA?
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48.Howdoyoumeasurethesizeanddensityofvariousprogrammablelogic
devices?
49.Whatissoftprocessor?Whatishardprocessor?
50.Whatismeantby90nmtechnology?
51.Whatarethedifferentformsofpullup?
52.Whatdoyoumeanbytranslationandmapping?
53.Whatdoyoumeanbyspeedgrade?
54.WhatisthedifferencebetweenASICDesignandFPGADesign?
55.Setuptimeandholdtimeindigitalcircuits.
56.FalsepathinFPGAs,Criticalpath,Negativeslack,Jittervs.clockskew.
57.Routingdelay,Floptooutdelay,Floptoflopdelay,Padtoflopdelay,
Boarddelay.
58.KnowledgeofSynthesisandlayoutconstraints.
runningeggs8:33
Google
FPGAInterviewQuestions
http://basicsofvlsi.blogspot.com/2011/10/fpgainterviewquestions.html
1.WhatisthefullformofRTL?
2.WhatisthedifferencebetweenRTLandHDL?
3.Drawthestatediagramtodetectasequence?
4.Drawthestatediagramofatrafficlightcontroller?
5.WhichoneisfasterCarrylookaheadorripplecarryadder?
6.WhatisthedifferencebetweenBigEndeanformatandLittleEndean
format?
7.CanyoumodelSRAMatRTLlevel?
8.Whatdoyoumeanbyconcurrentstatement?
9.Definecomponentinstantiation?
10.Whatisthedifferencebetweenvariableandsignal?
11.Listsomesequentialstatements?
12.Defineatestbench?
13.Whataretheadvantagesoftestbenches?
14.Whatisthedifferencebetweenbehavioralsimulationandtiming
simulation?
15.Doesfrequencyofoperationdependoncriticalpathinacircuit?Justify?
16.Whatisslack?
17.Whataredifferenttypesofscaling?Whichoneisusedandwhy?
18.WhatarethedifferentdesignstylesinVLSI?
19.WhatisthefullformofABEL?
20.Whatisentrydelayandexitdelay?
21.WhatisControllabilityandObservabilityintesting?
22.Whatisfaultcoverage?
23.WhatisDFT?Whatisitsimportance?
24.ExpandBIST?Explain?
25.Whatisthedifferencebetweentestingandverification?
26.Givenacircuitwithafaultyouhavetofindthetestvectortodetectthat
fault?
27.Consideracounter.Iwantittosenseoddpulsesorevenpulses
(alternatepulses).Howwillyoudoit?
28.WhatisSynthesis?
29.Whataresetuptime&holdtimeconstraints?Whatdotheysignify?
Whichoneiscriticalforestimatingmaximumclockfrequencyofacircuit?
30.WhatsthecriticalpathinaSRAM?
31.DrawthetimingdiagramforaSRAMRead.Whathappensifwedelaythe
enablingofClocksignal?
32.Drawa6TSRAMCellandexplaintheReadandWriteoperations
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33.DrawtheSRAMWriteCircuitry
34.Approximately,whatwerethesizesofyourtransistorsintheSRAMcell?
Howdidyouarriveatthosesizes?
35.Howwillyouallocateyourtimebetweenarchitecture,coding,and
verification?
36.HowdoyoudifferentiatebetweencodinginC/C++andatRTL(Register
TransferLevel)?
37.HowtoimplementHalfadderandfulladderinRTL?
38.WhenthelatchesareinferredinRTL?
runningeggs8:32
Google
http://learnfpga.blogspot.com/p/fpgavlsiinterviewquestions.html
ListofcommonlyaskedquestionsinthefieldofVLSI&FPGA.Listwillkeep
extendinginfuture.
YouguysarewelcometosharequestionsrelatedtoVLSI/FPGA/ASIC,put
themincommentssection,Iwilladthemalsointhelistbelow:
1. What'sthedifferencebetweenlatchandflipflop?
2. Makea2inputAND/OR/XORgateusing2:1MUX.
3. MakeaDlatchusing2:1MUX.
4. ExplainanyFPGAarchitecture.
5. Whatisglobalclockbufferandwhyitisused?
6. Howmany2:1MUXeswillbeneededtocreatea4096:1MUX?
7. Whatareholdtimeandsetuptimeincontextofflipflop?Alsoexplain
metastablityinflipflops.
8. ExplainFPGAdesignflow.
9. Whatisnetlistsimulationandhowtoperformthis?
10. Howmany4x4multipliersareneeded(inadditiontofulladders)to
realize8x8multiplier?
11. Drawstatemachinediagramforalogictodetectbinarysequence
"101011".
12. Whatispipeliningindigitalcircuitandhowdoesitimprovethetiming
performance?Alsoexplainit'ssideeffects.
13. What'sregisterreplication,whydoweneedregisterreplicationindigital
circuits?
14. What'smetastabilityandhowwecanreduceit'sprobability?Explain
twoflipflopsynchronizer.
15. What'sEDIFfileincontextofFPGAsynthesis?
16. CalculatethedepthofFIFOrequiredifwriteclockis50MHz,readclock
is20MHzandblocksizeis100.
17. HowtowriteverilogcodeforfollowingRAMconfigurationmodes:
Singleport/dualportwritefirstmode
Singleport/dualportreadfirstmode
18. Draw2:1MUXusingtransmissiongates.
19. ImplementY=AB+BCfunctionusing4:1MUX.
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20. What'sthedifferencebetweenblockingandnonblockingassignments
inVerilog?
21. DesignanFSMthatcangenerateasinglepulseaftercertainno.of
risingclkedge.Suchno.isdefinedbytheinput.
22. Howtofixtheholdtimeviolationafterthechipwasfabricated?
23. HowisraceavoidedinSystemVerilogtestbench?
24. HowmanyflopswillbethereinFSMifyouhave4states?
25. Whenclockisx,whatistheoutput?
26. Howwouldyoudesignforclockdomaincrossing?
27. Usingasimplelogicgate,convertaSETtypefloptoaRESETtypeflop.
28. Whatismulticycleandfalsepathinadesign?
29. Whatisskewinadesign?
30. Whatisthedifferencebetweentasksandfunctioninsytemverilog.
Whichoneofthemisreentrant?
31. WhatisthedifferencebetweenblockRAM&DistributedRAMinan
FPGA?
32. HowwillyoumoveenablecontroltothedatapathofaDflop?
33. Howwillyoumovesyncset/rstlogictodatapathofaDflop?
runningeggs8:30
Google
MISCproblems
http://www.asic.co.in/Index_files/miscfaq.htm
1)Explainzenerbreakdownandavalanchebreakdown?
Athermallygeneratedcarrier(partofreversesaturationcurrent)fallsdown
thejunctionbarrierandacquiresenergyfromtheappliedpotential.This
carrierscollideswithacrystalionandimpartssufficientenergytodisrupta
covalentbond.Inadditiontotheoriginalcarrier,anewelectronholepairhas
beengenerated.Thesecarriersmayalsopickupsufficientenergyand
createsstillanotherelectronholepair.Thiscumulativeprocessiscalledthe
Avalanchebreakdown.
Areverseelectricfieldatthejunctioncausesastrongforcetobeappliedon
aboundedelectronbythefieldtotearitoutofitscovalentbond.Thenew
holeelectronpairwhichiscreatedincreasesthereversecurrent,calledzener
breakdown.
2)WhatisInstrumentationAmplifier(IA)andwhatareallthe
advantages?
Aninstrumentationamplifierisadifferentialopampcircuitprovidinghigh
inputimpedanceswitheaseofgainadjustmentbyvaryingasingleresistor
3)WhatisthefundamentaldifferencebetweenaMOSFETandBJT?
InMOSFET,currentflowiseitherduetoelectrons(nchannelMOS)ordueto
holes(pchannelMOS)
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InBJT,weseecurrentduetoboththecarriers..electronsandholes.BJTis
acurrentcontrolleddeviceandMOSFETisavoltagecontrolleddevice.
4)WhatisthebasicdifferencebetweenAnalogandDigitalDesign?
Digitaldesignisdistinctfromanalogdesign.Inanalogcircuitswedealwith
physicalsignalswhicharecontinuousinamplitudeandtime.Ex:biological
data,sesimicsignals,sensoroutput,audio,videoetc.
Analogdesignisquitechallengingthandigitaldesignasanalogcircuitsare
sensitivetonoise,operatingvoltages,loadingconditionsandotherconditions
whichhassevereeffectsonperformance.Evenprocesstechnologyposes
certaintopologicallimitationsonthecircuit.Analogdesignerhastodealwith
realtimecontinuoussignalsandevenmanipulatethemeffectivelyevenin
harshenvironmentandinbrutaloperatingconditions.
Digitaldesignontheotherhandiseasiertoprocessandhasgreatimmunity
tonoise.Noroomforautomationinanalogdesignaseveryapplication
requiresadifferentdesign.Whereasdigitaldesigncanbeautomated.Analog
circuitsgenerallydealwithinstantaneousvalueofvoltageandcurrent(real
time).Cantakeanyvaluewithinthedomainofspecificationsforthe
device.consistsofpassiveelementswhichcontributetothenoise(thermal)
ofthecircuit.Theyareusuallymoresensitivetoexternalnoisemoreso
becauseforaparticularfunctionaanalogdesign
useslotlesstransistorsprovidingdesignchallengesoverprocesscornersand
temperatureranges.dealswithalotofdevicelevelphysicsandthestateof
thetransistorplaysaveryimportantroleDigitalCircuitsontheotherhand
dealwithonlytwologiclevels0and1(Isittruethataccordingtoquantum
mechanicsthereisathirdlogiclevel?)dealwithlotmoretransistorsfora
particularlogic,easiertodesigncomplexdesigns,flexiblelogicsynthesisand
greaterspeedalthoughatthecostofgreaterpower.Lesssensitivetonoise.
designandanalysisofsuchcircuitsisdependantontheclock.challengelies
innegatingthetimingandloaddelaysandensuringthereisnosetuporhold
violation.
5)Whatisringoscillator?Andderivethefreqofoperation?
Ringoscillatorcircuitisacoupledinverterchainwiththeoutputbeing
connectedtotheinputasfeedback.Thenumberofstages(inverters)is
alwaysoddtoensurethatthereisnosinglestablestate(outputvalue).
sometimesoneofthestagesconsistsofalogicgatewhichisusedto
initialiseandcontrolthecircuit.Thetotaltimeperiodofoperationisthe
productof2*numberofgatesandgate(inverter)delay.Andfrequencyof
operationwillbeinverseoftimeperiod.
Application:usedasprototypecircuitsformodelinganddesigningnew
semiconductorprocessesduetosimplicityindesignandeaseofuse.Also
formsapartofclockrecoverycircuit.
6)WhatareRTL,Gate,MetalandFIBfixes?Whatisa"sewingkits"?
ThereareseveralwaystofixanASICbaseddesign.>Fromeasiesttomost
extreme:
RTLFix>GateFix>MetalFix>FIBFix
First,let'sreviewfundementals.AstandardcellASICconsistsofatleast2
dozenmanufacturedlayers/masks.Lowerlayersconistsofmaterialsmaking
uptheactualCMOStransistorsandgatesofthedesign.Theupper36layers
aremetallayersusedticonnecteverythingtogether.ASICs,ofcourse,are
notintendedtobeflexiblelikeanFPGA,however,important"fixes"canbe
madeduringthemanufacturingprocess.Theprogressionofpossiblefixesin
themanufacturinglifecycleisaslistedabove.
AnRTLfixmeansyouchangetheVerilog/VHDLcodeandyouresynthesize.
ThisusuallyimpliesanewPlance&Route.RTLfixeswouldalsoimplynew
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masks,etc.etc.Inotherwordsstartfromscratch.
AGateFixmeansthataselectnumberofgatesandtheirinterconections
maybeaddedorsubtractedfromthedesign(e.g.thenetlist).Thisavoids
resynthesis.Gatefixespreservetheprevioussynthesiseffortandinvolve
manuallyeditingagatelevelnetlistaddinggates,removinggates,etc.
GatelevelfixesaffectALLlayersofthechipandallmasks.
AMetalFixmeansthatonlytheuppermetalinterconnectlayersareaffected.
Connectionsmaybebrokenormade,butnewcellsmaynotbeadded.A
SewingKitisameansofaddinganewgateintothedesignwhileonly
affectingthemetallayers.SewingKitsaretypicallyaddedintotheinitial
designeitherattheRTLlevelorduringsynthesisbythecustomerandare
partofthenetlist.AMetalFixaffectsonlythetoplayersofthewafersand
doesnotaffectthe"base"layers.
SewingKitsaremodulesthatcontainanunusedmixofgates,flipflopsor
anyothercellsconsideredpotentiallyusefulforanunforseenmetalfix.A
SewingKitmaybespecifiedinRTLbyinstantiatingtheliteralcellsfromthe
vendorlibrary.Thecellsinthekitareusuallyconnectedsuchthateachcell's
outputisunconnectedandtheinputsaretiedtoground.Clocksandresets
maybewiredintothelargerdesign'ssignals,ornot.
AFIBFix(FocussedIonBeam)Fixisonlyperformedonacompletedchip.
FIBisasomewhatexotictechnologywhereaparticlebeamisabletomake
andbreakconnectionsonacompleteddie.FIBfixesaredoneonindividual
chipsandwouldonlybedoneasalastresorttorepairanotherwisedefective
prototypechip.Masksarenotaffectedsinceitisthefinalchipthatis
intrusivelyrepaired.
Clearly,thesesortsoffixesaretrickyandrisky.Theyareavailabletothe
ASICdeveloper,butmustbenegotiatedandcoordinatedwiththefoundry.
ASICdesignerswhohavebeenthroughenoughofthesefixesappreciatethe
valueofaddingtestandfaulttolerantdesignfeaturesintotheRTLcodeso
thatSoftwareFixescancorrectmiorsiliconproblems!
runningeggs8:28
Google
CMOSinterviewquestions
http://www.asic.co.in/Index_files/cmosfaq.htm
1)Whatislatchup?
Latchuppertainstoafailuremechanismwhereinaparasiticthyristor(such
asaparasiticsiliconcontrolledrectifier,orSCR)isinadvertentlycreated
withinacircuit,causingahighamountofcurrenttocontinuouslyflowthrough
itonceitisaccidentallytriggeredorturnedon.Dependingonthecircuits
involved,theamountofcurrentflowproducedbythismechanismcanbe
largeenoughtoresultinpermanentdestructionofthedevicedueto
electricaloverstress(EOS).
2)WhyisNANDgatepreferredoverNORgateforfabrication?
NANDisabettergatefordesignthanNORbecauseatthetransistorlevelthe
mobilityofelectronsisnormallythreetimesthatofholescomparedtoNOR
andthustheNANDisafastergate.
Additionally,thegateleakageinNANDstructuresismuchlower.Ifyou
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considert_phlandt_plhdelaysyouwillfindthatitismoresymmetricincase
ofNAND(thedelayprofile),butforNOR,onedelayismuchhigherthanthe
other(obviouslyt_plhishighersincethehigherresistancepmos'sarein
seriesconnectionwhichagainincreasestheresistance).
3)WhatisNoiseMargin?ExplaintheproceduretodetermineNoise
Margin
Theminimumamountofnoisethatcanbeallowedontheinputstagefor
whichtheoutputwillnotbeeffected.
4)Explainsizingoftheinverter?
Inordertodrivethedesiredloadcapacitancewehavetoincreasethesize
(width)oftheinverterstogetanoptimizedperformance.
5)HowdoyousizeNMOSandPMOStransistorstoincreasethe
thresholdvoltage?
6)WhatisNoiseMargin?ExplaintheproceduretodetermineNoise
Margin?
Theminimumamountofnoisethatcanbeallowedontheinputstagefor
whichtheoutputwillnotbeeffected.
7)Whathappenstodelayifyouincreaseloadcapacitance?
delayincreases.
8)Whathappenstodelayifweincludearesistanceattheoutputof
aCMOScircuit?
Increases.(RCdelay)
9)Whatarethelimitationsinincreasingthepowersupplytoreduce
delay?
Thedelaycanbereducedbyincreasingthepowersupplybutifwedosothe
heatingeffectcomesbecauseofexcessivepower,tocompensatethiswe
havetoincreasethediesizewhichisnotpractical.
10)HowdoesResistanceofthemetallinesvarywithincreasing
thicknessandincreasinglength?
R=(*l)/A.
11)ForCMOSlogic,givethevarioustechniquesyouknowto
minimizepowerconsumption?
Powerdissipation=CV2f,fromthisminimizetheloadcapacitance,dcvoltage
andtheoperatingfrequency.
12)WhatisChargeSharing?ExplaintheChargeSharingproblem
whilesamplingdatafromaBus?
IntheseriallyconnectedNMOSlogictheinputcapacitanceofeachgate
sharesthechargewiththeloadcapacitancebywhichthelogicallevels
drasticallymismatchedthanthatofthedesiredonce.Toeliminatethisload
capacitancemustbeveryhighcomparedtotheinputcapacitanceofthe
gates(approximately10times).
13)Whydowegraduallyincreasethesizeofinvertersinbuffer
design?Whynotgivetheoutputofacircuittoonelargeinverter?
Becauseitcannotdrivetheoutputloadstraightaway,sowegradually
increasethesizetogetanoptimizedperformance.
14)WhatisLatchUp?ExplainLatchUpwithcrosssectionofaCMOS
Inverter.HowdoyouavoidLatchUp?
Latchupisaconditioninwhichtheparasiticcomponentsgiverisetothe
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EstablishmentoflowresistanceconductingpathbetweenVDDandVSSwith
Disastrousresults.
15)GivetheexpressionforCMOSswitchingpowerdissipation?
CV2
16)WhatisBodyEffect?
IngeneralmultipleMOSdevicesaremadeonacommonsubstrate.Asa
result,thesubstratevoltageofalldevicesisnormallyequal.Howeverwhile
connectingthedevicesseriallythismayresultinanincreaseinsourceto
substratevoltageasweproceedverticallyalongtheserieschain(Vsb1=0,
Vsb20).WhichresultsVth2>Vth1.
17)WhyisthesubstrateinNMOSconnectedtoGroundandinPMOS
toVDD?
wetrytoreversebiasnotthechannelandthesubstratebutwetryto
maintainthedrain,sourcejunctionsreversebiasedwithrespecttothe
substratesothatwedontlooseourcurrentintothesubstrate.
18)WhatisthefundamentaldifferencebetweenaMOSFETandBJT
?
InMOSFET,currentflowiseitherduetoelectrons(nchannelMOS)ordueto
holes(pchannelMOS)InBJT,weseecurrentduetoboththecarriers..
electronsandholes.BJTisacurrentcontrolleddeviceandMOSFETisa
voltagecontrolleddevice.
19)Whichtransistorhashighergain.BJTorMOSandwhy?
BJThashighergainbecauseithashighertransconductance.Thisisbecause
thecurrentinBJTisexponentiallydependentoninputwhereasinMOSFETit
issquarelaw.
20)Whydowegraduallyincreasethesizeofinvertersinbuffer
designwhentryingtodriveahighcapacitiveload?Whynotgivethe
outputofacircuittoonelargeinverter?
Wecannotuseabiginvertertodrivealargeoutputcapacitancebecause,
whowilldrivethebiginverter?Thesignalthathastodrivetheoutputcapwill
nowseealargergatecapacitanceoftheBIGinverter.Sothisresultsinslow
raiseorfalltimes.Aunitinvertercandriveapproximatelyaninverterthats4
timesbiggerinsize.Sosayweneedtodriveacapof64unitinverterthen
wetrytokeepthesizinglikesay1,4,16,64sothateachinverterseesasame
ratioofoutputtoinputcap.Thisistheprimereasonbehindgoingfor
progressivesizing.
21)InCMOStechnology,indigitaldesign,whydowedesignthesize
ofpmostobehigherthanthenmos.Whatdeterminesthesizeof
pmoswrtnmos.Thoughthisisasimplequestiontrytolistallthe
reasonspossible?
InPMOSthecarriersareholeswhosemobilityisless[aprroxhalf]thanthe
electrons,thecarriersinNMOS.ThatmeansPMOSisslowerthananNMOS.
InCMOStechnology,nmoshelpsinpullingdowntheoutputtogroundann
PMOShelpsinpullinguptheoutputtoVdd.IfthesizesofPMOSandNMOS
arethesame,thenPMOStakeslongtimetochargeuptheoutputnode.Ifwe
havealargerPMOSthantherewillbemorecarrierstochargethenode
quicklyandovercometheslownatureofPMOS.Basicallywedoallthisto
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getequalriseandfalltimesfortheoutputnode.
22)WhyPMOSandNMOSaresizedequallyinaTransmissionGates?
InTransmissionGate,PMOSandNMOSaideachotherrathercompetingwith
eachother.That'sthereasonwhyweneednotsizethemlikeinCMOS.In
CMOSdesignwehaveNMOSandPMOScompetingwhichisthereasonwe
trytosizethemproportionaltotheirmobility.
23)Allofusknowhowaninverterworks.Whathappenswhenthe
PMOSandNMOSareinterchangedwithoneanotherinaninverter?
IhaveseensimilarQsinsomeofthediscussions.Ifthesource&drainalso
connectedproperly...itactsasabuffer.Butsupposeinputislogic1O/Pwill
bedegraded1Similarlydegraded0
24)AgoodquestiononLayouts.Give5importantDesigntechniques
youwouldfollowwhendoingaLayoutforDigitalCircuits?
a)Indigitaldesign,decidetheheightofstandardcellsyouwanttolayout.It
dependsuponhowbigyourtransistorswillbe.HavereasonablewidthforVDD
andGNDmetalpaths.MaintaininguniformHeightforallthecellisvery
importantsincethiswillhelpyouuseplaceroutetooleasilyandalsoincase
youwanttodomanualconnectionofalltheblocksitsavesonlotofarea.
b)Useonemetalinonedirectiononly,Thisdoesnotapplyformetal1.Say
youareusingmetal2todohorizontalconnections,thenusemetal3for
verticalconnections,metal4forhorizontal,metal5verticaletc...
c)Placeasmanysubstratecontactaspossibleintheemptyspacesofthe
layout.
d)Donotusepolyoverlongdistancesasithashugeresistancesunlessyou
havenootherchoice.
e)Usefingeredtransistorsasandwhenyoufeelnecessary.
f)Trymaintainingsymmetryinyourdesign.TrytogetthedesigninBITSliced
manner.
25)Whatismetastability?When/whyitwilloccur?Differentwaysto
avoidthis?
Metastablestate:Aunknownstateinbetweenthetwologicalknown
states.ThiswillhappeniftheO/Pcapisnotallowedtocharge/dischargefully
totherequiredlogicallevels.
Oneofthecasesis:Ifthereisasetuptimeviolation,metastabilitywill
occur,Toavoidthis,aseriesofFFsisused(normally2or3)whichwill
removetheintermediatestates.
26)LetAandBbetwoinputsoftheNANDgate.SaysignalAarrives
attheNANDgatelaterthansignalB.Tooptimizedelayofthetwo
seriesNMOSinputsAandBwhichonewouldyouplaceneartothe
output?
runningeggs8:27
Google
TIMINGInterviewQuestions
http://www.asic.co.in/Index_files/Timing_interview_questions.htm
Timing,animportantparameterassociatedwithSequentialCircuitdesignwill
be discussed in this tutorial. We will begin with the general concepts
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associated with timing and then will proceed with examples to better
understand their application to digital design. This tutorial consists of three
sections.
PART1Introductionandterminology
PART2Equations
PART3Exampleproblems
PART1:Introductionandterminology
============================================
============================
A Digital System Design circuit can be characterized as a 'Combinational
circuit'ora'SequentialCircuit'andwhilecalculatingforTimingwewillhave
tofirstidentifywhattypeofcircuitisinvolved.
Q1.Howdoweknow,ifgivenacircuit,whetheritisaCombinationalCircuit
oraSequentialCircuit?
[Ans] If a circuit has only combinational devices (e.g.. gates like AND, OR
etcandMUX(s))andnoMemoryelementsthenitisaCombinationalcircuit.If
thecircuithasmemoryelementssuchasFlipFlops,Registers,Counters,or
other state devices then it is a Sequential Circuit. Synchronous sequential
circuitswillalsohaveaclearlylabeledclockinput.
Q2.Arethefollowingcircuitscombinationalorsequential?
[Ans]
Q3.Whydowehavetoidentifythetypeofcircuit?Doesitreallymatter?
[Ans] It is important to identify the type of circuit because our timing
calculation approach differs accordingly. Combinational circuits timing
analysis deals primarily with propagation delay issues. Sequential circuits
haveadditionalspecifictimingcharacteristicsthatmustbesatisfiedinorder
topreventmetastability,includingsetuptime,holdtime,andminimumclock
period.Designersofsequentialdevicesmustspecifytheseimportanttiming
characteristicsinordertoallowthedevicetobeusedwithouterror.
Q4.DoallDigitalDeviceslikegatesandFlipFlopshavetimingparameters?
[Ans] Yes, all digital devices have timing parameters. In the real
environment (not Ideal as in our lab) there will be a real (non zero) value
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associatedwitheverydigitaldevice.Observetheexamplesbelow
Example1and2:
Q5.Phew!!! So many things all at the same time.....what is propagation

delay?
[Ans] All devices have some delay associated with transferring an input
change to the output. These changes are not immediate in a real
environment. This delay that is due to the signal propagation through the
deviceiscalledthepropagationdelay.
Q6.WhatisSetuptime?
[Ans]SetuptimeisatimingparameterassociatedwithSequentialDevices
(forsimplicityhenceforthIwillbeonlyreferringtotheFlipFlop).TheSetup
time is used to meet the minimum pulse width requirement for the first
(Master) latch makes up a flip flop is. More simply, the setup time is the
amount of time that an input signal (to the device) must be stable
(unchanging) before the clock ticks in order to guarantee minimum pulse
widthandthusavoidpossiblemetastability.
Q7.WhatisHoldtime?
[Ans]HoldtimeisalsoatimingparameterassociatedwithFlipFlopsandall
other sequential devices. The Hold time is used to further satisfy the
minimumpulsewidthrequirementforthefirst(Master)latchthatmakesupa
flip flop. The input must not change until enough time has passed after the
clock tick to guarantee the master latch is fully disabled. More simply, hold
timeistheamountoftimethataninputsignal(toasequentialdevice)must
be stable (unchanging) after the clock tick in order to guarantee minimum
pulsewidthandthusavoidpossiblemetastability.
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Q8.CanyougiveanexamplethatcanhelpmebetterunderstandtheSetup
andHoldtimeconcept?
[Ans] Lets consider the situation wherein I am the Flip Flop and I am to
receiveanInput(aphotoofanoldfriendwhomIhavetorecognize)nowthe
amountoftimeitwouldtaketosetupthephotointherightpositionsothatit
isvisibletomefromwhereIamsitting(sinceIamlazytowalkover)canbe
considered as the "Setup time". Now once shown the photo the amount of
timethatIkeepstaringatittillIfeelcomfortableenoughtostartrelatingit
toknownfacescanbeconsideredasthe"Holdtime".
Q9.Whatisatimingdiagram?CanweuseittobetterunderstandSetupand
Holdtime?
[Ans]Timingdiagramisacompletedescriptionofadigitalmachine.Wecan
use the timing diagram (waveform) to illustrate Setup and Hold time.
Observethewaveformgivenbelow:
Fromthetimingdiagramweobservethatwehavethreesignals:theClock,
the Flip Flop Input (D) and the Flip Flop output (Q). We have four timing
instancesandthreetimeperiods.Theinferencesfromthiswaveformwillhelp
usunderstandtheconceptofpropagationdelaySetupandHoldtime.
(1)i.e.[t2t1]istheSetupTime:theminimumamountoftimeInputmust
beheldconstantBEFOREtheclocktick.NotethatDisactuallyheldconstant
forsomewhatlongerthantheminimumamount.Theextraconstanttimeis
sometimescalledthesetupmargin.
(2) i.e. [t3 t2] is the Propagation delay of the Flip Flop: the
minimum/maximumtimefortheinputtopropagateandinfluencetheoutput.
(3)i.e.[t4t2]istheHoldtime:theminimumamountoftimetheInputis
heldconstantAFTERtheclocktick.NotethatQisactuallyheldconstantfor
somewhat longer than the minimum amount. The extra constant time is
sometimescalledtheholdmargin.
(Theabovetimingdiagramhas2clockcyclesthetimingparametersforthe
secondcyclewillalsobesimilartothatofthefirstcycle)
PART2:Equations
============================================
============================
This part of the tutorial introduces us to the various different timing
calculationsassociatedwiththiscourse.Wemaybegivenasequentialcircuit
andaskedtosolveforthetimingparameters.Letusdiscussindetailhowwe
shouldapproachsuchproblems.
Q11.Whatisthefirstthingtodoifgivenasequentialcircuitandaskedto
analyzeitstiming?
[Ans]Givenasequentialcircuititisoftenadvisabletofirstdividethecircuit
intothreedistinctpartsi.e.InputLogic,StateMemoryandtheOutputLogic.
SuchdivisionwillalsohelpwithidentifyingwhetherthegivencircuitisMealy
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or Moore. The input logic (Next State Logic) and the output logic blocks
constituteofonlycombinationallogiccomponentslikegates,muxesetc.The
state memory block is made of only sequential components like Flip Flops
etc.
Q12.CanyouexplaintheanswertoQ11moreelaborately?
[Ans]Letmeexplainusingblockdiagrams.Agivensequentialcircuitcanbe
representedineitherofthetwowaysasshownbelow.
Thefirstrepresentationshowsthesequentialcircuitwheretheinput(s)have
to pass through the State memory to affect the output. Such machines are
calledMooremachines.
The second representation shows the red bypass which signifies that the
outputcanbedirectlyaffectedbytheinputswithouthavingtopassthrough
thestatememorydevice(s).SuchdevicesarecalledMealymachines.
Q13.Canyouexplainthiswithanexample?
[Ans]Ok,considerthesequentialcircuitshownbelow
Letusnowidentifythethreedistinctpartsinthisgivensequentialcircuit.
Observethedivisiononthecircuitbelow.
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.
Observation:ThisgivencircuitisaMEALYmachine.
Q14.Nowthatwehavedividedthecircuitintomoredistinctpartshowdowe
proceedwithcalculatingthetimingparameters?
[Ans]RememberfromourdiscussioninPart1ofthistutorialweknowthat
combinational devices and sequential devices have different timing
parameters.Nowthatwehaveseparatedthembothintoseparateblockswe
candefinethemmoreclearly.Torelatethemtotheblocksletusfollowsome
convention (already discussed in part 1). Let us refer to the timing
parametersfortheinputlogic(alsoreferredtoasthenextstatelogic)and
outputlogicwiththeletterFandGrespectively.Similarly,letusrefertoall
timingparametersassociatedwiththeStatememoryblockwiththeletterR.
Q15.Whattimingparametersarecommonlyused?
[Ans]Thelistofthetimingparametersthatyoumaybeaskedtocalculate
foragivensequentialcircuitis
1.Propagationdelay,ClocktoOutput(minimum)
2.Propagationdelay,ClocktoOutput(maximum)
3.Propagationdelay,InputtoOutput(minimum)
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4.Propagationdelay,InputtoOutput(maximum)
5.SetupTime(Datainputbeforeclock)
6.HoldTime(Datainputafterclock)
7.MaximumClockrate(oritsreciprocal,minimumclockperiod)
Q16.HowdowefindthePropagationdelay,ClocktoOutput?
[Ans] Propagation delay (PD) for the circuit can be calculated as the
summation of all delays encountered from where the clock occurs to the
output.Inshort,thedelaysoftheStatememoryandtheoutputlogic.
PDClockOutput(min)=Rpd(min)+Gpd(min)
PDClockOutput(max)=Rpd(max)+Gpd(max)
Q17.HowdowefindthePropagationdelay,InputtoOutput?
[Ans] This is a property associated with Mealy machines only. In other
words, for a Moore machine the value for this timing parameter is infinity
(). The calculation (for mealy machines) is the summation of all
propagation delays encountered between the input (that influences the
outputbybypassingthestatememory)andtheoutput.
ForMOOREmachines:
PDInputOutput(min)=infinity()
PDInputOutput(max)=infinity()
ForMEALYMachines
PDInputOutput(min)=Gpd(min)
PDInputOutput(max)=Gpd(max)
Q18.HowdowecalculateSetuptime?
[Ans] The calculation for setup time is the sum of the setup time for the
concernedflipflopandthemaximumdelayfromtheinputlogic.
TSETUP=RSETUP+Fpd(MAX)
Q19.HowdowegetthevaluefortheHoldtime?
[Ans]ThevaluefortheHoldtimecanbeobtainedbythefollowingformulae
THOLD=RHOLDFpd(MIN)
The concern here is how soon (minimum time) an erroneous input can
propagateinfromtheInputlogicwhiletheFlipFlopisattemptingtoholdon
to a stable value. The negative sign can be associated with after the clock
occurstoeaseinrememberingthisformulae.
Q20.HowdowecalculatetheMaximumClockrate(MCLK)?
[Ans]Maximumclockrateiscalculatedusingtheformula
MCLK=1/TMIN
SowewillhavetocalculateTMINfirst.TMINherereferstotheminimumtime
period for correct operation of the circuit, so it is calculated using all worst
cases(maximumdelays).
TMIN=Fpd(MAX)+RSETUP+Rpd(MAX)
SohavingfoundtheminimumclockperiodletusnowcalculatefortheMCLK
MCLK=1/TMIN =(Fpd(MAX) +RSETUP +Rpd(MAX)
)1
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Q21.Pleasesummarize.
[Ans]Ok,hereiseverythingwediscussedsofarinPart2
1.PDClockOutput(min)=Rpd(min)+Gpd(min)
2.PDClockOutput(max)=Rpd(max)+Gpd(max)
3. PD Input Output (min) = infinity () (For MOORE
machines)
4. PD Input Output (max) = infinity () (For MOORE
machines)
5. PD Input Output (min) = Gpd (min) (For MEALY
machines)
6. PD Input Output (max) = Gpd (max) (For MEALY
machines)
7.TSETUP=RSETUP+Fpd(MAX)
8.THOLD=RHOLDFpd(MIN)
9. MCLK=1/TMIN =(Fpd(MAX) +RSETUP +
Rpd(MAX))1
PART3:Examples
============================================
============================
Q23.Canwegothroughatimingexample(solvedproblem)sothatwecan
haveabetterunderstandingoftheconceptsdealtsofar?
[Ans] Sure, here is a simple example to begin with, you are given a
sequential circuit as shown below and asked to calculate all the timing
parameters discussed in Part 2 of this tutorial. The information provided to
youwiththequestionistheindividualtimingparametersofthecomponents
listedinthetablebelow.
Propagation
Propagation
Setup
Hold
Device
Delay
Delay
Time
Time
(Minimum)
(Maximum)
DFlipFlop
4ns
8ns
10ns
3ns
NANDGate
3ns
6ns
X
X
BubbledAND
2ns
4ns
X
X
Gate
WiththisinformationwecanapproachtheproblemasdiscussedinPart2of
thistutoriali.e.weshallfirstdividethegivencircuitintothreedistinctparts
and then solve for timing. With practice, we can afford to skip this step of
dividingthecircuitintodistinctparts(therebysavingtime)anddirectlysolve
for timing. Since this is the first example I shall religiously follow the steps
discussedinPart2.
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Observation:ThisisaMEALYMachine.
Nowletuscalculateforallthetimingparameters.
1.PDClockOutput(min)=Rpd(min)+G pd(min)=4ns+2ns=6ns
2.PDClockOutput(max)=Rpd(max)+G pd(max)=8ns+4ns=12ns
3.PDInputOutput(min)=G pd(min)=2ns
4.PDInputOutput(max)=G pd(max)=4ns
5.TSETUP=RSETUP+F pd(MAX)=10ns+6ns=16ns
6.THOLD=RHOLDF pd(MIN)=3ns3ns=0ns.
7.TMIN=Fpd(MAX)+RSETUP+Rpd(MAX)=6ns+10ns+8ns=24ns
8.MCLK=1/TMIN=(Fpd(MAX)+RSETUP+Rpd(MAX))1=1/24ns.
Q24. Can we go through another timing example (solved problem) using

morethanoneFlipFlop?
[Ans]Ok,hereisanexample(noticehowIwritedownthecorresponding
timingvaluesforsimplicityinunderstanding)
Given with the question is the individual timing parameter for all the
componentsusedintheCircuit.Observethetablegivenbelow.
Propagation
Propagation
Device
Delay
Delay
SetupTime
HoldTime
(minimum)
(maximum)
DFlipFlop
2ns
6ns
4ns
2ns
ANDGate
2ns
4ns
X
X
2i/pNOR
2ns
3ns
X
X
Gate
ORGate
2ns
3ns
X
X
3i/pNOR
1ns
2ns
X
X
Gate
Writingthetimingparametersnexttothecomponents(foreaseinsolving)
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Sowiththetimingparametersnexttothecomponentsthecircuitnowlooks
likethis
Dividingthecircuitintodistinctpartsislefttothereader(willgivethereader
somehandsonpractice)
Nowletuscalculateforallthetimingparameters.
1.PDClockOutput(min)=Rpd(min)+G pd(min)=2ns+1ns=3ns
2.PDClockOutput(max)=Rpd(max)+G pd(max)=6ns+3ns+2ns=11ns
3.PDInputOutput(min)=G pd(min)(ForMEALYmachines)=1ns
4.PDInputOutput(max)=G pd(max)(ForMEALYmachines)=2ns
5.TSETUP=RSETUP+F pd(MAX)=4ns+4ns=8ns
6.THOLD=RHOLDF pd(MIN)=2ns2ns=0ns.
7.TMIN=Fpd(MAX)+RSETUP+Rpd(MAX)=3ns+4ns+4ns+6ns=17ns
8.MCLK=1/TMIN=(Fpd(MAX)+RSETUP+Rpd(MAX))1=1/17ns.
Q25. Are these two solved examples enough to introduce us to the timing
conceptsnecessaryforthiscourse?
[Ans]Absolutely,thetwoexamplestogethercoveralmostalltheconcepts
necessarytogetyoustartedwithunderstandingtimingproblems(theintent
ofthistutorial).Moreexampleswouldresultinspoonfeedingandwouldnot
berecommended.Interestedstudentscannowreadthetextandattemptto
solveothertimingrelatedquestionsforpractice.
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Q5.Phew!!! So many things all at the same time.....what is propagation

Q24. Can we go through another timing example (solved problem) using

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