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Volume 7, Issue 1, Jan-Feb 2016, pp. 75-86, Article ID: IJECET_07_01_008
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ISSN Print: 0976-6464 and ISSN Online: 0976-6472
IAEME Publication
1. INTRODUCTION
A radiation source in space includes Solar flares, Coronal mass ejections, Solar wind,
Galactic cosmic rays, Van Allen radiation belts, solar particle events etc. This
radiation environment consists of particles such as photons, electrons, neutrons, and
heavy ions. Widely, two major effects are with respect to radiation effects are 1)
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Cumulative Effect 2) Single Event Effect (SEE). The classification of radiation effects
shown in Fig. 1
The charge particles can hit the ICs, results in non-destructive or destructive
effects depends on the charge intensity and strike location. Particle hit leads to
erroneous performance. When a particle hit introduces IC malfunctioning but does not
damage it permanently called soft-error. Whereas any permanent damage to device
due to particle hit is regard as a hard-error. Cumulative effect is long-term effect and
changes parameters of the device. Further, it divided in to two effects. One is TID
effect, which is a result of the hole trapping in gate oxide region. When any energetic
particle hit on gate of the MOSFET or at STI (Shallow Trench Isolation) region at this
condition holes are trapping inside gate oxide or STI region, which damage the
structure of the both, gate oxide as well as isolation oxide. Due to hole trapping in
gate oxide, changes the threshold voltages of the device and due to hole trapping in
isolation oxide between two devices increasing leakage current. Another effect is
Displacement Damage (DD) effect which occurs when any energetic particle displace
atoms in silicon or insulator and creates electrically active defects. DD effect also
known as TNID (Total Non-Ionizing Dose).
SEE effect is further subdividing in to six effects. In Single Event Upset effect,
upset the storage node charge in memory due to particle strike and change the logic
level. SEU are observing in storage elements like Flip-Flop, latches SRAM cells. If
SEU effect occurring multiple storage nodes in memory, it is known as MBU &
MCU. Due to SEU effect in processor, FPGAs etc. functionally of the circuits
disturbs. This effect called SEFI. Single Event Transient is an energy pulse due to
strike on sensitive node of the circuit. Sensitive nodes are off nMOS or pMOS
transistors in the circuits. Single Event Transient (SET) effect is observing in
Combinational logic circuits. If the duration of SET pulse are more than the clock
frequency of the circuit may disturb the function of the circuits or upset the memory if
SET pulse is occurs at clock edge. SEL is triggering of the thyristor (PNPN structure)
mainly exiting in CMOS circuits due to radiation. SEB effect is occurs in power
MOSFET devices when source is forward biased and drain-source current is higher
than the breakdown voltage of the parasitic structures. SEGR effect occurs when
particle damages the gate oxide insulation of the power MOSFET. A TID, DD, SEL,
SEB and SEGR effect creates permanent damage to the devices so these types of
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A Survey of Radiation Hardening by Design (RHBD) Techniques For Electronic Systems for
Space Application
effects are categorised under hard error. SEU, SEFI, MBU & MCU are affects device
or circuits temporary so these effects are categorised under Soft error.
The rest of the paper is organised as Section 2 discusses different Radiation
Hardening by Design techniques, followed by conclusion.
Figure 2 (a) Conventional two edge nMOS and (b) Enclosed Layout Transistor nMOS (c)
Ringed Source Transistor (d) Ringed inter-digitated Transistor
Although, they provide compact design as compared to ELT, sometimes they are
not immune to TID effects. The most commonly used layout technique for TID
prevention is ELT, which is briefly describing as follow:
2.1.1. Enclosed Layout Transistor
In the beginning, this type of layout design proposed to prevent gate leakage current
in conventional CMOS process. However, after detailed mathematical analysis
performed by A. Giraldo [1] [2] for effective aspect ratio calculations, this layout
technique is being increasingly used to prevent radiation effects in nuclear and space
environment. [3]. Fig. 3(a) shows enclosed gate layout transistor where, the gate is
surrounded from outside by Drain (or Source) and enclosed Source (or Drain).
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Figure 3 (a) Enclosed Gate Layout of Transistor (b) Guard Ring in nMOS Transistor
The effective aspect ratio of ELT transistor can well estimate by below formula
[1] [2] [3]:
(1)
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A Survey of Radiation Hardening by Design (RHBD) Techniques For Electronic Systems for
Space Application
prevent inter device leakage. It has reported that devices implementing guard rings
show a very high tolerance to SEL (LET > 90 (MeV cm2) / mg) [5].
6-P channel
Figure 4 (a) SEU hardened Memory Cell by Rockett (IBM) [6] (b) SEU-Hardened Memory
Cell by Whitaker (NASA) [7]
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Figure 5 (a) Improved Whitaker Memory Cell by Liu [9] (b) SEU hardened AND/NOR gate
to design an R-S latch [10]
Figure 6 (a) HIT Memory Cell [11] (b) DICE Storage Cell [12]
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A Survey of Radiation Hardening by Design (RHBD) Techniques For Electronic Systems for
Space Application
Figure 7(a) Master Temporal Latch and Slave DICE D Flip Flop (TDFF) [14] (b) Quatro
Storage Cell [17]
The temporal latch shown in Fig. 7(a) employs a triple redundant feedback
mechanism, which separates the signal in time. This makes it immune to both SET
and SEU effects [14] [15] [16]. In Fig. 7(a) is showing a temporal latch, which
employs delay blocks marked with . This shows that the cell is SET hardened up to
the duration of one delay.
2.2.8. Quatro Latch
The Quatro latch is an eight transistors storage cell with the similar basic design
compared to a DICE latch but different interconnection topology [17]. The four
storage nodes in Quatro cell are namely A, B, C, and D (Fig. 7(b)).
Table I shows that over DICE-FF, Quatro-FF is an improvement in area, power,
and maximum clock to Q delay while keeping operational characteristics unchanged.
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Area
Power
PDP
D-FF
DICE-FF
2.95
1.8
1.4
2.5
Quatro-FF
2.5
1.4
1.6
2.2
I i n (t)=
(e e )
( )
(2)
(WL )+ C
(3)
(a)
(b)
Figure 8 (a) 2-input NAND gate (b) SEU effects (Q, (W/L), (, )). [18]
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A Survey of Radiation Hardening by Design (RHBD) Techniques For Electronic Systems for
Space Application
So, if (W/L) of the node is increase then Capacitor is charged with more charges.
As the size of any gate increase means driving strength of any gate is increase than
current produce by the particle strike on sensitive node is decrease. So if particle
strike on output node of 2-input NAND gate in Fig. 8(a) than voltage generate by that
particle decreases with increasing W/L ratio of the gate shown in Fig. 8 (b).
The idea of the authors [18] is that increased output capacitance of any gate can
make it is less sensitive to particle hit than a normal gate. This technique was
applicable to only older technology. As in the advance technologies, initial value of
output capacitance is fF. If this technique applied to advance technologies then
increased capacitance values required to satisfy the transient effect become high [19]
[20]
2.2.10. Radiation Hardened Memory Cells
Previously discussed cells have partially SEU immunity and dependent on polarity on
single node or required more power. As CMOS technology scaling down, angled
particle strike becoming more severe [21] [22].In [23], an 11 T SRAM cell has
proposed [also shown in Fig. 9(a)].
Compared with DICE, as claimed by the authors, this circuit (called 11 T) offers
(little) smaller area and considerable lower Power Delay Product (PDP). To have a
better robustness against Single Event Multiple Effects (SEME), the authors of [23],
proposed another SRAM cell in [24] [also shown in Fig. 9(b)]. They showed that, this
latter circuit (called 13 T) can tolerate the effect of Single Event Multiple
Effect(SEME) better than their proposed circuit in [23].As the authors reported in
[24], their circuit has lower delay, higher power consumption and larger area as
compared with DICE.
In [25], new SEU hardening Incorporating an extreme low power bit-cell design
(SHIELD) proposed. The authors of [26] compare proposed design with proposed
design in [12] in terms of technology scaling and effect on it shown in Fig. 9 (c).
Figure 9 (a) Proposed in [23] (b) Proposed in [24] (c) The SHIELD SRAM [25] [26]
In [27][28] novel Radiation Hardened Memory cell which has 12- Transistor and
it is capable of fully SEU immunity and also can tolerant multi bit upset as shown in
Fig. 10(a). This technique is show better result against different radiation hardening
techniques [27].
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Figure 10(a) Proposed RHM (Radiation Hardened Memory) cell [28] (b) Proposed 13-T
RHM in [29]
In authors of [29] applied similar approach as applied by [24] and authors [24]
shows low design overhead, higher robustness to radiation effects in present of
SEMEs. Fig. 10(b) shows proposed 13-T RHM in [29].
2.2.11. Device based SEU Clamping Circuit
Equation (2) shows current produced by strike of particles on sensitive node with the
help of equation method proposed by [30]. The idea of this method is used same gate
with higher threshold than normal gate in circuit. Consider the circuit in Fig. 11;
assume that out node is at logic 0.
When energetic particle strike on out node, it causes a rising pulse on out node but
out node, voltage does not increase because protecting gate is at -0.4V.When the
voltage at protecting node outp starts to rise, the nMOS device turns on, thus
clamping the protected node.
If the particle strike on outp than voltage at protected node is unchanged because
protected node initially at much lower voltage (-0.4V) and as the voltage at protecting
node increases, the clamping nMOS device turns off and if voltage of the protecting
node rises above 0.4V than the clamping pMOS device turns on.
In a similar manner, the clamping pMOS device helps to protect a gate from
falling pulse due to a radiation event.
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A Survey of Radiation Hardening by Design (RHBD) Techniques For Electronic Systems for
Space Application
3. CONCLUSIONS
Considering the present need of low power, low cost radiation hardened systems;
RHBD will be helpful to resolve the issue. In this regard, this paper has tried to cover
the entire spectrum of various approaches for Radiation Hardening Design level. As
radiation hardening by process is a costly approach, one would prefer to focus on
Radiation Hardening by Design.
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