5.

Sequential Logic
6.004x Computation Structures
Part 1 Digital Circuits
Copyright 2015 MIT EECS

6.004 Computation Structures

L5: Sequential Logic, Slide #1

Something We Cant Build (Yet)

What if you were given the following design specification:
#1

button

#2

When the button is pushed:

1) Turn the light on if it is off
2) Turn the light off if it is on

light

The light should change

state within a second
of the button press

What makes this device different

from those weve discussed before?
1.State i.e., the device has memory
2.The output was changed by a input
event (pushing a button) rather
than an input level
6.004 Computation Structures

L5: Sequential Logic, Slide #2

Digital State: What Wed Like to Build

Sequence of values
Trigger
periodically

Memory
Device
LOAD

Input

Current
State

Combinational
Logic

Next
State

Output

Plan: Build a Sequential Circuit with stored digital STATE

Memory stores CURRENT state, produced at output
Combinational Logic computes

NEXT state (from input, current state)

OUTPUT bits (from input, current state)

Needed:
Loadable
Memory

State changes on LOAD control input

6.004 Computation Structures

L5: Sequential Logic, Slide #3

Memory: Using Capacitors

Weve chosen to encode information using voltages and
we know from physics that we can store a voltage as
charge on a capacitor:
Pros:
word line

compact low cost/bit

(on BIG memories)

bit line
NFET serves as
access switch

Cons:

VREF

To write:
Drive bit line, turn on access fet,
force storage cap to new voltage
To read:
precharge bit line, turn on access fet,
detect (small) change in bit line voltage
6.004 Computation Structures

complex interface
stable? (noise, )
it leaks! refresh
Suppose we use
feedback to
refresh
continuously?

L5: Sequential Logic, Slide #4

Memory: Using Feedback

IDEA: use positive feedback to maintain storage indefinitely.
Our logic gates are built to restore marginal signal levels, so
noise shouldnt be a problem!

1
0

0
1

VOUT

VIN
VTC for
inverter pair

VOUT

Feedback constraint:
VIN = VOUT

Not affected
by noise

Three solutions:
two end-points are stable
middle point is metastable
VIN

6.004 Computation Structures

1
0

Result: a bistable
storage element

Well get back to this!

L5: Sequential Logic, Slide #5

Settable Memory Element

Its easy to build a settable storage element (called a
latch) using a lenient MUX:
Heres a feedback path,
so its no longer a
combinational circuit.

D0

Q
Y
D
B

D1
S

S
G

state signal
appears as both
input and output

G D Q

0
1
---

0
1
0
1

0
0
1
1

--0
1

Q stable
Q follows D

D: data input
G: gate input
Q: state output

6.004 Computation Structures

L5: Sequential Logic, Slide #6

New Device: D Latch

G=1:
Q follows D
Q

Circuit:

V1

Q
D Q

V1
TPD

V2
TPD

G=1: Q Follows D, independently of Q

G=0: Q Holds stable Q, independently of D
6.004 Computation Structures

V2

Schematic
Symbol:

G=0:
Q holds

BUT A change in D
or G contaminates
Q, hence Q how
can this possibly
work?

L5: Sequential Logic, Slide #7

A Plea for Lenience

Q
D

0
1

1.
D

V1

Then output valid when

1. G=1, D stable for TPD,
independently of Q; or
2. Q=D stable for TPD ,
independently of G; or

3.

V2

G
Q

V1
TPD

Assume LENIENT Mux,

propagation delay of TPD

2.

V2
TPD

TPD

Does lenience guarantee a

working latch?
What if D and G
change at about
the same time

3. G=0, Q stable for TPD ,

independently of D
6.004 Computation Structures

L5: Sequential Logic, Slide #8

With a Little Discipline

D Stable

Q
A

To reliably latch V2:

Apply V2 to D, holding G=1
After TPD, V2 appears at Q=Q
After another TPD, Q & D
both valid for TPD; will hold
Q=V2 independently of G

V2

G
Q

V2
TPDTPD

TPD

TSETUP THOLD

Dynamic Discipline for our latch:

Set G=0, while Q & D hold Q=D

TSETUP = 2TPD: interval prior to G

transition for which D must
be stable & valid

After another TPD, G=0 and

Q are sufficient to hold
Q=V2 independently of D

THOLD = TPD: interval following G

transition for which D must
be stable & valid

6.004 Computation Structures

L5: Sequential Logic, Slide #9

Lets Try It Out!

New
State

D Q
G

Current
State

Combinational
Logic

Input

Output

When G=1, latch is Transparent

Looks like a stupid

approach to me

provides a combinational path from D to Q.

Cant work without tricky timing constraints on G=1
pulse:
Must fit within contamination delay of logic
Must accommodate latch setup, hold times
Want to signal an INSTANT, not an INTERVAL
6.004 Computation Structures

L5: Sequential Logic, Slide #10

Flakey Control Systems

Sequence
of values
Gate closed

6.004 Computation Structures

How do we
ensure
only one
car gets
through?

Gate open

L5: Sequential Logic, Slide #11

Solution: Escapement Strategy (2 gates)

Gate 2

Gate 2

Gate 1

Gate 1

Sequence
of values
Gate 1: open
Gate 2: closed
6.004 Computation Structures

Key: at no
time is there a
path through
both gates

Gate 1: closed
Gate 2: open
L5: Sequential Logic, Slide #12

(Edge-Triggered) D Register

What does
that one do?

0
0
1
1

CLK

The gate of this

latch is open
when the clock
is low

D Q

D Q

master

slave

The gate of this

latch is open
when the clock
is high

Observations:
only one latch transparent at any time:
master closed when slave is open
slave closed when master is open
no combinational path through register
(the feedback path in one of the master or slave latches is always active)

6.004 Computation Structures

L5: Sequential Logic, Slide #13

D-Register Waveforms
D

D Q

D Q

master

slave

D Q

CLK

CLK

D
CLK

Q
master closed
slave open
6.004 Computation Structures

master open
slave closed
L5: Sequential Logic, Slide #14

Um, about that hold time

D

D Q

D Q

master

slave

CLK

D
CLK
The masters contamination
delay must meet the hold time
of the slave: tCD,M tH,S

Slave latch is closing must meet setup/hold times

but master latch is opening so may change
6.004 Computation Structures

L5: Sequential Logic, Slide #15

D-Register Timing 1
tPD
tCD
D

D Q

CLK

Q
CLK
D

tPD: maximum propagation delay, CLKQ

tCD: minimum contamination delay, CLKQ

tSETUP tHOLD

tSETUP: setup time

guarantee that D has propagated through feedback path before master

closes

tHOLD: hold time

guarantee master is closed and data is stable before allowing D to

change

6.004 Computation Structures

L5: Sequential Logic, Slide #16

Single-clock Synchronous Circuits

Does that
symbol
register?

Well use registers in a highly constrained way to build

digital systems:
Single-clock Synchronous Discipline
No combinational cycles
Single periodic clock signal
shared among all clocked
devices
Only care about value of
register data inputs just before
rising edge of clock
Period greater than every
combinational delay + setup time
Change saved state after
noise-inducing logic
transitions have stopped!

6.004 Computation Structures

L5: Sequential Logic, Slide #17

Timing in a Single-clock System

D Q

QR1

D Q

reg1

reg2

CLK

t1
CLK
QR1

tCD,reg1
tCD, L

t2

what happens if theres no

combinational logic between
two registers?

tPD,reg1

tPD, L

Questions for register-based

designs:
how much time for useful work
(i.e. for combinational logic
delay)?

what happens if CLK signal

doesnt arrive at the two
registers at exactly the
same time (a phenomenon
tCLK known as clock skew)?

tSETUP,reg2

t1 = tCD,reg1 + tCD,L tHOLD,reg2

t2 = tPD,reg1 + tPD,L + tSETUP,reg2
6.004 Computation Structures

L5: Sequential Logic, Slide #18

Model: Discrete Time

State updated every rising clock edge

DREG
Memory

Current
State

Clock

Next
State

Combinational
Logic

Input

Output

Active Clock Edges punctuate time -- Discrete Clock periods

Sequences of states
Simple rules eg truth tables relating outputs to
inputs and the current state)
ABSTRACTION: Finite State Machines (next lecture!)
6.004 Computation Structures

L5: Sequential Logic, Slide #19

Sequential Circuit Timing

tCD,R = 1ns
tPD,R = 3ns
tS,R = 2ns
tH,R = 2ns

Next
State
Current
State

Clock

Combinational
Logic
tCD,L = ?
tPD,L = 5ns

Input

Questions:
Constraints on tCD

tCD,R (1 ns) + tCD,L(?) tH,R(2 ns)

for the logic? tCD,L 1 ns

Minimum clock period?

Setup, Hold times for Inputs?
tS,INPUT = tPD,L + tS,R = 7 nS
tH,INPUT = tH,R - tCD,L= 1 nS
6.004 Computation Structures

Output

tCLK tPD,R+tPD,L+ tS,R = 10nS

tPD,L

Input
Next State
clk

tCD,L
tS,R

tH,R
L5: Sequential Logic, Slide #20

Summary
Basic memory elements:
Feedback, detailed analysis
=> basic level-sensitive
devices (eg, latch)
2 Latches => Register
Dynamic Discipline:
constraints on input timing
Synchronous 1-clock logic:
Simple rules for sequential
circuits
Yields clocked circuit with TS,
TH constraints on input timing

Finite State Machines

Next Lecture Topic!

6.004 Computation Structures

>tS

>tH

D
Clk
Q
>tCD
<tPD

In

DQ

Combinational
logic

DQ

Out

Clk

L5: Sequential Logic, Slide #21