EXPER

RIMENT NO
O. 3
Aim: Siziing of an Inveerter chain to reduce delay
Theory:

The
T general deesign problem
m is to drive a large capacittive load withhout excessivee delay, area aand
power req
quirements. A large inverteer is required to drive the l arge capacitivve load at thee final stage.
Because the
t gate capaccitance of an inverter
i
is pro
oportional to its size, a medium size invverter is requiired
to drive th
he large inverrter. Thereforee, an obvious solution is too use a chain of successiveely larger inveerters
so that alll inverters in the
t chain driv
ve appropriatee loads and doo not cause exxcessive delayy. The circuitt
structure is
i shown in ab
bove figure. Intuitively,
I
if the chain is ttoo long, the ssignal delay w
will be too larrge
due to thee intrinsic delaay of each inv
verter. Howev
ver, if the chaain is too shorrt, the output signal slope w
will
be very weak
w
with long
g rise and falll times, which
h again cause long delay. T
The challengee is to decide the
length of the chain, i.e.., how many inverters,
i
and
d the size of eaach inverter.
We
W assume thaat the P and N transistor sizze ratio of alll inverters aree fixed. Typiccally, they aree
adjusted such
s
that the rise
r and fall tiimes are equaal. This allow
ws us to use a ssingle numbeer to express tthe
size of an inverter. To simplify the design
d
analyssis, we often ffix the stage rratio of the innverter chain tto a
constant factor
f
K. Thiss means that th
he first invertter has a unit size (typicallyy the smallesst size), the seecond
has size K,
K the third haas size , etcc.
Using
U
a very simple RC dellay model, thee delay of an inverter is dirrectly proporttional to the lload it
drives. In other words, if an inverterr drives K oth
her inverters oof the same siize, the delay through the
inverter iss Kd where d is the intrinsiic delay of thee inverter undder a single looad. Assume tthat d is identtical
for all inv
verters in our inverter chain
n, the delay D through the chain is

ln
n

ln

ln
a constants and the total chain delay D depends onn the stage ratiio K. The graaph of
and d are

is sho
own in figure. The delay D is minimum when K = e = 2.71, the naatural logarithhm base.

Schematic Diagram:

VDD

M3

M5

M0

Vin
Vin

M7

M9

gnd

Vout

M2

M4

M1

M6

M8

C0
model=capacitor
c=50f

val0=0.0
val1=1.8

gnd

gnd

gnd

Simulation Results:
To obtain K for minimum delay of the inverter chain using SPICE, we consider 5 inverters chain
and we progressively increase the stage ratio K from 1 to 10 and observe rise time for each K. We
observe that the rise time is minimum for K=3.1 and respective minimum rise time is 29.2 ps.