R.

W. Erickson
Department of Electrical, Computer, and Energy Engineering
University of Colorado, Boulder

Introduction to Inverters
Robert W. Erickson
Department of Electrical, Computer, and Energy Engineering
University of Colorado, Boulder

Single-Phase Inverter Approaches

The Solar Application
Single-Phase Solar Inverters
Microinverters

A Basic Single-Phase
Inverter Circuit
Two ways to generate
a PWM sinusoid
DC power source

H-bridge inverter circuit

(a) Operate left and right sides

AC load
with same (complementary)
L-C filter may or may not be present
gate drive signals
resistive load illustrated; actual AC loads are more complex
v(t) = (2d(t) 1)Simple
Vg
Even in the single-phase case, there are multiple ways to control the
switches
Two-level waveform
Applications:
Some three-phase applications:
vac(t)
Uninterruptable
power supply (UPS)
AC motor drives
(b) PWM one side, whileother
AC motor drive
Inverters for wind and solar
side switches at 60 Hz
Fluorescent lamp driver
Electric
vehicles
v(t) = d(t) Vg Solar power inverter
t
DC transmission line stations
Automobile AC power inverter
6
Three-level waveform
Power Electronics Lab

Modied
Sine-Wave
Inverter
The
Modified
Sine
Wave
Inverter
Modied Sine-Wave Inverter
vac(t)
H-bridge switches at the
vac(t) has a
output
frequency
vac(t) has a + VHVDC
rectangular
Waveform is highly
rectangular
waveformwith
nonsinusoidal,
waveform
significant harmonics
Inverter
transistors
Some ac loads can
Inverter
switch
60 Hz, transistors
VHVDC
tolerate
thisat
waveform,
switch at 60 Hz,
T =cannot
8.33 msec
others
T = 8.33 msec
Inexpensive, efficient

vac(t)
+DT/2
VHVDC

DT/2

T/2
T/2
VHVDC

Choose VHVDC larger than

Choose VHVDC larger than
desired Vac,RMS
desired Vac,RMS
Can regulate value of
Can regulate
Vac,RMS by variation
of D value of
Vac,RMS by variation of D
Waveform is highly
Waveform
is highly
nonsinusoidal,
with
nonsinusoidal,
Standalone inverter: inverter drives a passive load, and regulates
the voltage
supplied to with
signicant
harmonics
the load
signicant harmonics

RMS value of vac(t) is:

value
of vac
is:cycle D:
Control of ac rmsRMS
voltage
by control
of(t)
duty

Power Electronics Lab

Power Electronics Lab

4
4

Two
ways
to
generate
a
PWM
s
Two
ways
to
generate
a
PWM
sinusoid
ways to
to generate
generate aa PWM
PWM sinusoid
sinusoid
oo ways
The True Sine Wave
Inverter
Two
ways to generate a PWM si
Use of PWM with high
frequency switching to produce
a sinusoidal ac voltage having
low harmonic content. Typically
an L-C filter is included to meet
EMI requirements

left and
and right
right sides
sides
left
me (complementary)
(complementary)
me
ve signals
signals
ve
(2d(t) 1)
1) VVg
== (2d(t)
g

v(t) = (2d(t) 1) Vg
Two-level waveform

Two-level waveform
waveform
Two-level

ne side,
side, while
while other
other
ne
tches at
at 60
60 Hz
Hz
tches
d(t) VVg
== d(t)

bb

(a)
Switches
1a and
are right
drivensides
by the same
Operate
left1band
gate with
drive same
signal,(complementary)
and conduct during d
(a)
Operate left and right sides
interval
gate drive signals
with
Switchessame
2a and(complementary)
2b are driven by the
v(t) = (2d(t) 1) Vg
complement
andsignals
conduct during d interval
gate drive

(a) Operate left and right sides

with same (complementary)
gate drive signals
v(t) = (2d(t) 1) Vg

For positive half cycle, switch 1b is on.

Switches 1a and 2a operate with PWM vac(t)
(b)
For negative
halfside,
cycle,while
switchother
2a is on.
PWM one
vac(t)
Switches
and 1b operate
with PWM
side 2b
switches
at 60 Hz

vac(t)

v (t)
vacac(t)

(b) PWM one side, while other

side switches at 60 Hz
v(t) = d(t) Vg

Power Electronics
LabThree-level
6
6

waveform
Three-level waveform

Two-level wav

Two-level wav

(b) PWM one side, while other

v(t) = d(t)
Vg Hz
t
side switches
at 60
Alternate: b switches
switch
v(t) = d(t)
Vg at the line

t
t
6

frequency, and a switches operate with PWM

Power Electronics
Lab
Three-level
Three-level
exhibitswaveform
reduced switching loss
Power Electronics Lab

6
6

Three-level w

Three-level w

Standalone vs. grid-tied applications

Standalone inverter:
Inverter regulates ac voltage

Grid-tied inverter:
Inverter regulates its ac current
Inverter

Inverter

Vdc

AC
load

dinv

Vdc

vac(t)

PWM

PWM

iac(t)

Phase-locked loop

H3

H3

Gc3(s)

Gc3(s)

+
vref(t) Sinusoidal
reference

vac(t)

dinv

vac(t)

iref(t)
Vcontrol

Sinusoid
unit amplitude
phase-locked to vac

Reactive power
For a standalone application, the inverter must be capable of supplying
whatever current waveform is demanded by the ac load
Reactive load, in which current is phase-shifted relative to voltage
Distorted current
In most grid-tied applications, the inverter supplies a low-THD current
waveform to the grid, with power factor very close to unity.
Improved efficiency
This opens the possibility of simpler converter topologies using singlequadrant switches

The grid-tied solar inverter application

AC voltage is determined by the utility system (infinite bus)
Power is determined by the solar array
Inverter produces ac current synchronized to the utility, with amplitude dependent on
array power
A residential solar array system

Functions performed by the inverter

Maximum power point
tracking: operate the solar
array at the voltage that
maximizes generated power
120 Hz energy storage: the
difference between the constant
power supplied by the array and
the 120 Hz pulsating power
flowing into the utility is
supplied/stored in the capacitor

pac(t)

AC current control: ac line

current must meet harmonic
requirements (THD < 5%), with
unity power factor
Array voltage, capacitor voltage, and
ac line voltage are independent

Ppv

vc(t)

System resembles PWM rectifier

system, but with power flow reversed
t

An Inverter System
vpv(t)

vbus(t)

DC-DC

Inverter

EMI

PV

vac(t)

H1

vac(t)

dinv

PWM

PWM
ibus

Gc3(s)

vbus(t)

iac(t)

Phase-locked loop

H3
Gc3(s)

MPPT

vpv(t)

Vref-pv

H2

iref(t)
Vref-bus

Gc2(s)

Sinusoid
unit amplitude
phase-locked to vac

Standards
IEEE 1547: standard for connecting a renewable energy source to the utility grid
Current harmonic limit (THD < 5%)
Anti-islanding (detect loss of grid, shut down within 1 sec)
Disconnection when grid frequency or grid voltage is out of bounds
National Electric Code
UL 1741
Weighted Efficiency standards: California Energy Commission (CEC)
Power level,
% of rated

Weight

100%

0.05

75%

0.53

50%

0.21

30%

0.12

20%

0.05

10%

0.04

Provides a way to compare products

of different companies
Weightings reflect typical distribution
of array power experienced in
California

Microinverters
One inverter per panel
Mounted on or near the panelon roof
MPPT on per-panel basis
Conventional AC wiring reduces
Balance-of-system cost
Straightforward expandability
Reliability? Efficiency?
Rated temperature?

Ascension Tech. microinverter, 1998

Enphase
microinverter,
2008

Elements of a Microinverter System

Pdc
i
+

PV
Cells
i
v

v(t)
i(t)

Pac

Energy
storage

DC-DC
Converter

DC-AC
Inverter

iac
+

Microinverter
power train:
DC-DC converter
(high boost ratio)

vcap

vac

Pdc

Pac

vac(t)
iac(t)

Central box
Microinverter

Microinverter

Power stage
MPPT Current
control
Anti-islanding

Power stage
MPPT Current
control
Anti-islanding

Roof
AC

Transient
protection

AC
utility
AC
disconnect

Communications
Computer

Smart grid

Energy storage
capacitor
Inverter

Rooftop system
Microinverters
include most or all
of grid interface
control
Central box

boosts the low PV input voltage to a higher voltage. The inverter stage generates the AC current that is injected to the
AC line. Despite various new topologies that have been demonstrated in recent literature [5], the typical low-cost
micro-inverter is still designed either as a full-bridge stage, or as a buck stage with an unfolder stage. The unfolder

Microinverter Approaches

stage, if present, switches at the zero-crossings of the line voltage to convert the rectified sinusoid at the buck output
to a full sinusoid on the AC line.

H-bridge inverter

Buck converter plus unfolder

Unfolder: similar to bridge
rectifier, but power flows in
reverse
Fig. 1. Common micro-inverter power stages. (a) Full bridge. (b) Buck stage with an unfolder
stage. direction. Implemented
using transistors that switch at
ac line frequency
An illustration of the Boundary Conduction Mode (BCM) waveform is shown in Fig. 2. Although it is softswitching, and operates with low RMS current, a disadvantage of BCM is its high average switching frequency, which
causes high switching losses. As demonstrated by equation (1), the BCM waveform has the highest switching

Inverter sinewave synthesis approaches

We can employ any of the approaches we have already discussed for PWM
rectifier systems:
Average current control
Peak current control
Boundary conduction mode
Hysteretic control
Discontinuous conduction mode control
Cycle-by-cycle control
(and there are a few we didnt discuss, most notably harmonic elimination, that
could be employed for either rectifiers or inverters)

lowest possible peak current in DCM, and as a result the switching frequency in BCM is maximal. Equation (1) also
predicts that the switching frequency of BCM increases at low output powers, creating a switching frequency profile
that causes disproportional switching losses at low powers. This is demonstrated by the last expression in equation (1)

Synthesizing a Sinusoidal Current:

results in a higher switching frequency, so the switching frequency and switching losses in BCM substantially increase
Boundary Conduction Mode (BCM)
at low voltages and low powers.
for which the power-factor is unity and the switching frequency is proportional to Rout. A lower output voltage vout(t)

Inductor current waveform, BCM

Fig. 2. Illustration of the inductor current in BCM, showing soft switching transitions (ZVS, ZCS) and the variations in switching
frequency over the line cycle.

The switching frequencies in DCM and BCM are given by:

DCM:

fs t

vout t
2 L iout t

BCM:

fs t

vout t
2 L iout t

v t
1 out
vdc t
1

2iout t
i pk t

vout t
vdc t

Loss components at different solar

irradiance levels, BCM
(300 W, 240 Vac example)
(1)

BCM with unity power factor :

fs t
Fig.

v t
Rout
1 out
2L
vdc t

, where Rout

vout t
iout t

Fig. 3. Distribution of losses in BCM. The vertical bars represent average losses over an AC line cycle. The losses are shown in percent
the average
AC outputat
power.
Switching
losses
dominateThe
at low
powers.
3 shows how the totalrelative
loss into BCM
distributes
various
output
powers.
losses
in this figure are averaged

over a line cycle, and are shown in percent relative to the cycle averaged output power. The total loss is composed of

BCM waveform. The DC operating points are selected with constant ratio of voltage and current vout/iout = Rout, and
thus reside on the same output sinusoid. The efficiency is computed according to the calibrated loss model presented
in section IV, with conditions as follows: Rout = 215.1 , average AC power of 225 W, bus voltage of vbus = 425 V,
and an inductor of 300H built on a PQ 26/20 core. Each curve is label by its output power pout = voutiout, which is

Discontinuous
conduction
mode
(DCM)
given in percent relative to the maximal instantaneous output power of 450 W.

Higher conduction loss

program
Lower that
switching loss
To find the optimal values of the inductance L and magnetic flux density Bmax, we used a computer
A net improvement in
numerically scanned the weighted efficiency of every combination of these two parameters. The program runs over
CEC efficiency
each output power level, and over single DC operating points in the output sinusoid, and computes the efficiency at

each operating point, using the calibrated loss model. The resulting efficiency data is averaged according to the CEC
efficiency formula (see section V). Typical results of this simulation are shown in Fig. 10, for a PQ 26/20 magnetic
core, and conditions as detailed in Table I.

CEC efficiency [%]

Fig. 4. By increasing the peak current 99.2

in DCM, the switching frequency is reduced, while the average inductor current (iout) is unchanged.
99
98.8
98.6
98.4
98.2
98
97.8
97.6
97.4

Weighted efficiency vs. inductor

size, DCM vs. BCM
300 W, 240 Vac example

constant peak current

BCM
250

350

450

550

650

750

850

inductance [H]
Fig. 10. Weighted CEC efficiency with a PQ 26/20 magnetic core, for a BCM controller and the proposed constant peak current
controller.

200
400
DC output power pout [W]

600

Fig. 14. Efficiency measurements at DC operating points, for various average AC powers

Fig. 12.
Inverter
waveforms
at efficiency
a DC operating
Ch1 (yellow)
cycle-by-cycle
capacitor over
voltagea vline
int(t) , Ch2 (blue) auxiliary
At each
power
level,
the AC
is point.
computed
by averaging
theintegration
DC efficiencies
cycle. The results

are

Measured Results: 300 W Microinverter Prototype

winding voltage sensor, at comparator output, Ch4 (green) inductor current iL(t). Conditions: Vdc= 426.8 V, Idc= 0.98 A, vout= 330.1 V, iout=
A.
again averaged by the CEC weighted average formula 1.259
to obtain
the overall CEC efficiency. The AC efficiency is

computed by equation (9), and the results are summarized in Table II.
/ ac

AC line voltage

pout t dt
AC efficiency

0
AC

/ ac

pout t
DC

pout t

where pout t

Pac sin 2

ac

(9)
Current reference

dt

Filtered inverter current

In this equation, Pac is the average AC power, pout(t) is the output power at a DC operating point, and DC(pout) is the

inductor current
efficiency at those operating points, as shown in Fig. 14. The weighted CEC efficiency is found toInstantaneous
be 99.15 %.

Fig. 13. Inverter waveforms over a line cycle. Ch1 (yellow) AC line voltage sensor, Ch2 (blue) AC current iac(t), Ch3 (magenta) reference
signal iref(t), Ch4 (green) inductor current
iL(t). Conditions:
Vdc= 425 V, Idc= 0.462 A, Rload=253
TABLE
II

CEC Efficiency
CEC
Average
average AC
average AC
power
weight
loss over
power P
The efficiency of the inverter
points.efficiency
These tests are done with a power supply
levelis measured at static DCac operating
AC cycle
100resistor
%
0.05
300 W
2.6 W
99.13 %
at the input and a variable load
(R
load) at the output. To increase the accuracy of the measurements, the meters
75 %
0.53
225 W
1.97 W
99.12 %
at the input and output are filtered
The1.26
efficiency
results
50 % by large
0.21 EMI inductors.
150 W
W
99.16
% are shown in Fig. 14. The various
30 %
0.12
90 W
0.7 W
99.22 %
curves in the figure correspond
to
tests
with
different
average
AC
powers
(P
ac). At each such test the load resistor is
20 %
0.05
60 W
0.45 W
99.24
%
10 instantaneous
%
0.04 output
30power
W
0.24 W in the99.2
% 0 2Pac.
set to Rload=Vac,rms2/Pac, and the
is scanned
range

Overall weighted CEC efficiency = 99.15 %

Development of Electrical Model

of the Photovoltaic Cell, slide 1
Photogeneration
Semiconductor material absorbs photons and
converts into hole-electron pairs if
Photon energy h > Egap
(*)
Energy in excess of Egap is converted to
heat
Photo-generated current I0 is proportional to
number of absorbed photons satisfying (*)

photon

Charge separation
Electric eld created by diode structure separates holes and electrons
Open circuit voltage Voc depends on diode characteristic, Voc < Egap/q

Development of Electrical Model

of the Photovoltaic Cell, slide 2

Current source I0 models photo-generated current

I0 is proportional to the solar irradiance, also called the insolation:
I0 = k (solar irradiance)
Solar irradiance is measured in W/m^2

Development of Electrical Model

of the Photovoltaic Cell, slide 3

Diode models pn junction

Diode iv characteristic follows classical
exponential diode equation:
Id = Idss (eLVd 1)
The diode current Id causes the terminal
current Ipv to be less than or equal to the
photo-generated current I0.

Development of Electrical Model

of the Photovoltaic Cell, slide 4

Modeling nonidealities:
R1 : defects and other
leakage current mechanisms
R2 : contact resistance and
other series resistances

Cell characteristic
Cell output power is Ppv = IpvVpv
At the maximum power point
(MPP):
Vpv = Vmp
Ipv = Imp
At the short circuit point:
Ipv = Isc = I0
Ppv = 0
At the open circuit point:
Vpv = Voc
Ppv = 0

Maximum Power Point Tracking

Automatically operate the PV panel at its
maximum power point
Some possible MPPT algorithms:
Perturb and observe
Periodic scan

I-V curve
with partial
shading

Newton s method, or related hillclimbing algorithms

What is the control variable? Where is
the power measured?

Power vs. voltage

Example MPPT: Perturb and Observe

A well-known approach"

Works well if properly tuned"

When not well tuned, maximum power

point tracker (MPPT) is slow and can
get confused by rapid changes in
operating point"

A common choice: control is switch

duty cycle"

Basic algorithm!
!
Measure power"
Loop:"
Perturb the operating point in
some direction"
Wait for system to settle"
Measure power"
Did the power increase?"
Yes: retain direction for next
perturbation"
N: reverse direction for next
perturbation"
Repeat"

Control Issues:
MPPT by Perturb-and-Observe

,
,

Measured power vs. commanded

PV voltage

Key elements of digital controller

Find PV voltage that maximizes power output

Switching converter is high noise environment
This noise is partly correlated to the control,
and hence isnt entirely random
The highly-ltered dc control characteristic
exhibits many small peaks (traps), where
P&O algorithm gets stuck
More noise makes P&O work better!

Magnied view

Typical experimental data

()

()

Perturb-and-observe step time of 15 msec

Perturb-and-observe algorithm may take minutes to nd max power
Weather can change in seconds
Improved algorithm achieves max power in seconds
Adaptive algorithm nds max power quickly, then reduces jitter size to
improve equilibrium MPPT accuracy