Single-Phase Converter Systems Containing Ideal Rectifiers

R.
W. Erickson
Department of Electrical, Computer, and Energy Engineering
University of Colorado, Boulder
18.4 Single-phase converter systems

containing ideal rectifiers
It is usually desired that the output voltage v(t) be regulated with

high accuracy, using a wide-bandwidth feedback loop
For a given constant load characteristic, the instantaneous load

current and power are then also constant:
pload (t) = v(t)i(t) = VI
The instantaneous input power of a single-phase ideal rectifier is

not constant:
pac(t) = vg(t)i g(t)
with
so
vg(t) = VM sin (t)
vg(t)
i g(t) =
Re
2
V 2M
V
pac(t) =
sin 2 t = M 1 cos 2t
Re
2Re
Fundamentals of Power Electronics
51
Chapter 18: PWM Rectifiers
Power flow in single-phase ideal rectifier system
Ideal rectifier is lossless, and contains no internal energy storage.
Hence instantaneous input and output powers must be equal
An energy storage element must be added
Capacitor energy storage: instantaneous power flowing into

capacitor is equal to difference between input and output powers:
d EC(t)
pC(t) =
=
dt
1
2
Cv 2C(t)
dt
= pac(t) pload(t)
Energy storage capacitor voltage must be allowed to vary, in

accordance with this equation
52
Capacitor energy storage in 1 system

pac(t)
Pload
vc(t)
1
2
Cv 2C(t)
dt
= pac(t) pload(t)
t
53
Single-phase system with internal energy storage
iac(t)
vac(t)
pload(t) = VI = Pload
Ideal rectifier (LFR) i (t)

2
ig(t)
vg(t)
pac(t)T
+
s
Re
vC(t)
Dcdc
converter
i(t)
v(t)
load
Energy storage
capacitor
Energy storage capacitor

voltage vC(t) must be
independent of input and
output voltage waveforms, so
that it can vary according to
1
2
Cv 2C(t)
dt
This system is capable of
= pac(t) pload(t)
54
Wide-bandwidth control of
output voltage
Wide-bandwidth control of
input current waveform
Internal independent energy

storage
Hold up time
Internal energy storage allows the system to function in other
situations where the instantaneous input and output powers differ.
A common example: continue to supply load power in spite of failure

of ac line for short periods of time.
Hold up time: the duration which the dc output voltage v(t) remains
regulated after vac(t) has become zero
A typical hold-up time requirement: supply load for one complete
missing ac line cycle, or 20 msec in a 50 Hz system
During the hold-up time, the load power is supplied entirely by the
energy storage capacitor
55
Energy storage element

Instead of a capacitor, and inductor or higher-order LC network could
store the necessary energy.
But, inductors are not good energy-storage elements

Example
100 V 100 F capacitor
100 A 100 H inductor
each store 1 Joule of energy
But the capacitor is considerably smaller, lighter, and less
expensive
So a single big capacitor is the best solution
56
Inrush current
A problem caused by the large energy storage capacitor: the large
inrush current observed during system startup, necessary to charge
the capacitor to its equilibrium value.
Boost converter is not capable of controlling this inrush current.
Even with d = 0, a large current flows through the boost converter
diode to the capacitor, as long as v(t) < vg(t).
Additional circuitry is needed to limit the magnitude of this inrush
current.
Converters having buck-boost characteristics are capable of
controlling the inrush current. Unfortunately, these converters exhibit
higher transistor stresses.
57
Universal input
The capability to operate from the ac line voltages and frequencies
found everywhere in the world:
50Hz and 60Hz
Nominal rms line voltages of 100V to 260V:
100V, 110V, 115V, 120V, 132V, 200V, 220V, 230V, 240V, 260V
Regardless of the input voltage and frequency, the near-ideal rectifier
produces a constant nominal dc output voltage. With a boost
converter, this voltage is 380 or 400V.
58
Low-frequency model of dc-dc converter

Dc-dc converter produces well-regulated dc load voltage V.
Load therefore draws constant current I.
Load power is therefore the constant value Pload = VI.
To the extent that dc-dc converter losses can be neglected, then dc-dc
converter input power is Pload , regardless of capacitor voltage vc(t).
Dc-dc converter input port behaves as a power sink. A low frequency
converter model is
p (t) = VI = P
i (t)
load
+
C
vC(t)
+
Pload V +
Energy storage
capacitor
59
load
i(t)
v(t) load
Dc-dc
converter
Low-frequency energy storage process, 1 system

A complete low-frequency system model:
iac(t)
vac(t)
i2(t)
ig(t)
+
vg(t)
pac(t)Ts
Re
vC(t)
+
Pload V +
Ideal rectifier (LFR)
Energy storage
capacitor
i(t)
v(t) load
Dc-dc
converter
Difference between rectifier output power and dc-dc converter

input power flows into capacitor
In equilibrium, average rectifier and load powers must be equal
But the system contains no mechanism to accomplish this
An additional feeback loop is necessary, to adjust Re such that the

rectifier average power is equal to the load power
60
Obtaining average power balance
iac(t)
vac(t)
i2(t)
ig(t)
+
vg(t)
pac(t)Ts
Re
vC(t)
+
Pload V +
v(t) load
Energy storage
capacitor
i(t)
Dc-dc
converter
If the load power exceeds the average rectifier power, then there is a
net discharge in capacitor energy and voltage over one ac line cycle.
There is a net increase in capacitor charge when the reverse is true.
This suggests that rectifier and load powers can be balanced by
regulating the energy storage capacitor voltage.
61
A complete 1 system
containing three feedback loops
Boost converter
i2(t)
+
ig(t)
+
iac(t)
vac(t)
D1
vg(t)
Q1
vC(t)
vcontrol(t)
vg(t)
Multiplier
i(t)
DCDC
Converter
Load v(t)
ig(t)
Rs
d(t)
PWM
v(t)
va(t)
vref1(t)
= kxvg(t)vcontrol(t)
v (t)
+ err
Gc(s)
Compensator
and modulator
+ vref3
Compensator
Wide-bandwidth output voltage controller
Wide-bandwidth input current controller

vC(t)
Compensator
+ vref2
Low-bandwidth energy-storage capacitor voltage controller
62
Bandwidth of capacitor voltage loop
The energy-storage-capacitor voltage feedback loop causes the

dc component of vc(t) to be equal to some reference value
Average rectifier power is controlled by variation of Re.
Re must not vary too quickly; otherwise, ac line current harmonics

are generated
Extreme limit: loop has infinite bandwidth, and vc(t) is perfectly

regulated to be equal to a constant reference value
Energy storage capacitor voltage then does not change, and
this capacitor does not store or release energy
Instantaneous load and ac line powers are then equal
Input current becomes
i ac(t) =
pac(t)
p (t)
Pload
= load
=
vac(t)
vac(t)
VM sin t
63
Input current waveform, extreme limit

i ac(t) =
pac(t)
p (t)
Pload
= load
=
vac(t)
vac(t)
VM sin t
THD
Power factor 0
vac(t)
iac(t)
64
So bandwidth of
capacitor voltage
loop must be
limited, and THD
increases rapidly
with increasing
bandwidth
18.4.2 Modeling the outer low-bandwidth

control system
This loop maintains power balance, stabilizing the rectifier output
voltage against variations in load power, ac line voltage, and
component values
The loop must be slow, to avoid introducing variations in Re at the
harmonics of the ac line frequency
Objective of our modeling efforts: low-frequency small-signal model
that predicts transfer functions at frequencies below the ac line
frequency
65
Large signal model

averaged over switching period Ts
ig(t)Ts
p(t)T
vg(t)T
i2(t)T
+
s
Re (vcontrol )
v(t)T
Load
ac
input
dc
output
vcontrol
Ideal rectifier model, assuming that inner wide-bandwidth loop

operates ideally
High-frequency switching harmonics are removed via averaging
Ac line-frequency harmonics are included in model
Nonlinear and time-varying
66
Predictions of large-signal model
If the input voltage is

vg(t) = 2 vg,rms sin t
ig(t)Ts
p(t)T
vg(t)T
Re (vcontrol )
i2(t)T
+
s
v(t)T
Then the
instantaneous power
is:
vg(t)
ac
input
dc
output
vcontrol
v 2g,rms
p(t) T =
=
1 cos 2t
s
Re(vcontrol(t)) Re(vcontrol(t))
Ts
which contains a constant term plus a secondharmonic term
67
Load
Separation of power source into its constant and

time-varying components
i2(t)T
+
V 2g,rms
cos 2 2t
Re
V 2g,rms
Re
v(t)Ts
Load
Rectifier output port

The second-harmonic variation in power leads to second-harmonic
variations in the output voltage and current
68
Removal of even harmonics via averaging
v(t)
v(t)Ts
v(t)T
2L
T2L =
1
2
69
2 =

Resulting averaged model
i2(t)T2L
+
V 2g,rms
Re
v(t)T2L
Load
Time invariant model

Power source is nonlinear
70
Perturbation and linearization

The averaged model predicts that the rectifier output current is
i 2(t)
T 2L
p(t)
v(t)
T 2L
T 2L
v 2g,rms(t)
Re(vcontrol(t)) v(t)
= f vg,rms(t), v(t)
Let
T 2L
, vcontrol(t))
T 2L
with
v(t)
i 2(t)
T 2L
T 2L
= V + v(t)
V >> v(t)
= I 2 + i 2(t)
I 2 >> i 2(t)
vg,rms = Vg,rms + vg,rms(t)

vcontrol(t) = Vcontrol + vcontrol(t)
Vg,rms >> vg,rms(t)

Vcontrol >> vcontrol(t)
71
Linearized result
vcontrol(t)
I 2 + i 2(t) = g 2vg,rms(t) + j2v(t)
r2
where
g2 =
df vg,rms, V, Vcontrol)
dvg,rms
1 =
r2
j2 =
Vg,rms
2
=
Re(Vcontrol) V
v g,rms = V g,rms
df Vg,rms, v
d v
, Vcontrol)
T 2L
T 2L
I2
=
V
v T =V
2L
df Vg,rms, V, vcontrol)
dvcontrol
v control = V control
72
V 2g,rms
dRe(vcontrol)
=
VR 2e (Vcontrol) dvcontrol
v control = V control
Small-signal equivalent circuit

i2
+
r2
j2 vcontrol
g 2 vg,rms
Predicted transfer functions
Control-to-output
v(s)
1
= j2 R||r 2
vcontrol(s)
1 + sC R||r 2
Line-to-output
v(s)
1
= g 2 R||r 2
vg,rms(s)
1 + sC R||r 2
73
Model parameters
Table 18.1 Small-signal model parameters for several types of rectifier control schemes
Controller type
g2
j2
r2
Average current control with

feedforward, Fig. 18.14
Pav
VVcontrol
V2
Pav
Current-programmed control,
Fig. 18.16
2Pav
VVg,rms
Pav
VVcontrol
V2
Pav
Nonlinear-carrier charge control

of boost rectifier, Fig. 18.21
2Pav
VVg,rms
Pav
VVcontrol
V2
2Pav
Boost with critical conduction mode

control, Fig. 18.20
2Pav
VVg,rms
Pav
VVcontrol
V2
Pav
DCM buck-boost, flyback, SEPIC,

or Cuk converters
2Pav
VVg,rms
2Pav
VD
V2
Pav
74
Constant power load

ig(t)
+
iac(t)
vg(t)
vac(t)
i2(t)
Re
pac(t)Ts
vC(t)
Pload V +
v(t) load
Energy storage
capacitor
i(t)
Dc-dc
converter
Rectifier and dc-dc converter operate with same average power

Incremental resistance R of constant power load is negative, and is
2
V
R=
Pav
which is equal in magnitude and opposite in polarity to rectifier

incremental output resistance r2 for all controllers except NLC
75
Transfer functions with constant power load

When r2 = R, the parallel combination r2 || R becomes equal to zero.
The small-signal transfer functions then reduce to
j2
v(s)
=
vcontrol(s) sC
g2
v(s)
=
vg,rms(s) sC
76
18.5 RMS values of rectifier waveforms

Doubly-modulated transistor current waveform, boost rectifier:
iQ(t)
t
Computation of rms value of this waveform is complex and tedious
Approximate here using double integral
Generate tables of component rms and average currents for various
rectifier converter topologies, and compare
77
RMS transistor current

RMS transistor current is
I Qrms =
1
Tac
T ac
iQ(t)
i 2Q(t)dt
Express as sum of integrals over

all switching periods contained
in one ac line period:
I Qrms =
1 T
Tac s
T ac/T s
n=1
1
Ts
nT s
i 2Q(t)dt
(n-1)T s
Quantity in parentheses is the value of iQ2, averaged over the nth

switching period.
78
Approximation of RMS expression

I Qrms =
T ac/T s
1 T
Tac s
1
Ts
n=1
nT s
i 2Q(t)dt
(n-1)T s
When Ts << Tac, then the summation can be approximated by an

integral, which leads to the double-average:
I Qrms
=
=
1 lim T
Tac T s0 s
1
Tac
T ac
i 2Q(t)
79
Ts
1
Ts
T ac/T s
n=1
t+T s
1
Ts
nT s
i 2Q()d
(n-1)T s
i 2Q()d dt
T ac
18.5.1 Boost rectifier example

For the boost converter, the transistor current iQ(t) is equal to the input
current when the transistor conducts, and is zero when the transistor
is off. The average over one switching period of iQ2(t) is therefore
2
Q T
s
t+T s
= 1
i 2Q(t)dt
Ts t
= d(t)i 2ac(t)
If the input voltage is

vac(t) = VM sin t
then the input current will be given by
VM
i ac(t) =
sin t
Re
and the duty cycle will ideally be
V =
1
vac(t) 1 d(t)
80
(this neglects
converter dynamics)
Boost rectifier example

Duty cycle is therefore
VM
d(t) = 1
sin t
V
Evaluate the first integral:
2
Q T
s
V 2M
VM
= 2 1
sin t
V
Re
sin 2 t
Now plug this into the RMS formula:
I Qrms =
=
I Qrms =
1
Tac
T ac
i 2Q
0
T ac
1
Tac
2
M
2
e
2 V
Tac R
81
Ts
dt
V 2M
VM
1
sin t
2
V
Re
T ac/2
sin 2 t
0
sin 2 t dt
VM
sin 3 t dt
V
Integration of powers of sin over complete half-cycle
sin ()d =
0
2 246 (n 1) if n is odd
135 n
135 (n 1)
if n is even
246 n
82
sin n ()d
1
2
4
3
3
8
16
15
15
48
Boost example: transistor RMS current
VM
I Qrms =
2 Re
VM
8
1
3 V
= I ac rms
VM
8
1
3 V
Transistor RMS current is minimized by choosing V as small as

possible: V = VM. This leads to
I Qrms = 0.39I ac rms
When the dc output voltage is not too much greater than the peak ac
input voltage, the boost rectifier exhibits very low transistor current.
Efficiency of the boost rectifier is then quite high, and 95% is typical in
a 1kW application.
83
Table of rectifier current stresses for various topologies
Tabl e 18. 3
Summary of rectifier current stresses for several converter topologies

rms
Average
Peak
CCM boost
Transistor
I ac rms
Diode
I dc
VM
1 8
3 V
V
I ac rms 2 2 1 M
8 V
16 V
3 V M
I dc
I ac rms 2 2
I ac rms
Inductor
I ac rms 2
2 I dc V
VM
I ac rms 2
CCM flyback, with n:1 isolation transformer and input filter

Transistor,
xfmr primary
I ac rms
L1
C1
Diode,
xfmr secondary
I ac rms
I dc
V
1+ 8 M
3 nV
I ac rms 2 2
I ac rms
I ac rms 2 2
8 VM
3 nV
3 + 16 nV
2 3 V M
I dc
84
I ac rms 2 1 +
V
n
I ac rms 2
I ac rms 2 max 1,
VM
nV
2I dc 1 + nV
VM
Table of rectifier current stresses

continued
CCM SEPIC, nonisolated
Transistor
V
1+ 8 M
3 V
I ac rms
I ac rms
L1
C1
8 VM
3 V
I ac rms
L2
I dc
I ac rms 2 1 +
I ac rms 2 2
I ac rms 2
VM 3
V 2
I ac rms V M
2 V
3 + 16 V
2 3 V M
I dc
I ac rms
Diode
I ac rms 2 2
I ac rms max 1,
I ac rms
VM
V
VM
V
VM
2
V
2I dc 1 + V
VM
CCM SEPIC, with n:1 isolation transformer

transistor
I ac rms
V
1+ 8 M
3 nV
I ac rms
L1
C1,
xfmr primary
Diode,
xfmr secondary
I ac rms
I dc
8 VM
3 nV
3 + 16 nV
2 3 V M
I ac rms 2 2
I ac rms 2 1 +
I ac rms 2 2
I ac rms 2
I dc
VM
nV
I ac rms 2 max 1,
2I dc 1 + nV
VM
I ac rms
= 2 V , ac input voltage = V M sin( t)
VM
I dc
dc output voltage = V
with, in all cases,
85
Comparison of rectifier topologies

Boost converter
Lowest transistor rms current, highest efficiency
Isolated topologies are possible, with higher transistor stress
No limiting of inrush current
Output voltage must be greater than peak input voltage
Buck-boost, SEPIC, and Cuk converters
Higher transistor rms current, lower efficiency
Isolated topologies are possible, without increased transistor

stress
Inrush current limiting is possible
Output voltage can be greater than or less than peak input

voltage
86
Comparison of rectifier topologies

1kW, 240Vrms example. Output voltage: 380Vdc. Input current: 4.2Arms
Converter
Transistor rms
current
Transistor
voltage
Diode rms
current
Transistor rms
current, 120V
Diode rms
current, 120V
Boost
2A
380 V
3.6 A
6.6 A
5.1 A
Nonisolated
SEPIC
5.5 A
719 V
4.85 A
9.8 A
6.1 A
Isolated
SEPIC
5.5 A
719 V
36.4 A
11.4 A
42.5 A
Isolated SEPIC example has 4:1 turns ratio, with 42V 23.8A dc load
87
18.6 Modeling losses and efficiency

in CCM high-quality rectifiers
Objective: extend procedure of Chapter 3, to predict the output
voltage, duty cycle variations, and efficiency, of PWM CCM low
harmonic rectifiers.
Approach: Use the models developed in Chapter 3. Integrate over
one ac line cycle to determine steady-state waveforms and average
power.
Boost example
L
D1
ig(t)
i(t)
+
vg(t)
Q1
v(t) vg(t)
RL
DRon
D' : 1
VF
i(t)
ig(t)
RL
+
R
Dc-dc boost converter circuit

Averaged dc model
88
v(t)
Modeling the ac-dc boost rectifier

Boost
rectifier
circuit
ig(t)
+
iac(t)
id(t)
RL
D1
vg(t)
vac(t)
i(t)
Q1
v(t)
controller
Averaged
model
vg(t)
RL
d(t) Ron
d'(t) : 1
VF
ig(t)
id(t)
i(t) = I
+
C
(large)
v(t) = V
89
Boost rectifier waveforms

vg(t)
ig(t)
300
10
vg(t)
Typical waveforms
200
ig(t)
(low frequency components)
vg(t)
ig(t) =
Re
100
2
0
0
0
d(t)
30
60
90
120
150
180
0.8
id(t)
0.6
i(t) = I
0.4
0.2
30
60
90
120
150
180
30
60
90
120
150
180
90
Example: boost rectifier

with MOSFET on-resistance
ig(t)
id(t)
d(t) Ron
vg(t)
i(t) = I
d'(t) : 1
C
(large)
v(t) = V
Averaged model
Inductor dynamics are neglected, a good approximation when the ac
line variations are slow compared to the converter natural frequencies
91
18.6.1 Expression for controller duty cycle d(t)

ig(t)
Solve input side of

model:
d(t) Ron
i g(t)d(t)Ron = vg(t) d'(t)v
with
vg(t)
ig(t) =
Re
vg(t)
i(t) = I
d'(t) : 1
id(t)
C
(large)
v(t) = V
vg(t) = VM sin t
eliminate ig(t):
solve for d(t):
v vg(t)
d(t) =
Ron
v vg(t)
Re
vg(t)
d(t)Ron = vg(t) d'(t)v
Re
Again, these expressions neglect converter dynamics, and assume

that the converter always operates in CCM.
92
18.6.2 Expression for the dc load current

Solve output side of
model, using charge
balance on capacitor C:
I = id T
ac
ig(t)
d(t) Ron
vg(t)
i(t) = I
d'(t) : 1
id(t)
C
(large)
vg(t)
i d (t) = d'(t)i g(t) = d'(t)
Re
v(t) = V
Butd(t) is:
hence id(t) can be expressed as
Ron
vg(t) 1
Re
d'(t) =
Ron
v vg(t)
Re
Ron
1
2
Re
v g(t)
i d (t) =
Re
Ron
v vg(t)
Re
Next, average id(t) over an ac line period, to find the dc load current I.
93
Dc load current I
Now substitute vg (t) = VM sin t, and integrate to find id(t)Tac:
T ac/2
I = id
V 2M
Re
2
=
T ac
Tac
Ron
1
sin 2 t
Re
v
VM Ron
sin t
Re
dt
This can be written in the normalized form

T ac/2
2
M
Ron
V
2
I=
1
Tac VRe
Re
with
a=
VM
V
sin 2 t
1 a sin t
dt
Ron
Re
94
Integration
By waveform symmetry, we need only integrate from 0 to Tac/4. Also,
make the substitution = t:
I=
/2
2
M
V
R 2
1 on
VRe
Re
sin 2
1 a sin
This integral is obtained not only in the boost rectifier, but also in the
buck-boost and other rectifier topologies. The solution is
/2
sin 2
d = F(a) = 22
a
1 a sin
1 a2
a is typically much smaller than

unity
Result is in closed form

a is a measure of the loss
resistance relative to Re
2a +
4 sin 1 a + 2 cos 1 a
95
The integral F(a)

/2
sin 2
d = F(a) = 22
a
1 a sin
Approximation via
polynomial:
1 a2
1.15
1.1
F(a) 1 + 0.862a + 0.78a 2
For | a | 0.15, this

approximate expression is
within 0.1% of the exact
value. If the a2 term is
omitted, then the accuracy
drops to 2% for | a | 0.15.
The accuracy of F(a)
coincides with the accuracy
of the rectifier efficiency .
2a +
4 sin 1 a + 2 cos 1 a
1.05
F(a)
1
0.95
0.9
0.85
0.15
0.10
0.05
0.00
0.05
0.10
0.15
a
96
18.6.3 Solution for converter efficiency

Converter average input power is
V 2M
Pin = pin(t) T =
ac
2Re
Average load power is
Pout = VI = V
V 2M
Ron F(a)
1
VRe
Re
2
VM
a=
V
with
Ron
Re
So the efficiency is
Pout
Ron
=
= 1
F(a)
Pin
Re
Polynomial approximation:
Ron
Re
1 + 0.862
VM Ron
V R
+ 0.78 M on
V Re
V Re
97
Boost rectifier efficiency

1
Pout
Ron
=
= 1
F(a)
Pin
Re
.05
R on /R e = 0
0.95
=
R on/R e
0.9
0.1
To obtain high
efficiency, choose V
slightly larger than VM
0.15
=
R
R on/ e
0.2
=
/R e
R on
0.85
0.8
Efficiencies in the range

90% to 95% can then be
obtained, even with Ron
as high as 0.2Re
0.75
0.0
0.2
0.4
0.6
0.8
VM /V
98
1.0
Losses other than

MOSFET on-resistance
are not included here
18.6.4 Design example

Let us design for a given efficiency. Consider the following
specifications:
Output voltage
390 V
Output power
500 W
rms input voltage
120 V
Efficiency
95%
Assume that losses other than the MOSFET conduction loss are
negligible.
Average input power is
Pout 500 W
Pin = =
= 526 W
0.95
Then the emulated resistance is
V 2g, rms (120 V) 2

Re =
=
= 27.4
Pin
526 W
99
Design example
Also,
VM 120 2 V
=
= 0.435
V
390 V
95% efficiency with

VM/V = 0.435 occurs
with Ron/Re 0.075.
.05
R on /R e = 0
0.95
=
R on/R e
0.9
So we require a
MOSFET with on
resistance of
0.1
0.15
=
R
R on/ e
0.2
=
/R e
R on
0.85
0.8
Ron (0.075) Re
= (0.075) (27.4 ) = 2
0.75
0.0
0.2
0.4
0.6
0.8
1.0
VM /V
100

Single-Phase Converter Systems Containing Ideal Rectifiers

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Single-Phase Converter Systems Containing Ideal Rectifiers

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R.

18.4 Single-phase converter systems

It is usually desired that the output voltage v(t) be regulated with

For a given constant load characteristic, the instantaneous load

The instantaneous input power of a single-phase ideal rectifier is

vg(t) = VM sin (t)

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Power flow in single-phase ideal rectifier system

Ideal rectifier is lossless, and contains no internal energy storage.

Hence instantaneous input and output powers must be equal

An energy storage element must be added

Capacitor energy storage: instantaneous power flowing into

Energy storage capacitor voltage must be allowed to vary, in

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Capacitor energy storage in 1 system

Chapter 18: PWM Rectifiers

Single-phase system with internal energy storage

Ideal rectifier (LFR) i (t)

Energy storage capacitor

This system is capable of

Fundamentals of Power Electronics

Internal independent energy

A common example: continue to supply load power in spite of failure

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Energy storage element

But, inductors are not good energy-storage elements

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Low-frequency model of dc-dc converter

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Low-frequency energy storage process, 1 system

Ideal rectifier (LFR)

Difference between rectifier output power and dc-dc converter

In equilibrium, average rectifier and load powers must be equal

But the system contains no mechanism to accomplish this

An additional feeback loop is necessary, to adjust Re such that the

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Obtaining average power balance

Ideal rectifier (LFR)

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Wide-bandwidth output voltage controller

Wide-bandwidth input current controller

Low-bandwidth energy-storage capacitor voltage controller

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Bandwidth of capacitor voltage loop

The energy-storage-capacitor voltage feedback loop causes the

Average rectifier power is controlled by variation of Re.

Re must not vary too quickly; otherwise, ac line current harmonics

Extreme limit: loop has infinite bandwidth, and vc(t) is perfectly

Fundamentals of Power Electronics

Chapter 18: PWM Rectifiers

Input current waveform, extreme limit