Microprocessors Ch2. Overview of A CISC Microprocessor Core - HC 2016 v1

Horia Cucu
Speech & Dialogue Research Laboratory

Faculty of Electronics, Telecommunications and Information Technology
University POLITEHNICA of Bucharest
2.1 Von Neumann Architecture Reminder and Example
Block Diagram of a Microcomputer
The CPU: executes instructions (processes data) and controls the system
The Memory: stores both the data and the instructions
The I/O Devices: interconnect the microcomputer with the outside world
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Microprocessors Architecture
Instruction Execution Example
Reset
Execute
instructions from
address 100h
The CPU is reset and starts executing instructions from a
predefined address in the memory (100h)
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100h
MEM-READ
The CPU sends the address of this first instruction (100h)
through the Address Bus

The CPU sends a MEM-READ signal through the Control Bus
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100h
MEM-READ
The Memory receives the MEM-READ signal and reads the
address from the Address Bus
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The Memory finds the instruction (instruction #1) in the
memory location(s) with the corresponding address (100h)
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instruction #1
ACK
The Memory sends the instruction through the Data Bus and
sends an ACK signal through the Control Bus
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instruction #1
ACK
The CPU receives the ACK signal and reads the instruction
from the Data Bus
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Decode
instruction
The CPU decodes the instruction to "understand" what it has
to do next
Let's suppose that it has to add the value 50h to the value
stored in the memory location with the address 2000h
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2000h
MEM-READ
The CPU sends the address (2000h) on the Address Bus and
sends a MEM-READ signal through the Control Bus
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2000h
MEM-READ
The Memory receives the MEM-READ signal and reads the
address from the Address Bus
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The Memory finds the data (85h) in the memory location
with the corresponding address (2000h)
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85h
ACK
The Memory sends the data (85h) through the Data Bus and
sends an ACK signal through the Control Bus
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85h
ACK
The CPU receives the ACK signal and reads the data from the
Data Bus
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The CPU temporarily stores the data in a register
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The CPU adds the value 50h to the register (the result will be
D5h)
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D5h
2000h
MEM-WRITE
The CPU sends

the result (D5h) through the Data Bus,
the address (2000h) through the Address Bus and
a MEM-WRITE signal through the Control Bus

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D5h
2000h
MEM-WRITE
The Memory
receives the MEM-WRITE signal,
reads the address (2000h) from the Address Bus,
reads the result (D5h) from the Data Bus and
stores the result into the corresponding memory location
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The CPU continues by executing the next instruction
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2.2 The Set of General Purpose Registers
CPU Registers
Register a small amount of storage inside the CPU
Implemented as a set of N synchronized bistables
Stores N bits of data
Highest access speed among all storage options
Several types of registers:
General vs. special purpose (dedicated) registers
Physical vs. logical registers
User-accessible vs. non user-accessible registers
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General Purpose Registers

General purpose registers (GPRs)
Set of equally-sized registers used to store temporary data
(operands/results) needed in the execution of the program
User-accessible (architectural attributes)
Implemented as physical or logical registers
May have implicit functions
The size of the GPRs performance criterion
Equal to the size of the Internal Data Bus
The number of GPRs performance criterion
A larger number of GPRs => faster, more compact programs,
ease of programming,
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General Purpose Registers
MUX (multiplexer) outputs one of the data inputs
(depending on the address inputs)

Internal Data Bus extension of the External Data Bus
inside the CPU
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Special Purpose Registers

Special purpose registers
Dedicated registers that can be used only for specific purposes
Size depends on the particular role of the register
Some are user-accessible (architectural attributes), some not
Examples:
Data register (DR) and Address register (AR)
Accumulator (A)
Status (Flags) register (F)
Instruction Pointer (IP)
Stack Pointer (SP)
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2.3 The interface between the CPU and the System Bus
The Data Register

and the Address Register
DR (data register): the CPU Data Bus interface

The data in DR are available to all the hardware blocks
connected on the Data Bus

The size of DR is the size of the Data Bus
DR is not an architectural attribute
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The Data Register

and the Address Register
AR (address register): the CPU Address Bus interface

The address in AR is available to all the hardware blocks
connected on the Address Bus; only the CPU writes in AR

The size of AR is the size of the Address Bus
AR is not an architectural attribute
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2.4 The Arithmetic and Logic Unit (ALU)
The Arithmetic and Logic Unit

The Arithmetic and Logic Unit (ALU)
digital circuit that performs
integer arithmetic operations: add, subtract, increment, etc.

logical operations: and, or, xor, not, clear, shift, rotate, etc.
The inputs of the ALU

Data to be processed (one or two integer numbers)
The operation to be performed (specified by the Control Unit)
Possibly some status flags
The outputs of the ALU
The operation result(s) are placed in the Accumulator or on the
Internal Data Bus
The status flags are updated after each operation
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The Arithmetic and Logic Unit
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The Status Register

The Status Register (also called Flags Register)
A collection of flag bits, which store information regarding
the state of the processor
Arithmetic and logic flags
Bits encoding the status of the previous arithmetic/logic
operation
Used and updated by the ALU
Other types of flags
Interrupt enable flag
Supervisor flag
Direction flag
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Typical Arithmetic and Logic Flags

Carry flag (CF): signals an arithmetic carry or borrow for
unsigned numbers
Parity flag (PF): signals that the number of ones in the least
significant byte of the result is even

Zero flag (ZF): signals that the result is 0
Sign flag (SF): signals that the most significant bit of the N-bit
result is set (the sign bit in twos complement representation)

Overflow flag (OF): signals an arithmetic overflow for signed
numbers
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The Accumulator and the Shift Register

The Accumulator special purpose register
Stores one of the operands before the operation
Stores the result of the operation
Size equal to the size of the general purpose registers
Is user-accessible (architecture attribute)
The Shift Register special purpose register
Used by the ALU to make shift and rotation operations
Size double than the size of the general purpose registers
Is not user-accessible
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2.5 The Memory Addressing Control Unit (MACU)
The Memory Addressing Control Unit

Hardware block that computes the physical address needed to
identify information in the Memory or I/O Ports
Receives input from the Internal Data Bus
Places its output (a physical address) in the Address Register
Functionality classification
Instruction addressing (in the program memory)
Sequentially, instruction after instruction

Non-sequentially, through jumps
Data addressing (in the data memory)
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Elementary data addressing

Stack addressing
Data arrays addressing
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Memory Management Techniques

Linear Memory Organization
The memory is regarded as a single block of memory locations
The memory is addressed using directly a physical address
Memory Segmentation
The memory is logically divided into segments (non equal-sized,
possibly overlapping sections)
The memory is addressed using a segment address and an offset
Memory Paging
The memory is logically divided into pages (equal sized, nonoverlapping, strictly concatenated sections)
The memory is addressed using a page address and an offset
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Sequential Instructions Addressing

The main principle of the von Neumann architecture
Achieved through the means of a counter register
The Program Counter (PC) special purpose register
Stores the physical address of the current instruction
Incremented after the execution of each instruction
Size equal to the size of a physical address
In some architectures is user-accessible
Other hardware blocks involved: MUX2 and MUX5

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The program is executed instruction after instruction

The Instruction Register stores the instruction before
decoding
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Non-Sequential Instructions Addressing

Exceptions to the normal, sequential execution of a program:
jumps, loops or subprogram calls

The jump address can be:
An absolute address: a complete physical address
The address is provided by another hardware block through the

Internal Data Bus
An offset relative to the address of the current instruction
The offset provided by another hardware block through the Internal

Data Bus is added to the address in PC
The Program Counter is also updated

Other hardware blocks involved: MUX2, MUX4, MUX5, Adder
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Elementary Data Addressing

The data can potentially reside anywhere in the memory
The address required to identify the data can be:
An absolute address: a complete physical address
The address is provided by another hardware block through the

Internal Data Bus
An offset relative to the address of the current instruction
The offset provided by another hardware block through the

Internal Data Bus is added to the address in PC
Other hardware blocks involved: MUX4, MUX5, Adder

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Stack Addressing
The Stack: LIFO data structure
Accessed through the means of a pointer register
Pushing an element in the Stack -> decrementing the pointer
Popping an element out of the Stack -> incrementing the pointer
Software vs. hardware Stack
The Stack Pointer (SP ) special purpose register
Stores the physical address of the top element
User-accessible (architecture attribute)
Other hardware blocks involved: MUX3 and MUX5

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Stack Addressing
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Data Arrays Addressing

The Memory can accommodate arrays of data
Accessed through the means of index registers, which store the
physical address of the first element in the array
The address of a random element is obtained by adding a relative
offset to the index register
Offset size => max number of elements in the array
The Index Registers (IX) special purpose registers

Store the physical addresses of various data arrays
User-accessible (architecture attribute)
Other hardware blocks involved: MUX1, MUX4, MUX5, Adder
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2.6 The Timing and Control Unit
The Timing and Control Unit

The Timing and Control Unit (TCU)
Hardware block inside the CPU that:
fetches, decodes and manages the execution of instructions

controls the flow of data through the processor
coordinates the activities of the other hardware blocks within the
CPU and also outside the CPU
achieves the above through timing and control signals
Design: hardwired vs. micro-programmed
The inputs to the TCU

The instruction in the Instruction Register (IR)
Internal control signals (the status flags)
The outputs of the TCU
Internal control signals (for the blocks within the CPU)
External control signals (for the blocks outside the CPU)
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The Timing and Control Unit
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The Instruction Register and

the Instruction Decoder
The Instruction Register (IR) special purpose register
Stores the instruction code fetched from the memory
Receives input only from the Data Register
Size equal to the smallest instruction code
Is not user-accessible (not an architecture attribute)
The Instruction Decoder
Hardware block that decodes instruction codes
Each code has an associated, unique output line

Only one of the output lines will be 1 at any moment in time
Receives input from the Instruction Register
Sends its output to the Timing and Control Unit

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The Typical CISC Instruction Format

The instructions are stored in the memory in one or several
memory locations (depending on the type of instruction)

Instruction format all the information required by the CPU to
execute an instruction
Comprises at least one byte: the instruction code (the semantic)
The instruction code may require additional bytes
May comprise operands, addresses, offsets on one or several bytes
1-6 bytes for 16-bit x86 microprocessors
1-15 bytes for 32-bit x86 microprocessors
Example:
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code
[code]
[data or
address]
[data or
address]
[data or
address]
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Instruction Execution Timing

Typically, the execution of an instruction has several stages:
Fetch the instruction code is read from the memory
Decode the instruction code is decoded
Execute the instruction is executed (might comprise operands fetch)
Write the result is written in a register or a memory location
The instruction execution stages are called machine cycles
Any instruction is executed in one or several machine cycles (depending on
its complexity)
In a machine cycle the CPU executes sequentially several elementary
actions accomplishing a clear, well-defined task
Elementary actions are executed once every clock cycle
An internal clock signal is generated based on an external quartz oscillator
A CPU state is a physical time period equal to the duration of a clock cycle
In a state, the CPU executes one elementary action or two independent
elementary actions (in the same time)
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Instruction Execution Timing Example

Instruction example: (2000h) <- (2000h) + 50h
Instruction format:
code
addrlow
(00h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand 1
M5. Read operand 2 and Execute
M6. Write result
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addrhigh
(20h)
data
(50h)
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Machine Cycle 1: Fetch

Instruction format:
addrlow
addrhigh
code
(00h)
(20h)
6 machine cycles:
data
(50h)
T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (IR) <- (DR)
T4. decode instruction code

M4. Read operand 1
M6. Write result
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T2. (PC) <- (PC) + 1, (DR) <- ((AR))
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T3. (IR) <- (DR)
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T4. decode instruction code
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Machine Cycle 2: Read Address

Instruction format:
code
addrlow
(00h)
6 machine cycles:
addrhigh
(20h)
data
(50h)

T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (AUX2) <- (DR)

M4. Read operand 1
M6. Write result

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T2. (PC) <- (PC) + 1, (DR) <- ((AR))
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T3. (AUX2) <- (DR)
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Instruction format:
code
addrlow
(00h)
6 machine cycles:
addrhigh
(20h)
data
(50h)

T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (AUX1) <- (DR)
M4. Read operand 1

M6. Write result

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T2. (PC) <- (PC) + 1, (DR) <- ((AR))
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T3. (AUX1) <- (DR)
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Machine Cycle 4: Read Operand 1

Instruction format:
code
addrlow
(00h)
6 machine cycles:
M4. Read operand 1
addrhigh
(20h)
data
(50h)

T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (A) <- (DR)
M6. Write result

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T2. (PC) <- (PC) + 1, (DR) <- ((AR))
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T3. (A) <- (DR)
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Machine cycle 5: Read operand 2 and Execute

Instruction format:
code
addrlow
(00h)
6 machine cycles:
M4. Read operand 1
addrhigh
(20h)
data
(50h)
T1. (AR) <- (AUX1, AUX2), MEM-READ

T2. (DR) <- ((AR))
T3. (A) <- (A) + (DR)
M6. Write result

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T1. (AR) <- (AUX1, AUX2), MEM-READ
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T2. (DR) <- ((AR))
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T3. (A) <- (A) + (DR)
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Machine Cycle 6: Write Result

Instruction format:
code
addrlow
(00h)
6 machine cycles:
M4. Read operand 1
M6. Write result
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addrhigh
(20h)
data
(50h)
T1. (DR) <- (A)

T2. (AR) <- (AUX1, AUX2), MEM-WRITE
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T1. (DR) <- (A)
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T2. (AR) <- (AUX1, AUX2), MEM-WRITE
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2.7 Summary
Summary
General Purpose Registers (GPRs)

Memory Data Register (DR)
Memory Address Register (AR)
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Arithmetic and Logic Unit (ALU)

Memory Addressing Control Unit
Timing and Control Unit (TCU)
81

Microprocessors Ch2. Overview of A CISC Microprocessor Core - HC 2016 v1

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Horia Cucu

Speech & Dialogue Research Laboratory

2.1 Von Neumann Architecture Reminder and Example

Block Diagram of a Microcomputer

Instruction Execution Example

The CPU is reset and starts executing instructions from a

predefined address in the memory (100h)

Instruction Execution Example

The CPU sends the address of this first instruction (100h)

through the Address Bus

Instruction Execution Example

The Memory receives the MEM-READ signal and reads the

address from the Address Bus

Instruction Execution Example

The Memory finds the instruction (instruction #1) in the

memory location(s) with the corresponding address (100h)

Instruction Execution Example

sends an ACK signal through the Control Bus

Instruction Execution Example

from the Data Bus

Instruction Execution Example

The CPU decodes the instruction to "understand" what it has

Instruction Execution Example

sends a MEM-READ signal through the Control Bus

Instruction Execution Example

The Memory receives the MEM-READ signal and reads the

address from the Address Bus

Instruction Execution Example

The Memory finds the data (85h) in the memory location

with the corresponding address (2000h)

Instruction Execution Example

sends an ACK signal through the Control Bus

Instruction Execution Example

Instruction Execution Example

The CPU temporarily stores the data in a register

Instruction Execution Example

Instruction Execution Example

The CPU sends

a MEM-WRITE signal through the Control Bus

Instruction Execution Example

Instruction Execution Example

The CPU continues by executing the next instruction

2.2 The Set of General Purpose Registers

General Purpose Registers

General Purpose Registers

MUX (multiplexer) outputs one of the data inputs

(depending on the address inputs)

Special Purpose Registers

The Data Register

DR (data register): the CPU Data Bus interface

connected on the Data Bus

The Data Register

AR (address register): the CPU Address Bus interface

connected on the Address Bus; only the CPU writes in AR

2.4 The Arithmetic and Logic Unit (ALU)

The Arithmetic and Logic Unit

integer arithmetic operations: add, subtract, increment, etc.

The inputs of the ALU

The Arithmetic and Logic Unit

The Status Register

Typical Arithmetic and Logic Flags

significant byte of the result is even

result is set (the sign bit in twos complement representation)