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The CPU: executes instructions (processes data) and controls the system
The Memory: stores both the data and the instructions
The I/O Devices: interconnect the microcomputer with the outside world
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Reset
Execute
instructions from
address 100h
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100h
MEM-READ
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100h
MEM-READ
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instruction #1
ACK
The Memory sends the instruction through the Data Bus and
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instruction #1
ACK
The CPU receives the ACK signal and reads the instruction
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Decode
instruction
to do next
Let's suppose that it has to add the value 50h to the value
stored in the memory location with the address 2000h
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2000h
MEM-READ
The CPU sends the address (2000h) on the Address Bus and
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2000h
MEM-READ
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85h
ACK
The Memory sends the data (85h) through the Data Bus and
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85h
ACK
The CPU receives the ACK signal and reads the data from the
Data Bus
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The CPU adds the value 50h to the register (the result will be
D5h)
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D5h
2000h
MEM-WRITE
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D5h
2000h
MEM-WRITE
The Memory
receives the MEM-WRITE signal,
reads the address (2000h) from the Address Bus,
reads the result (D5h) from the Data Bus and
stores the result into the corresponding memory location
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CPU Registers
Register a small amount of storage inside the CPU
Implemented as a set of N synchronized bistables
Stores N bits of data
Highest access speed among all storage options
Several types of registers:
General vs. special purpose (dedicated) registers
Physical vs. logical registers
User-accessible vs. non user-accessible registers
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2.3 The interface between the CPU and the System Bus
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unsigned numbers
Parity flag (PF): signals that the number of ones in the least
numbers
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decoding
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Stack Addressing
The Stack: LIFO data structure
Accessed through the means of a pointer register
Pushing an element in the Stack -> decrementing the pointer
Popping an element out of the Stack -> incrementing the pointer
Software vs. hardware Stack
The Stack Pointer (SP ) special purpose register
Stores the physical address of the top element
Size equal to the size of a physical address
User-accessible (architecture attribute)
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Stack Addressing
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execute an instruction
Comprises at least one byte: the instruction code (the semantic)
The instruction code may require additional bytes
May comprise operands, addresses, offsets on one or several bytes
1-6 bytes for 16-bit x86 microprocessors
1-15 bytes for 32-bit x86 microprocessors
Example:
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code
[code]
[data or
address]
[data or
address]
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[data or
address]
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Instruction format:
code
addrlow
(00h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand 1
M5. Read operand 2 and Execute
M6. Write result
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addrhigh
(20h)
data
(50h)
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code
(00h)
(20h)
6 machine cycles:
M1. Fetch and Decode
data
(50h)
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Instruction format:
code
addrlow
(00h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
addrhigh
(20h)
data
(50h)
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Instruction format:
code
addrlow
(00h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
addrhigh
(20h)
data
(50h)
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Instruction format:
code
addrlow
(00h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand 1
addrhigh
(20h)
data
(50h)
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Instruction format:
code
addrlow
(00h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand 1
M5. Read operand 2 and Execute
addrhigh
(20h)
data
(50h)
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Instruction format:
code
addrlow
(00h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand 1
M5. Read operand 2 and Execute
M6. Write result
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addrhigh
(20h)
data
(50h)
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2.7 Summary
Summary
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