Novel Multiplier

A FINAL PROJECT REPORT
ON
A NOVEL APPORACH TO REALIZE BUILT IN SELF TEST
ENABLED UART USING VHDL
This dissertation is submitted in partial fulfillment of the requirements for the
award of degree of
MASTER OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
(VLSI & EMBEDEDED SYSTEM)
Submitted By
V RATNA RAJU KATARAPU (13KK1D6817)
Under the esteemed guidance of
P.SUDHAKAR RAO
Assoc. Professor
DEPT.OF E.C.E
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
NOVA COLLEGE OF ENGINEERING
(Affiliated to Jawaharlal Nehru Technological University)

Jupudi (V), Ibrahimpatnam (M), Krishna (D).
2013 -2015
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Jupudi (V), Ibrahimpatnam (M), Krishna (D).
[Affiliated to JNTUK, Approved by AICTE]
CERTIFICATE
This is to certify that the project on A NOVEL APPORACH TO REALIZE
BUILT IN SELF TEST ENABLED UART USING VHDL that is being submitted by V
RATNARAJU KATARAPU (13KK1D6817) partial fulfillment of the requirement

of the award for the degree of Master of technology in Electronics and Communications
Engineering J.N.T.U., Kakinada. This record of the bonafied work carried out by them
under my guidance and supervision. The result embodied in this project report has been
submitted to any other university or Institute for the award of any degree.
Internal guide
Head of Department
P.SUDHAKAR RAO,
Mr. P. SUDHAKAR RAO
M.Tech
M.Tech
External Viva-Voce held on dated:__________________________
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DECLARATION
This is the certify that the work reported in the presented thesis titled A NOVEL
APPROACH TO REALIZE BUILT IN SELF TEST ENABLED UART USING VHDL
is a record work done by me in the department of Electronics and Communication
Engineering , Nova College of Engineering .
No part of the thesis is copied from books/journals/internet and wherever the portion
is taken; the same has been duly referred in the text. The reported are based on the project
work done entirely by me and not copied from any other source.
VENKATA RATNARAJU KATARAPU (13KK1D6817)
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ACKNOWLEDGEMENT
We would like to acknowledge the secretary Lion.M.KrishnaRao and management of
Nova College of engineering and technology, jupudi for providing necessary
infrastructure and lab facility for executing this work.
We whole heartedly acknowledge, Director Dr.J.SrinivasaRao and Principal
Dr.T.V.S. Arun Murthy for giving opportunity and support for completion of project
We would like to acknowledge Academic Co-Coordinator V.Surender Reddy and
HEAD OF DEPT ECE Mr. P.SUDHAKAR RAO for giving opportunity to execute this
project.
It is a great pleasure to work for my M.Tech under the valuable guidance of
Mr.P.SUDHAKAR RAO Assco. Professor in ECE Department, we are thankful to him/her
for his/her affection, moral support, and encouragement throughout the work. We are
always grateful to him/her.
We also extend our thanks to all faculty members of Electronics and
Communication Engineering, for their valuable guidance and encouragement in this
main-project.
We thank all my well-wishers for rendering necessary support during the
execution of this work. We thank all my parents and family members and friends for
their encouragement during the execution of this work.
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CONTENTS
CHAPTER 1: INTRODUCTION
PAGE NO
1
1.1 Existing Multiplier Technology
1.2 Proposed Multiplier
1.3 Reversible Logic Gates
1.4 Literature Survey
1.5 Thesis Organization
CHAPTER 2: VEDIC MATHEMATICS
CHAPTER 3: LITERATURE SURVEY
12
3.1 Introduction
12
3.2 Definition Pertaining To Reversible Logic
14
3.2.1 Reversible Function

3.2.2 Reversible Logic Gate
3.2.3 Constant Outputs
3.2.4 Garbage Outputs
3.2.5 Quantum Cost
3.2.6 Flexibility
3.2.7 Gate Level
3.2.8 Hardware Complexity
3.3 Design Constraints Of Reversible Logic
15
15
3.4.1 CNOT Gate

3.4.2 Fredkin Gate
3.4.3 Peres Gate
3.4.4 HNG Gate
CHAPTER 4. MULTIPLIER TECHNOLOGY
19
4.1 Multiplication Algorithm
19
4.2 Serial Multiplier
21
4.3 Parellel Multiplier
21
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4.4 Array Multiplier
22
4.5 Booth Multiplier
23
CONTENTS
PAGE NO
4.6 Wallace Multiplier
24
4.7 Urdva Multiplier
25
CHAPTER 5: VEDIC MULTIPLIER URDVA TIRYAKBAYAM LOGIC 29

5.1 Conventional Multiplier
29
5.2 UT 2x2 Multiplier
30
5.3 UT 4x4 Multiplier
31
CHAPTER 6: SIMULATION RESULT
35
6.1 Multiplier 2x2 Bit
35
6.2 RC Adder 4 Bit
37
6.3 RC Adder 5 Bit
39
6.4 Multiplier 4x4 Bit
41
CHAPTER 7: CONCALUSION
45
REFERENES
46
APPENDIX
47
PAPER
54
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List of Figures
Fig 3.1 Circuit Logic Symbol of CNOT Gate
16
Fig 3.2 Circuit Logic Symbol of FREDKIN Gate
16
Fig 3.3 Circuit Logic Symbol of PERES Gate
17
Fig 3.4 Circuit Logic Symbol of HNG Gate
18
Fig 4.1 Multiplication of 4x4 Multiplier
19
Fig 4.2 Partial Products of 4x4 Multiplier
20
Fig 4.3 Serial Multiplier
21
Fig 4.4 Serial/Parellel Multiplier
22
Fig 4.5 Array Multiplier
23
Fig 4.6 Booth Multiplier
24
Fig 4.7 Wallce Tree Multipler
25
Fig 4.8 Cross Multiplication of UT Multiplier
26
Fig 4.9 Example of UT Multiplier
27
Fig 5.1 Conventional Multiplier
29
Fig 5.2 UT 2x2 Multiplier
30
Fig 5.3 Cross Multiplication of 2x2 UT Multiplier
31
Fig 5.4 UT 4x4 Multiplier
32
Fig 5.5 Design of 4 bit RC Adder
33
Fig 5.6 Design of 5 bit RC Adder
34
Fig 5.7 Cross Multiplication of 2x2 UT Multiplier
34
Fig 6.1 2x2 Bit Multipler
35
Fig 6.2 RTL Schematic of 2x2 Bit Multiplier
36
Fig 6.3 Simulation Result of 2x2 Multiplier
36
Fig 6.4 RC Adder 4 Bit
37
Fig 6.5 RTL Schematic of 4 Bit RC Adder
38
Fig 6.6 Simulation Result of 4 Bit RC Adder
38
Fig 6.7 RC Adder 5 Bit
39
Fig 6.8 RTL Schematic of 5 Bit RC Adder
39
Fig 6.9 Simulation Result of 5 Bit RC Adder
40
Fig 6.10 Multiplier 4x4 Bit
41
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Fig 6.11 RTL Schematic of 4 Bit Multiplier
41
Fig 6.12 Simulation Result of 4 Bit Multiplier
42
Fig 6.13 Comparison of Various Multiplier Techniques
43
CHAPTER 1
INTRODUCTION
1. INTRODUCTION
Multiplication is one of the more silicon-intensive functions, especially when

implemented in Programmable Logic. Multipliers are key components of many high
performance systems such as FIR filters, Microprocessors, Digital Signal Processors, etc. A
system's performance is generally determined by the performance of the multiplier, because
the multiplier is generally the slowest element in the system. Furthermore, it is generally the
most area consuming. Hence, optimizing the speed and area of the multiplier is a major
design issue. Vedic mathematics is the ancient Indian system of mathematics which mainly
deals with Vedic mathematical formula and their application to various branches of
mathematics. The word 'Vedic' is derived from the word 'Veda' which means the store-house
of all knowledge. Vedic mathematics was reconstructed from the ancient Indian scriptures
(Vedas) by Sri Bharati Krishna Tirthaji (1884-1960), after his eight years of research on
Vedas. The Vedic mathematics is based on 16 Sutras (or aphorisms) dealing with various
branches of mathematics like arithmetic, algebra, geometry etc.
1.1. EXISTING MULTIPLIER TECHNIQUES
The common multiplication method is add and shift algorithm. In parallel
multipliers number of partial products to be added is the main parameter that determines the
performance of the multiplier. To reduce the number of partial products to be added,
Modified Booth algorithm is one of the most popular algorithms. To achieve speed
improvements Wallace Tree algorithm can be used to reduce the number of sequential adding
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stages. Further by combining both Modified Booth algorithm and Wallace Tree technique we
can see advantage of both algorithms in one multiplier. However with increasing parallelism,
the amount of shifts between the partial products and intermediate sums to be added will
increase which may result in reduced speed, increase in silicon area due to irregularity of
structure and also increased power consumption due to increase in interconnect resulting
from complex routing.
1.2. PROPOSED MULTIPLIER

Multipliers play an important role in todays digital signal processing and various
other applications. With advances in technology, many researchers have tried and are trying
to design multipliers which offer either of the following design targets high speed, low
power consumption, regularity of layout and hence less area or even combination of them in
one multiplier thus making them suitable for various high speed, low power and compact
VLSI implementation.
Multipliers are vital components of any processor or computing machine. More often
than not, performance of microcontrollers and Digital signal processors are evaluated on the
basis of number of multiplications performed in unit time. Hence better multiplier
architectures are bound to increase the efficiency of the system. Vedic multiplier is one such
promising solution. Its simple architecture coupled with increased speed forms an
unparalleled combination for serving any complex multiplication computations. Tagged with
these highlights, implementing this with reversible logic further reduces power dissipation.
Power dissipation is another important constraint in an embedded system which

cannot be neglected. In this paper we bring out a Vedic multiplier known as "Urdhva
Tiryakbhayam" meaning vertical and crosswise, implemented using reversible logic, which is
the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs),
and other applications of DSP like imaging, software defined radios, wireless
communications.
1.3. REVERSIBLE LOGICAL GATES
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Reversible logic is a promising computing design paradigm which presents a method

for constructing computers that produce no heat dissipation. Reversible computing emerged
as a result of the application of quantum mechanics principles towards the development of a
universal computing machine.Specifically, the fundamentals of reversible computing are
based on the relationship between entropy, heat transfer between molecules in a system, the
probability of a quantum particle occupying a particular state at any given time, and the
quantum electrodynamics between electrons when they are in dose proximity.
The basic principle of reversible computing is that a objective device with an identical
number of input and output lines will produce a computing environment where the
electrodynamics of the system allow for prediction of all future states based on known past
states, and the system reaches every possible state, resulting in no heat dissipation. A
reversible logic gate is an N-input N-output logic device that provides one to one mapping
between the input and the output.
It not only helps us to determine the outputs from the inputs but also helps us to
uniquely recover the inputs from the outputs. Garbage outputs are those which do not
contribute to the reversible logic realization of the design. Quantum cast refers to the cost of
the circuit in terms of the cost of a primitive gate. Gate count is the number of reversible
gates used to realize the function. Gate level refers to the number of levels which are required
to realize the given logic functions.
1.4. LITERATURE SURVEY

Energy loss is an important consideration in digital circuit design. A part of this
problem arises from the technological non ideality of switches and materials. The other part
of the problem arises from Land Auers principle for which there is no solution. Land Auers
Principle states that logical computations that are not reversible necessarily generate
k*T*ln(2) joules of heat energy, where k is the Boltzmann's Constant k=1.38xlO-23 J/K, T is
the absolute temperature at which the computation is performed.
Although this amount of heat appears to be small, Moore's Law predicts exponential
growth of heat generated due to information lost, which will be a noticeable amount of heat
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loss in next decade. Also by second law of thermodynamics any process that is reversible will
not change its entropy. On thermo dynamical grounds, the erasure of one bit of information
from the mechanical degrees of a system must be accompanied by the thermalization of an
amount of k*T*ln (2) joules of energy. The information entropy H can be calculated for any
probability distribution. Similarly the thermodynamic entropy S refers to thermodynamic
probabilities specifically.Thus gain in entropy always means loss of information, and nothing
more. Design that does not result in information loss is called reversible. It naturally takes
care of heat generated due to information loss.
Bennett showed that zero energy dissipation would be possible only if the network
consists of reversible logic gates, Thus reversibility will become an essential property in
future circuit design technologies. In the multiplier is designed using two units; one is the
partial product generation unit constructed using Fredkin gates and other the summing unit
constructed using 4x4 TSG gates. Presented a fault tolerant reversible 4x4 multiplier circuit.
For construction of this circuit parity preserving FRG and MIG gates were used.
Multiplier circuit was designed in two parts. In second part of circuit MIG gates were
used instead of half adders and full adders. Has proposed a design of reversible multiplier
which makes use of Peres gate for generation of partial products as compared to which uses
Fredkin gates. For the construction of adders the HNG gate was devised. Proposes low
quantum cost realization of reversible multipliers which mainly uses Peres full adder gate (PF
AG) for its design. It also uses Peres gates for the generation of partial products.
1.5. THESIS ORGANIZATION

This project is organized into six chapters. The second chapter focuses on the various
multiplier techniques. Third chapter deals with the reversible logical gates. Fourth chapter
deals with the Vedic multiplier. The VHDL simulation results and the comparison of
proposed Vedic multiplier and existing multiplier techniques are included in fifth chapter.
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CHAPTER 2
LITERATURE SURVEY 1
(Vedic mathematics)
2. VEDIC MATHEMATICS
Many Indian Secondary School students consider Mathematics a very difficult
subject. Some students encounter difficulty with basic arithmetical operations. Some students
feel it difficult to manipulate symbols and balance equations. In other words, abstract and
logical reasoning is their hurdle. Many such difficulties in learning Mathematics enter into a
long list if prepared by an experienced teacher of Mathematics. Volumes have been written
on the diagnosis of 'learning difficulties' related to Mathematics and remedial techniques.
Learning Mathematics is an unpleasant experience to some students mainly because it
involves mental exercise. Of late, a few teachers and scholars have revived interest in Vedic
Mathematics which was developed, as a system derived from Vedic principles, by Swami
Bharati Krishna Tirthaji in the early decades of the 20th century. Dr. Narinder Puri of the
Roorke University prepared teaching materials based on Vedic Mathematics during 1986 89.
A few of his opinions are stated here under:

i.
Mathematics, derived from the Veda, provides one line, mental and superfast
methods along with quick cross checking systems.
ii. Vedic Mathematics converts a tedious subject into a playful and blissful one which
students learn with smiles.
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iii. Vedic Mathematics offers a new and entirely different approach to the study of
Mathematics based on pattern recognition. It allows for constant expression of a
student's creativity, and is found to be easier to learn.
iv. In this system, for any problem, there is always one general technique applicable to
all cases and also a number of special pattern problems. The element of choice and
flexibility at each stage keeps the mind lively and alert to develop clarity of thought
and intuition, and thereby a holistic development of the human brain automatically
takes place.
v.
Vedic Mathematics with its special features has the inbuilt potential to solve the
psychological problem of Mathematics - anxiety.
J.T.Glover (London, 1995) says that the experience of teaching Vedic Mathematics' methods
to children has shown that a high degree of mathematical ability can be attained from an early
stage while the subject is enjoyed for its own merits.
A.P. Nicholas (1984) puts the Vedic Mathematics system as 'one of the most delightful
chapters of the 20th century mathematical history'.
Prof. R.C. Gupta (1994) says 'the system has great educational value because the Sutras
contain techniques for performing some elementary mathematical operations in simple ways,
and results are obtained quickly'.
Prof. J.N. Kapur says 'Vedic Mathematics can be used to remove mathphobia, and can be
taught to (school) children as enrichment material along with other high speed methods'.
Dr. Michael Weinless, Chairman of the Department of Mathematics at the M.I.U, Iowa says
thus: 'Vedic Mathematics is easier to learn, faster to use and less prone to error than
conventional methods. Furthermore, the techniques of Vedic Mathematics not only enable the
students to solve specific mathematical problems; they also develop creativity, logical
thinking and intuition.'
Keeping the above observations in view, let us enter Vedic Mathematics as given by
Sri Bharati Krishna Tirthaji (1884 - 1960), Sankaracharya of Govardhana Math, Puri.
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Entering into the methods and procedures, one can realize the importance and applicability of
the different formulae (Sutras) and methods.
These Sutras along with their brief meanings are enlisted below alphabetically.
1) (Anurupye) Shunyamanyat If one is in ratio, the other is zero.
2)
Chalana-Kalanabyham Differences and Similarities.
3)
Ekadhikina Purvena By one more than the previous one.
4)
Ekanyunena Purvena By one less than the previous one.
5)
Gunakasamuchyah The factors of the sum is equal to the sum of the factors.
6)
Gunitasamuchyah The product of the sum is equal to the sum of product.
7)
Nikhilam Navatashcaramam Dashatah All from 9 and the last from 10.
8)
Paraavartya Yojayet Transpose and adjust.
9)
Puranapuranabyham By the completion or Non-completion.
10) Sankalana-vyavakalanabhyam By addition and by subtraction.

11) Shesanyankena Charamena The remainders by the last digit.
12) Shunyam Saamyasamuccaye When the sum is the same that sum is zero.
13) Sopaantyadvayamantyam The ultimate and twice the Penultimate.
14) Urdhva-Tiryagbyham Vertically and crosswise.
15) Yaavadunam Whatever the extent of its efficiency.
16) Viyashtisamanstih part and hole.
The difference between the number and the base is termed as deviation. Deviation
may be positive or negative. Positive deviation is written without the positive sign and the
negative deviation, is written using Rekhank (a bar on the number).
URDHVA TIRYAGBHYAM
Urdhva tiryagbhyam is the general formula applicable to all cases of Multiplication
and also in the division of a large number by another large Number. It means
(a) Multiplication of two 2 digit numbers.

Ex.1: Find the product 14 X 12
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1) The right hand most digit of the multiplicand, the first number (14) i.e.,4 is
multiplied by the right hand most digit of the multiplier, the second number (12) i.e.,
2. The product 4 X 2 = 8 forms the right hand most part of the answer.
2)
Now, diagonally multiply the first digit of the multiplicand (14) i.e., 4 and second
digit of the multiplier (12)i.e., 1 (answer 4 X 1=4); then multiply the second digit of the
multiplicand i.e.,1 and first digit of the multiplier i.e., 2 (answer 1 X 2 = 2);
Add these two i.e., 4 + 2 = 6. It gives the next, i.e., second digit of the answer. Hence
second digit of the answer is 6.
3)
Now, multiply the second digit of the multiplicand i.e., 1 and second digit of the
multiplier i.e., 1 vertically, i.e., 1 X 1 = 1. It gives the left hand most part of the answer.
Let the two numbers be (ax + bx + c) and (dx2 + ex + f). Note that x=10.
Now the product is
ax2 + bx + c
dx2 + ex + f
ad.x4 + bd.x3 + cd.x2 + ae.x3 + be.x2 + ce.x + af.x2 + bf.x + cf
= ad.x4 + (bd + ae). x3 + (cd + be + af).x2 + (ce + bf)x + cf
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Note the following points:

i.
The coefficient of x4 , i.e., ad is obtained by the vertical multiplication of the first

coefficient from the left side :
ii.
The coefficient of x3 , i.e., (ae + bd) is obtained by the cross wise multiplication of the
first two coefficients and by the addition of the two products;
iii. The coefficient of x2 is obtained by the multiplication of the first coefficient of the
multiplicand(ax2+bx +c) i.e., a; by the last coefficient of the multiplier (dx2 +ex +f) i.e.,
f ; of the middle one i.e., b of the multiplicand by the middle one i.e., e of the multiplier
and of the last one i.e., c of the multiplicand by the first one i.e., d of the multiplier and
by the addition of all the three products i.e., af + be +cd :
iv. The coefficient of x is obtained by the cross wise multiplication of the second coefficient
i.e., b of the multiplicand by the third one i.e., f of the multiplier, and conversely the third
coefficient i.e., c of the multiplicand by the second coefficient i.e., e of the multiplier and
by addition of the two products,i.e., bf +ce ;
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v.
And finally the last (independent of x) term is obtained by the vertical multiplication of
the last coefficients c and f i.e., cf
Thus the process can be put symbolically as (from left to right)
Consider the following example

124 X 132.
Proceeding from right to left
i.
4 X 2 = 8. First digit = 8
ii.
(2 X 2) + (3 X 4) = 4 + 12 = 16. The digit 6 is retained and 1 is carried over to

left side. Second digit = 6.
iii.
(1 X 2) + (2 X 3) + (1 X 4) = 2 + 6 + 4 =12. The carried over 1 of above step

is added.i.e., 12 + 1 = 13. Now 3 is retained and 1 is carried over to left side.
Thus third digit = 3.
iv.
( 1X 3 ) + ( 2 X 1 ) = 3 + 2 = 5. the carried over 1 of above step is added

i.e., 5 + 1 = 6 . It is retained. Thus fourth digit = 6
v.
( 1 X 1 ) = 1. As there is no carried over number from the previous step it is

retained.
Thus fifth digit = 1

124 X 132 = 16368.

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Let us work another problem by placing the carried over digits under the first row and
proceed.
234
X 316
61724
1222
73944
i.
4 X 6 = 24 : 2, the carried over digit is placed below the second digit.
ii.
(3 X 6) + (4 x 1) = 18 + 4 = 22; 2, the carried over digit is placed below
iii. (2 X 6) + (3 X 1) + (4 X 3) = 12 + 3 + 12 = 27; 2, the carried over digit is placed below

fourth digit.
iv. (2 X 1) + ( 3 X 3) = 2 + 9 = 11; 1, the carried over digit is placed below fifth digit.
v.
(2 X 3 ) = 6.
vi. Respective digits are added.
Note :
1.
We can carry out the multiplication in Urdhva - Tiryak process from left to right or right
to left.
2.
The same process can be applied even for numbers having more digits.
3.
Urdhva Tiryak process of multiplication can be effectively used in multiplication

regarding algebraic expressions.
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CHAPTER 3
LITERATURE SURVEY 2
(Reversible Logical Gates)
3.1. INTRODUCTION
Reversible logic is one of the most vital issue at present time and it has different areas
for its application, those are low power CMOS, quantum computing, nanotechnology,
cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum
dot cellular automata, communication, computer graphics. It is not possible to realize
quantum computing without implementation of reversible logic. The main purposes of
designing reversible logic are to decrease quantum cost, depth of the circuits and the number
of garbage outputs. This paper provides the basic reversible logic gates, which in designing of
more complex system having reversible circuits as a primitive component and which can
execute more complicated operations using quantum computers.
The reversible circuits form the basic building block of quantum computers as all
quantum operations are reversible. Reversible logic is one of the promlsmg fields for future
low power design technologies. Since one of the requirements of all DSP processors and
other hand held devices is to minimize power dissipation multipliers with high speed and
lower dissipations are critical.Energy dissipation is one of the major issues in present day
technology. Energy dissipation due to information loss in high technology circuits and
systems constructed using irreversible hardware was demonstrated by R. Landauer in the year
1960. According to Landauers principle, the loss of one bit of information lost, will dissipate
kT*ln (2) joules of energy where, k is the Boltzmanns constant and k=1.38x10 -23 J/K, T is
the absolute temperature in Kelvin.
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The primitive combinational logic circuits dissipate heat energy for every bit of
information that is lost during the operation. This is because according to second law of
thermodynamics, information once lost cannot be recovered by any methods. In 1973,
Bennett, showed that in order to avoid kTln2 joules of energy dissipation in a circuit it must
be built from reversible circuits.
According to Moores law the numbers of transistors will double every 18 months.
Thus energy conservative devices are the need of the day. The amount of energy dissipated in
a system bears a direct relationship to the number of bits erased during comput ation.
Reversible circuits are those circuits that do not lose information. The most prominent application of
reversible logic lies in quantum computers. A quantum computer will be viewed as a quantum
network (or a family of quantum networks) composed of quantum logic gates; It has applications in
various research areas such as Low Power CMOS design, quantum computing, nanotechnology and
DNA computing.
Quantum networks composed of quantum logic gates; each gate performing an

elementary unitary operation on one, two or more twostate quantum systems called qubits.
Each qubit represents an elementary unit of information; corresponding to the classical bit
values 0 and 1. Any unitary operation is reversible and hence quantum networks effecting
elementary arithmetic operations such as addition, multiplication and exponentiation cannot
be directly deduced from their classical Boolean counterparts (classical logic gates such as
AND or OR are clearly irreversible).Thus, quantum arithmetic must be built from reversible
logical components. Reversible computation in a system can be performed only when the
system comprises of reversible gates.
A circuit/gate is said to be reversible if the input vector can be uniquely recovered

from the output vector and there is a one-to-one correspondence between its input and output
assignments.
An N*N reversible gate can be represented as
Iv=(I1, I2, I3,IN)

Ov=(O1, O2, O3,.ON).
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Where Iv and Ov represent the input and output vectors respectively.
In quantum computing, by considering the need of reversible gates, a literature survey has
been done and the mostly available reversible logic gates are presented in this paper.
3.2. Definitions Pertaining To Reversible Logic

3.2.1 Reversible Function:
The multiple output Boolean function F(x1; x2;..; xn) of n Boolean
variables is called reversible if:
a.
The number of outputs is equal to the number of inputs;
b.
Any output pattern has a unique pre-image

In other words, reversible functions are those that perform permutations of the
set of input vectors.
3.2.2 Reversible logic gate:
Reversible Gates are circuits in which number of outputs is equal to the

number of inputs and there is a one to one correspondence between the vector of
inputs and outputs. It not only helps us to determine the outputs from the inputs but
also helps us to uniquely recover the inputs from the outputs.
3.2.3 Ancilla inputs/ constant inputs:

This refers to the number of inputs that are to be maintaining constant at either
0 or 1 in order to synthesize the given logical function.
3.2.4 Garbage outputs:

Additional inputs or outputs can be added so as to make the number of inputs
and outputs equal whenever necessary. This also refers to the number of outputs
which are not used in the synthesis of a given function. In certain cases these become
mandatory to achieve reversibility. Garbage is the number of outputs added to make
an n-input k-output function ((n; k) function) reversible.
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We use the words constant inputs to denote the present value inputs that
were added to an (n; k) function to make it reversible. The following simple formula
shows the relation between the number of garbage outputs and constant inputs.
Input + constant input = output + garbage.
3.2.5 Quantum cost:

Quantum cost refers to the cost of the circuit in terms of the cost of a primitive
gate. It is calculated knowing the number of primitive reversible logic gates (1*1 or
2*2) required to realize the circuit. The quantum cost of a circuit is the minimum
number of 2*2 unitary gates to represent the circuit keeping the output unchanged.
The quantum cost of a 1*1 gate is 0 and that of any 2*2 gate is the same, which is 1.
3.2.6 Flexibility:
Flexibility refers to the universality of a reversible logic gate in realizing more
functions.
3.2.7 Gate Level:

This refers to the number of levels in the circuit which are required to realize
the given logic functions.
3.2.8 Hardware Complexity:

This refers to the total number of logic operation in a circuit. Means the total
number of AND, OR and EXOR operation in a circuit.
3.3 Design Constraints for Reversible Logic Circuits

The following are the important design constraints for reversible logic circuits.
Reversible logic gates do not allow fan-outs.
Reversible logic circuits should have minimum quantum cost.
The design can be optimized so as to produce minimum number of garbage outputs.
The reversible logic circuits must use minimum number of constant inputs.
The reversible logic circuits must use a minimum logic depth or gate levels
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There are many number of reversible logic gates that exist at present. The quantum
cost of each reversible logic gate is an important optimization parameter. The quantum cost
of a 1x1 reversible gate is assumed to be zero while the quantum cost of a 2x2 reversible
logic gate is taken as unity.
The quantum cost of other reversible gates is calculated by counting the number of V,
V+ and CNOT gates present in their circuit. V is the square root of NOT gate and V+ is its
Hermitian. The V and V+ quantum gates have the following properties:
V * V = NOT . (1)
V * V+ = V+ * V = 1 . (2)
V+ * V+ = NOT . (3)
Some of the important reversible logic gates are,
3.4.1 CNOT Gate:
CNOT gate is also known as controlled-not gate. It is a 2*2 reversible gate. The
CNOT gate can be described as:
Iv = (A, B);
Ov= (P= A, Q= A B)
Iv and Ov are input and output vectors respectively. Quantum cost of CNOT gate is Figure 3.1
shows a 2*2 CNOT gate and its symbol.
Page 23
Figure 3.1: Circuit & Logical symbols of CNOT Gate
3.4.2 Fredkin Gate

Reversible 3*3 gate maps inputs (A, B, C) to outputs (P=A, Q=A'B+AC, R=AB+A'C)
having Quantum cost of 5 and it requires two dotted rectangles, is equivalent to a 2*2
Feynman gate with Quantum cost of each dotted rectangle is 1, 1 V and 2 CNOT gates as
shown in figure 3.2
Figure 3.2: Circuit &Logical symbol of Fredkin Gate
3.4.3 Peres Gate

It is a 3x3 gate and its logic circuit is as shown in the figure. It has quantum cost four.
It is used to realize various Boolean functions such as AND, XOR as shown in figure 3.3.
Page 24
Figure 3.3. Circuit &Logical symbol of Peres Gate
3.4.4 HNG Gate

It is a 4x4 gate and its logic circuit is as shown in the figure 3.3 & 3.4. It has quantum
cost six. It is used for designing ripple carry adders. It can produce both sum and carry in a
single gate thus minimizing the garbage and gate counts.
Figure 3.3 Logical symbol of HNG Gate
Page 25
Figure 3.4: Circuit symbol of HNG Gate
CHAPTER 4
MULTIPLIER TECHNIQUES
The common multiplication method is add and shift algorithm. In parallel
multipliers number of partial products to be added is the main parameter that determines the
performance of the multiplier. To reduce the number of partial products to be added,
Modified Booth algorithm is one of the most popular algorithms. To achieve speed
improvements Wallace Tree algorithm can be used to reduce the number of sequential adding
stages. Further by combining both Modified Booth algorithm and Wallace Tree technique we
can see advantage of both algorithms in one multiplier. However with increasing parallelism,
the amount of shifts between the partial products and intermediate sums to be added will
increase which may result in reduced speed, increase in silicon area due to irregularity of
structure and also increased power consumption due to increase in interconnect resulting
from complex routing. On the other hand serial-parallel multipliers compromise speed to
achieve better performance for area and power consumption. The selection of a parallel or
serial multiplier actually depends on the nature of application. In this lecture we introduce the
multiplication algorithms and architecture and compare them in terms of speed, area, power
and combination of these metrics.
4.1 MULTIPLICATION ALGORITHM

The multiplication algorithm for an N bit multiplicand by N bit multiplier is shown below:
Y= Yn-1 Yn-2 ........................Y2 Y1 Y0 Multiplicand
Page 26
X= Xn-1 Xn-2 ..................... X2 X1 X0 Multiplier
Figure 4.1 Multiplication of 4x4 multiplier

Generally AND gates are used to generate the Partial Products, PP, If the multiplicand
is N-bits and the Multiplier is M-bits then there is N* M partial product. The way that the
partial products are generated or summed up is the difference between the different
architectures of various multipliers. Multiplication of binary numbers can be decomposed
into additions. Consider the multiplication of two 8-bit numbers A and B to generate the 16
bit product P.
Figure 4.2 Partial products of 4x4 multiplier

The equation of addition is
Page 27
Multiplication Algorithm
If the LSB of Multiplier is 1, then add the multiplicand into an accumulator.
Shift the multiplier one bit to the right and multiplicand one bit to the left.
Stop when all bits of the multiplier are zero.
From above it is clear that the multiplication has been changed to addition of
numbers. If the Partial Products are added serially then a serial adder is used with least
hardware. It is possible to add all the partial products with one combinational circuit using a
parallel multiplier. However it is possible also, to use compression technique then the number
of partial products can be reduced before addition .is performed.
4.2 SERIAL MULTIPLIER
Where area and power is of utmost importance and delay can be tolerated the serial
multiplier is shown in figure 2.1. This circuit uses one adder to add the m * n partial products.
The circuit is shown in the fig. below for m=n=4. Multiplicand and Multiplier inputs have to
be arranged in a special manner synchronized with circuit behavior as shown on the figure.
The inputs could be presented at different rates depending on the length of the multiplicand
and the multiplier. Two clocks are used, one to clock the data and one for the reset. A first
order approximation of the delay is O (m,n). With this circuit arrangement the delay is given
as D =[ (m+1)n + 1 ] tfa.
Figure 4.3. Serial Multiplier

Page 28
4.3 SERIAL/PARALLEL MULTIPLIER
The general architecture of the serial/parallel multiplier is shown in the below figure
2.2. One operand is fed to the circuit in parallel while the other is serial. N partial products
are formed each cycle. On successive cycles, each cycle does the addition of one column of
the multiplication table of M*N PPs.The final results are stored in the output register after
N+M cycles. While the area required is N-1 for M=N. For snapshots of data transfer through
this multiplier please see the course website/slides of lecture.
Figure 4.4: Serial/Parallel Multiplier
4.4 ARRAY MULTIPLIER
In Array multiplier, AND gates are used for generation of the bit-products and adders
for accumulation of generated bit products. All bit-products are generated in parallel and
collected through an array of full adders or any other type of adders as shown in figure 2.2.
Since the array multiplier is having a regular structure, wiring and the layout are done in a
much simplified manner. Therefore, among other multiplier structures, array multiplier takes
up the least amount of area. But it is also the slowest with the latency proportional to O(Wct),
where Wd is the word length of the operand.
Page 29
Figure 2.3: Array Multiplier

Page 30
4.5 BOOTH MULTIPLIERS
It is a powerful algorithm for signed-number multiplication, which treats both positive

and negative numbers uniformly. For the standard add-shift operation, each multiplier bit generates
one multiple of the multiplicand to be added to the partial product. If the multiplier is very large, then
a large number of multiplicands have to be added. In this case the delay of multiplier is determined
mainly by the number of additions to be performed. If there is a way to reduce the number of the
additions, the performance will get better.
Booth algorithm is a method that will reduce the number of multiplicand multiples.
For a given range of numbers to be represented, a higher representation radix leads to fewer
digits.
Since a k-bit binary number can be interpreted as K/2-digit radix-4 number, a K/3digit radix-8 number, and so on, it can deal with more than one bit of the multiplier in each
cycle by using high radix multiplication. This is shown for Radix-4 in the example below.
Zi = -2xi+1 + xi + xi-1
4.6 WALLACE TREE MULTIPLIER
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Several popular and well-known schemes, with the objective of improving the speed
of the parallel multiplier, have been developed in past. Wallace introduced a very important
iterative realization of parallel multiplier. This advantage becomes more pronounced for
multipliers of bigger than 16 bits.
In Wallace tree architecture, all the bits of all of the partial products in each column
are added together by a set of counters in parallel without propagating any carries. Another
set of counters then reduces this new matrix and so on, until a two-row matrix is generated.
The most common counter used is the 3:2 counters which is a Full Adder. The final results
are added using usually carry propagate adder. The advantage of Wallace tree is speed
because the addition of partial products is now O (log N).
A block diagram of 4 bit Wallace Tree multiplier is shown in below. As seen from the
block diagram partial products are added in Wallace tree block. The result of these additions
is the final product bits and sum and carry bits which are added in the final fast adder (CRA).
Page 32
Figure 4.7: Wallace Tree Multiplier

4.7 URDHAVA MULTIPLIER
In Urdhava Tiryakbhyam is a Sanskrit word which means vertically and crosswire in

English. The method is a general multiplication formula applicable to all cases of
multiplication. It is based on a novel concept through which all partial products are generated
concurrently. Fig. Demonstrates a 4 x 4 binary multiplication using this method. The method
can be generalized for any N x N bit multiplication.
This type of multiplier is independent of the clock frequency of the processor because
the partial products and their sums are calculated in parallel. The net advantage is that it
reduces the need of microprocessors to operate at increasingly higher clock frequencies.
Page 33
As the operating frequency of a processor increases the number of switching instances

also increases. This results more power consumption and also dissipation in the form of heat
which results in higher device operating temperatures. Another advantage of Urdhava
Tiryakbhyam multiplier is its scalability T.
Figure 4.8: Cross Multiplication of URDHAVA MULTIPLIER
The processing power can easily be increased by increasing the input and output data
bus widths since it has a regular structure. Due to its regular structure, it can be easily layout
in a silicon chip and also consumes optimum area. As the number of input bits increase, gate
delay and area increase very slowly as compared to other multipliers. Therefore Urdhava
Tiryakbhyam multiplier is time, space and power efficient.
Page 34
Figure 4.9: Example of URDHAVA MULTIPLIER

The line diagram in figure 2.5 illustrates the algorithm for multiplying two 4-bit
binary numbers a3, a2, a1, a0 and b3, b2, b1, b0. The procedure is divided into 7 steps and
each step generates partial products. Initially as shown in step 1 of figure 2.6, the least
significant bit (LSB) of the multiplier is multiplied with least significant bit of the
multiplicand (vertical multiplication). This result forms the LSB of the product. In step 2 next
higher bit of the multiplier is multiplied with the LSB of the multiplicand and the LSB of the
multiplier is multiplied with the next higher bit of the multiplicand (crosswire multiplication).
These two partial products are added and the LSB of the sum is the next higher bit of
the final product and the remaining bits are carried to the next step. For example, if in some
intermediate step, we get the result as 1101, then 1 will act as the result bit (referred as rn)
and 110 as the carry (referred as cn). Therefore cn may be a multi-bit number. Similarly other
steps are carried out as indicated by the line diagram. The important feature is that all the
partial products and their sums for every step can be calculated in parallel.
CHAPTER 5
Page 35
VEDIC MULTIPLIER URDHVA TIRYAKBHAYAM

Multiplier design is always a challenging task; how many ever novel designs
are proposed, the user needs demands much more optimized ones. Vedic mathematics is
world renowned
for
its
algorithms
that
yield quicker
results, be
it
for mental
calculations or hardware design. Power dissipation is drastically reduced by the use of

Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such
multiplier which is effective both in terms of speed and power. In this paper we aim to
enhance the performance of the previous design. The Total Reversible Logic Implementation
Cost (TRLIC) is used as an aid to evaluate the proposed design. This multiplier can be
efficiently adopted
in designing Fast Fourier Transforms (FFTs) Filters
and
other
applications of DSP like imaging, software defined radios, wireless communications.
Vedic Mathematics is one of the most ancient methodologies used by the Aryans in
order to perform mathematical calculations. This consists of algorithms that can boil down
large arithmetic operations to simple mind calculations. The above said advantage stems from
the fact that Vedic mathematics approach is totally different and considered very close to the
way a human mind works. The efforts put by Jagadguru Swami Sri Bharati Krishna Tirtha
Maharaja to introduce Vedic Mathematics to the commoners as well as streamline Vedic
Algorithms into 16 categories or Sutras needs to be acknowledged and appreciated. The
Urdhva Tiryakbhayam is one such multiplication algorithm which is well known for its
efficiency in reducing the calculations involved. With the advancement in the VLSI
technology, there is an ever increasing quench for portable and embedded Digital Signal
Processing (DSP) systems. DSP is omnipresent in almost every engineering discipline. Faster
additions and multiplications are the order of the day.
Multiplication is the most basic and frequently used operations in a CPU.

Multiplication is an operation of scaling one number by another. Multiplication operations
also form the basis for other complex operations such as convolution, Discrete Fourier
Transform, Fast Fourier Transforms, etc. With ever increasing need for faster clock
frequency it becomes imperative to have faster arithmetic unit.
Therefore, DSP engineers are constantly looking for new algorithms and hardware to
implement them. Vedic mathematics can be aptly employed here to perform multiplication.
Page 36
Another important area which any DSP engineer has to concentrate is the power dissipation,
the first one being speed. There is always a tradeoff between the power dissipated and speed
of operation. The reversible computation is one such field that assures zero power dissipation.
Thus during the design of any reversible circuit the delay is the only criteria that has to be
taken care of. Urdhva Tiryakbhayam (UT) is a multiplier based on Vedic mathematical
algorithms devised by ancient Indian Vedic mathematicians. Urdhva Tiryakbhayam sutra can
be applied to all cases of multiplications viz. Binary, Hex and also Decimals. It is based on
the concept that generation of all partial products can be done and then concurrent addition of
these partial products is performed. The parallelism in generation of partial products and their
summation is obtained using Urdhva Tiryakbhayam.
Unlike other multipliers with the increase in the number of bits of multiplicand and/or
multiplier the time delay in computation of the product does not increase proportionately.
Because of this fact the time of computation is independent of clock frequency of the
processor Hence one can limit the clock frequency to a lower value. Also, since processors
using lower clock frequency dissipate lower energy, it is economical in terms of power factor
to use low frequency processors employing fast algorithms like the above mentioned. The
Multiplier based on this sutra has the advantage that as the number of bits increases, gate
delay and area increases at a slow pace as compared to other conventional multipliers.
5.1 CONVENTIONAL MULTIPLIER

The digital logic implementation of the 2X2 Urdhva Tiryakbhayam multiplier using
the conventional logic gates as shown in figure 5.1
Figure 5.1 Conventional Multiplier

The expressions for the four output bits are given under.
q0= a0.b0
Page 37
ql= (a1.b0) xor (a0.bl)

q2= ((a0.al) and (b0.bl)) xor (al.bl)
q3= a0.al.b0.bl
5.2 DESIGN OF 2*2 URDHVA TIRYABHAYAM MULTIPLIER
The digital logic implementation of the 2X2 Urdhva Tiryakbhayam multiplier using
the Reversible logic gates is as shown in figure 5.2. This design does not consider the
fanouts. The circuit requires a total of six reversible logic gates out of which five are Peres
gates and remaining one is the Feynman Gate. The quantum cost of the 2X2 Urdhva
Tiryakbhayam Multiplier is enumerated to be 21. The number of garbage outputs is 9 and
number of constant inputs is 4.
Figure 5.2: 2X2 Urdhva Tiryakbhayam Multiplier
The algorithm steps for 2X2 Urdhva Tiryakbhayam Multiplier using cross
multiplication of 2bits as shown in figure 5.3.
Page 38
Figure 5.3: Cross Multiplication of 2X2 Multiplier
The Algorithm: Multiplication of 10 by 11.

1.
We will take the right-hand digits and multiply them together. This will give us LSB
digit of the answer.
2.
Multiply LSB digit of the top number by the second bit of the bottom number and
the LSB of the bottom number by the second bit of the top number. Once we have
those values, add them together.
3.
Multiply the LSB digit of bottom number with the MSB digit of the top one, LSB
digit of top number with the MSB digit of bottom and then multiply the second bit of
both, and then add them all together.
4.
This step is similar to the second step, just move one place to the left. We will
multiply the second digit of one number by the MSB of the other number.
5.
Finally, simply multiply the LSB of both numbers together to get the final product.
5.3 DESIGN OF 4X4 URDHVA TIRYAKBHAYAM MULTIPLIER
The Reversible 4X4 Urdhva Tiryakbhayam Multiplier design emanates from the 2X2
multiplier. The block diagram of the 4X4 Vedic Multiplier is presented in the figure 5.4.It
consists of four 2X2 multipliers each of which procures four bits as inputs; two bits from the
multiplicand and two bits from the multiplier. The lower two bits of the output of the first
2X2 multiplier are entrapped as the lowest two bits of the final result of multiplication. Two
zeros are concatenated with the upper two bits and given as input to the four bit ripple carry
adder. The other four input bits for the ripple carry adder are obtained from the second 2X2
multiplier. Likewise the outputs of the third and the terminal 2X2 multipliers are given as
inputs to the second four bit ripple carry adder.
Page 39
The outputs of these four bit ripple carry adders are in turn 5 bits each which need to
be summed up. This is done by a five bit ripple carry adder which generates a six bit output.
These six bits form the upper bits of the final result.
Figure 5.4: 4X4 Urdhva Tiryakbhayam Multiplier
5.3.1 Modification in the design of ripple carry adder
The design shown in figure 5.5 consists of only HNG gates. The number of HNG
gates is 4 if the ripple carry adder is used in the second stage or five if the ripple carry adder
is used in the last stage of the 4X4 Urdhva Tiryakbhayam Multiplier. The ripple carry adder
can be modified as under. Since for any ripple carry adder the input carry for the first full
adder is zero, this implicitly means the first adder is a half adder.
Thus a Peres gate can efficiently replace a HNG. This cut down the quantum cost by
two for any ripple carry adder and the garbage output by one. The Constant inputs and the
gate count remain unchanged.
Page 40
Figure 5.5: Design of 4 bit ripple carry adder

The design shown in figure 5.6 consists of only HNG gates. The number of HNG
gates is 5 if the ripple carry adder is used in the second stage or five if the ripple carry adder
is used in the last stage of the 4X4 Urdhva Tiryakbhayam Multiplier. The ripple carry adder
can be modified as under. Since for any ripple carry adder the input carry for the first full
adder is zero, this implicitly means the first adder is a half adder. Thus a Peres gate can
efficiently replace a HNG. This cut down the quantum cost by two for any ripple carry adder
and the garbage output by one. The Constant inputs and the gate count remain unchanged.
Figure 5.6: Design of 5 bit ripple carry adder

5.3.2 Algorithm for 4X4 Urdhva Tiryakbhayam Multiplier
The algorithm steps for 4X4 Urdhva Tiryakbhayam Multiplier using cross
multiplication of 4bits as shown in figure 5.7.
Page 41
Figure 5.7: Cross Multiplication of 4X4 Multiplier
The Algorithm: Multiplication of 1100 by 0101.

1.
We will take the right-hand digits and multiply them together. This will give us LSB
digit of the answer.
2.
Multiply LSB digit of the top number by the second bit of the bottom number and the
LSB of the bottom number by the second bit of the top number. Once we have those
values, add them together.
3.
Multiply the LSB digit of bottom number with the MSB digit of the top one, LSB digit of
top number with the MSB digit of bottom and then multiply the second bit of both, and
then add them all together.
4.
This step is similar to the second step, just move one place to the left. We will multiply
the second digit of one number by the MSB of the other number.
5.
Finally, simply multiply the LSB of both numbers together to get the final product.
Page 42
CHAPTER 6
SIMULATION RESULTS
The code is divided into modules which do some application specific functions. These
modules are instantiated and used by the main module. This chapter focuses on the
simulation waveforms of different modules, synthesis reports and power consumption of
various multiplier techniques etc. This chapter also contains the RTL schematics of the main
module and their top level results. The various multiplier techniques comparison results are
also depicted.
6.1 Multiplier 2 X 2 Bit
By using Xilinx tools such as Xilinx 13.1 version, X-Simulator and X-Power analysis
are placed on Spartan 3E FPGA kit. The top level module with input and output signals of the
proposed 2bit multiplier is shown in Figure 6.1. 2bit multiplier has two input and four output
interfacing signals.
Figure: 6.1 2 X 2 Bit Multiplier
The RTL schematic of proposed 2 X 2 multiplier consists of two reversible logical gates such
as five peres gate and one cnot gate as shown in figure 6.2.
Page 43
Figure: 6.2 Multiplier 2 X 2 Bit

Inputs and Outputs are generated using VHDL test bench. The simulation result for 2-bit
multiplier is shown in the Figure 6.3.
Figure 6.3: Simulation Results for 2 X 2 Multiplier

Page 44
Consider some example as follows

CASE - 1: Inputs a = 01, b = 01
Product z = 0001
CASE - 2: Inputs a = 10, b = 10
Product p = 0100
CASE - 3: Inputs a = 11, b = 11
6.2 RC ADDER 4BIT

The top level module with input and output signals of the proposed 4bit ripple carry
adder is shown in Figure 5.4. 4bit ripple carry adder has four input and five output interfacing
signals.
Figure 6.4: RC Adder 4Bit

The RTL schematic of proposed 4 bit ripple carry adder consists of one reversible logical
gates such as four HNG gate as shown in figure 6.5.
Page 45
Figure 6.5: RTL Schematic of RC Adder 4bit

Inputs and Outputs are generated using VHDL test bench. The simulation result for 4 bit rc
adder is shown in the Figure 6.6.
Figure 6.6: Simulation Results for 4 bit rc adder
Consider some examples as follows

CASE - 1: Inputs a [3:0] = 0000, b [3:0] = 0000
Sum & Carry f [4:0] = 00000
Page 46
CASE - 2: Inputs a [3:0] = 1100, b[3:0] = 1011

Sum & Carry f [4:0] = 10111
CASE - 3: Inputs a [3:0] = 1111, b [3:0] = 1111
Sum & Carry f [4:0] = 11110
6.3 RC ADDER 5BIT

The top level module with input and output signals of the proposed 5bit ripple carry adder is
shown in Figure 5.7. 5bit ripple carry adder has five input and six output interfacing signals.
Figure 6.7: RC Adder 5Bit

The internal RTL diagram of the 5bit adder was shown in figure 6.8.
Figure 6.8: RTL Schematic of RC Adder 5bit

Page 47
Inputs and Outputs are generated using VHDL test bench. The simulation result for 5 bit rc
adder is shown in the Figure 6.9.
Consider some examples as follows
CASE - 1: Inputs a [4:0] = 0001, b [4:0] = 0010
Sum & Carry f [5:0] = 000011
CASE - 2: Inputs a [4:0] = 00100, b [4:0] = 01001
Sum & Carry f [4:0] = 001101
CASE - 3: Inputs a [3:0] = 11111, b [3:0] = 11111
Sum & Carry f [4:0] = 111110
Figure 6.9: Simulation Results for 5 bit rc adder
6.4 MULTIPLIER 4 X 4 Bit

The top level module with input and output signals of the proposed 4 X 4 proposed multiplier
using reversible logical gates is shown in Figure 6.10. 5bit ripple carry adder has four input
and eight output interfacing signals.
Page 48
Figure: 6.10 4 X 4 Bit Multiplier

The RTL schematic of proposed 4 bit multiplier consists of four 2 X 2 multiplier, two 4bit rc
adder and one 5bit rc adder as shown in figure 6.11.The internal RTL diagram of the 4bit
multiplier was shown in figure 6.11.
Figure: 6.11 Multiplier 4 X 4 Bit
Inputs and Outputs are generated using VHDL test bench. The simulation result for proposed
multiplier is shown in the Figure 6.12.
Page 49
Figure 6.12: Simulation Results for 4 X 4 Multiplier
FPGA and verified for possible inputs given below. Inputs are generated using VHDL test
bench. The simulation result for 4-bit multiplier is shown in the Figure 12.
CASE - 1: Inputs a = 0101, b = 0010
Product z = 00001010
CASE - 2: Inputs a = 1111, b = 0011
Product z = 00101101
In the figure 5.13 the comparison of different multiplier techniques with proposed
multiplier (Urdhva tryaakbhayam) using reversible logical gates related to the power, Delay,
Speed and Area were specified.
Figure 6.13: Comparison of Various Multiplier Techniques

Page 50
Comparison different parameters of Proposed and Existing multiplier techniques were

shown in table 6.1.
Table 6.1
Comparison of Various Multiplier Techniques with the proposed Multiplier Technique
Page 51
CONCLUSION
In this project presents realizing a high speed, low power multiplier using Urdhva
Tiryagbhyam sutra implemented in reversible logical gates. A 4-bit modified multiplier is
designed. The 4-bit multiplier is realized using four 2-bit Vedic multipliers and modified
ripple carry adders using reversible logical gates. Ripple carry adders are modified because
not all bits have same weight and hardware can be reduced by reducing the number of full
adders used. Though the number of gates used is fairly high, the increase in speed
compensates for the increase in area. The proposed 4-bit multiplier gives a total delay of
9.418 ns and power is 81mW which is less when compared to the total delay and power of
any other renowned multiplier architecture.
Page 52
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Page 54
APPENDIX
PAPER PUBLICATIOS RELATED WORK
Sainadh chintha, Ch. Tirupathi Rao, FPGA Implementation of Fast and Power
Efficient 4 Bit Vedic Multiplier (Urdhva Tiryakbhayam) using Reversible Logical
Gate International Journal of IT, Engineering and Applied Sciences Research
(IJIEASR) ISSN: 2319-4413 Volume 3, No. 10, October 2014.
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A FINAL PROJECT REPORT

(Affiliated to Jawaharlal Nehru Technological University)

NOVA COLLEGE OF ENGINEERING

NOVA COLLEGE OF ENGINEERING

RATNARAJU KATARAPU (13KK1D6817) partial fulfillment of the requirement

Mr. P. SUDHAKAR RAO

External Viva-Voce held on dated:__________________________

NOVA COLLEGE OF ENGINEERING

VENKATA RATNARAJU KATARAPU (13KK1D6817)

NOVA COLLEGE OF ENGINEERING

NOVA COLLEGE OF ENGINEERING

1.1 Existing Multiplier Technology

1.2 Proposed Multiplier

1.3 Reversible Logic Gates

1.4 Literature Survey

1.5 Thesis Organization

CHAPTER 2: VEDIC MATHEMATICS

CHAPTER 3: LITERATURE SURVEY

3.2 Definition Pertaining To Reversible Logic

3.2.1 Reversible Function

3.4 Reversible Logic Gates

3.4.1 CNOT Gate

4.1 Multiplication Algorithm

4.2 Serial Multiplier

4.3 Parellel Multiplier

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4.4 Array Multiplier

4.5 Booth Multiplier

4.6 Wallace Multiplier

4.7 Urdva Multiplier

CHAPTER 5: VEDIC MULTIPLIER URDVA TIRYAKBAYAM LOGIC 29

5.2 UT 2x2 Multiplier

5.3 UT 4x4 Multiplier

CHAPTER 6: SIMULATION RESULT

6.1 Multiplier 2x2 Bit

6.2 RC Adder 4 Bit

6.3 RC Adder 5 Bit

6.4 Multiplier 4x4 Bit

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Fig 3.2 Circuit Logic Symbol of FREDKIN Gate

Fig 3.3 Circuit Logic Symbol of PERES Gate

Fig 3.4 Circuit Logic Symbol of HNG Gate

Fig 4.1 Multiplication of 4x4 Multiplier

Fig 4.2 Partial Products of 4x4 Multiplier

Fig 4.3 Serial Multiplier

Fig 4.4 Serial/Parellel Multiplier

Fig 4.5 Array Multiplier

Fig 4.6 Booth Multiplier

Fig 4.7 Wallce Tree Multipler

Fig 4.8 Cross Multiplication of UT Multiplier

Fig 4.9 Example of UT Multiplier

Fig 5.1 Conventional Multiplier

Fig 5.2 UT 2x2 Multiplier

Fig 5.3 Cross Multiplication of 2x2 UT Multiplier

Fig 5.4 UT 4x4 Multiplier

Fig 5.5 Design of 4 bit RC Adder

Fig 5.6 Design of 5 bit RC Adder

Fig 5.7 Cross Multiplication of 2x2 UT Multiplier

Fig 6.1 2x2 Bit Multipler

Fig 6.2 RTL Schematic of 2x2 Bit Multiplier

Fig 6.3 Simulation Result of 2x2 Multiplier

Fig 6.4 RC Adder 4 Bit

Fig 6.5 RTL Schematic of 4 Bit RC Adder

Fig 6.6 Simulation Result of 4 Bit RC Adder