THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

ECNG 2004
LABORATORY & PROJECT DESIGN II
http://myelearning.sta.uwi.edu/course/view.php?id=1678
Semester I, 2009/2010

1. GENERAL INFORMATION
Lab #:
Name of the Lab:

DIGLAB3
Design of Modulo Counters

Lab Weighting:

5 % [TOTAL = 32 MARKS] Estimated total

study hours1:
Lecture
Online
; Lab
Other

Delivery mode:

Venue for the Lab:

Electronics Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 1014

Theoretical content link: http://myelearning.sta.uwi.edu/
Pre-Requisites None
Use Xilinx Schematic Editor to implement simple digital circuits.

Recommended
prior knowledge
and skills3:

Course Staff

Position/Role

Marcus L George Instructor

E-mail
Phone
Office


Marcus.George@uwi.sta.edu ext3164 Electronics
Lab Office

Office
Hours
Fridays
10am - 1pm

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

2. LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Implementation of a 4-bit binary counter macro using a Xilinx schematic

Cognitive
Level
C, Ap

editor.
2. Implementations of a 1-digit BCD counter macro using a Xilinx schematic

C, Ap

editor.
3. Implementation of a 2.5MHz frequency divider using the 1-digit BCD

C, Ap

counter and positive edge triggered D Flip-Flips

4. Design and implement a frequency divider to meet a required specification

Ap

DIGLAB3: Design of Modulo Counters

3. PRE-LAB
Due Date:

Must submitted with the post-lab report

Submission
Procedure:

Must be submitted with the post-lab report. Make sure it is properly

Estimated time to
completion:

30 minutes

attached to the post lab report.

3.1. Required Reading Resources

Digital Design Principles and Practices, by John F. Wakerly
3.2. Reading Exercise
Using suitable reading resources (ECNG1014 notes, recommended books, internet, etc) research
and understand the following topics .

Modulo Counter

Binary Counter

BCD Counter

Frequency Divider

1kHz Frequency Divider

Make sure to fully understand the implementation of these digital circuits using logic gates. Also
read through the laboratory manual for DIGLAB3 to understand how these circuits may have
been utilized.

3.3. Computation Exercise

The reference clock frequency for the Spartan 3 FPGA board is 50MHz. Before we can
implement frequency dividers to produce smaller frequencies from this 50MHz, we must first

DIGLAB3: Design of Modulo Counters

calculate the value of N for the counter to be use in the implementation of this frequency
divider. The following equation is crucial to this calculation.
For the modulo counter N = a

reference
required

freference = 50MHz
frequired = desired frequency

3.3.1.

Calculate the value of N for a modulo N counter. This must be used by a frequency
divider to produce a 2.5MHz clock signal using the 50MHz reference clock signal.
Show all working.

3.3.2.

Calculate the value of N for a modulo N counter. This must be used by a frequency
divider to produce a 1kHz clock signal using the 50MHz reference clock signal. Show
all working.

3.3.3.

What is the output frequency of a frequency divider that utilizes the 50MHz reference
clock signal and a modulo 500,000 counter? Show all working.

DIGLAB3: Design of Modulo Counters

4. IN-LAB
Allotted Completion 3 hours
Time:
1 printed copy of the digital lab3 manual (students must bring to the lab)
Required lab
Equipment:
1 Computer

4.1. Objectives
In this laboratory exercise Xilinx Schematic Editor will be used to investigate the
implementation of modulo counters(binary and BCD counters) and frequency dividers. This
laboratory exercise is broken up into three components:
i. Implementation of a 4-bit binary counter macro using a Xilinx schematic editor.
ii. Implementations of a 1-digit BCD counter macro using a Xilinx schematic editor.
iii. Creation of the desired frequency divider using the 1-digit BCD counter and positive
edge triggered D Flip-Flips(create a frequency divider capable of dividing the reference
clock signal(50MHz) by 20)..

Lab #3: Design of Modulo Counters

4.2. Implementation of a 4-bit binary counter macro using a Xilinx schematic editor.
4.2.1.

Use the Xilinx Schematic Editor to create a 4-bit counter binary counter as shown in
figure 1 below.

4.2.2.

Synthesize and implement the 4-bit binary counter.

4.2.3.

Create a new test bench waveform and simulate both the functional and timing behavior
of the 4-bit binary counter created.

4.2.4.

Create a macro for the 4-bit binary counter.

Figure 1: Schematic for the 4-bit Binary Counter

Lab #3: Design of Modulo Counters

4.3. Implementation of a 1-digit BCD counter macro using the Xilinx Schematic Editor.
4.3.1.

Use the Xilinx Schematic Editor to create a 1-digit BCD counter as shown in figure 2
below.

4.3.2.

Synthesize and implement the 1-digit BCD counter.

4.3.3.

Create a new test bench waveform and simulate both the functional and timing behavior
of the 1-digit BCD created.

4.3.4.

Create a macro for the 1-digit BCD counter.

Figure 2: Schematic for the 1-digit BCD Counter

Lab #3: Design of Modulo Counters

4.4. Creation of the desired frequency divider using the 1-digit BCD counter created and
positive edge triggered D Flip-Flips.
4.4.1.

Use the Xilinx Schematic Editor to create the desired frequency divider as shown in
figure 3 below.

4.4.2.

Synthesize and implement the frequency divider.

4.4.3.

Create a new test bench waveform and simulate both the functional and timing behavior
of the frequency divider created.

RESET
reference clock
clk

reset

D Flip-Flop
(FDC)

OR

RESET

OR2

reference clock
clk

RESET

reset

Modulo N BCD Counter

tc
(N = 10)

clk

reset

ce

D Flip-Flop
(FDC)

clock1

NOT
inv

Figure 3: Datapath block diagram of the Frequency Divider

Lab #3: Design of Modulo Counters

Proceed to post-lab exercise.

Lab #3: Design of Modulo Counters

5. POST-LAB
A signed plagiarism declaration form must be submitted with your assignment.
Due Date:

The deadline for submission of report for this laboratory exercise is as

follows:

Feedback on Lab

All Groups: Friday 16th October 2009 at 12 noon

Feedback for this laboratory exercise will be given by Mr. Marcus
George on Friday 23rd October 2009 in the Electronics Laboratory
during office hours. Students lab marks will be available.

Submission
Procedure:

Submit reports to designated graduate assistant in the Electronics

laboratory. Students must also fill out a report submission receipt and
have it signed or stamped by the graduate assistant.

Deliverables:

Submit an informal report consisting of the responses to the post-lab

exercises in addition to a lab discussion and conclusion.
[1] Discussion of the lab should include: [3 mark]
a. Relate design to the results obtained.
b. If design was successful then explain why it works. If not
successful then explain why design did not work along with and
possible solutions.
c. Include and explain all observations made.
d. Design decisions made and justification for decisions made.
e. Problems faced and how were they dealt with.
[2] Conclusion of the lab should include: [1 mark]
State briefly, but clearly, what you have gained from this laboratory.
Outline aspects that you have noted within the experiment outside of the
questions asked. Make comments on the procedure of the lab - Is there
anything that you could have done differently? How did you split the
work between group members? Did you have a plan of action? What else
would you suggest that should be added to this lab session?

10

Lab #3: Design of Modulo Counters

5.1. Assignment:
5.1.1.

Compare the 4-bit binary counter and 4-bit BCD counter in terms of operation, speed
(Maximum Frequency/ MHz) and hardware utilization (Device Utilization) for the
Spartan 3 xc3s1000-5ft256 chip. This can be easily obtained from the synthesis report.
[8 marks]

5.1.2.

Design and implement a modulo 25 counter using logic gates. [3 marks]

5.1.3.

Schematic [1 marks]

5.1.4.

functional simulation [1 mark]

5.1.5.

timing simulation [1 mark]

5.1.6.

Explain the operation of the frequency divider implemented in section 4.4 of this
laboratory exercise. [8 marks]

5.1.7.

Explain how we can modify the frequency divider implemented in section 4.4 such that
it takes the 50MHz reference clock signal and produces a 1kHz signal. Implement this
frequency divider using binary counters and perform functional and timing simulation
on it. [total = 6 marks]
Students must submit the following for this question:
i. Schematic [2 marks]
ii. functional simulation [1 mark]
iii. timing simulation [1 mark]

5.1.8.

Implement this frequency divider using BCD counters and perform functional and
timing simulation on it. Remember to submit the schematic. Students must submit the
following for this question:
i. Schematic [1 marks]
ii. functional simulation [1 mark]
iii. timing simulation [1 mark]

End of DIGLAB3: Design of Modulo Counters

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