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TLC2272, TLC2272A, TLC2272M, TLC2272AM

SLOS190H FEBRUARY 1997 REVISED MARCH 2016
TLC227x, TLC227xA: Advanced LinCMOS Rail-to-Rail Operational Amplifiers

1 Features
Output Swing Includes Both Supply Rails

Low Noise: 9 nV/Hz Typical at f = 1 kHz
Low-Input Bias Current: 1-pA Typical
Fully-Specified for Both Single-Supply and SplitSupply Operation
Common-Mode Input Voltage Range Includes
Negative Rail
High-Gain Bandwidth: 2.2-MHz Typical
High Slew Rate: 3.6-V/s Typical
Low Input Offset Voltage: 950 V Maximum at
TA = 25C
Macromodel Included
Performance Upgrades for the TLC272 and
TLC274
Available in Q-Temp Automotive
The TLC227x also make great upgrades to the

TLC27x in standard designs. They offer increased
output dynamic range, lower noise voltage, and lower
input offset voltage. This enhanced feature set allows
them to be used in a wider range of applications. For
applications that require higher output drive and wider
input voltage range, see the TLV2432 and TLV2442
devices.
If the design requires single amplifiers, see the
TLV2211, TLV2221 and TLV2231 family. These
devices are single rail-to-rail operational amplifiers in
the SOT-23 package. Their small size and low power
consumption make them ideal for high density,
battery-powered equipment.
Device Information(1)
PART NUMBER
TLC2272
2 Applications
White Goods (Refrigerators, Washing Machines)
Hand-held Monitoring Systems
Configuration Control and Print Support
Transducer Interfaces
Battery-Powered Applications
3 Description
The TLC2272 and TLC2274 are dual and quadruple
operational amplifiers from Texas Instruments. Both
devices exhibit rail-to-rail output performance for
increased dynamic range in single- or split-supply
applications. The TLC227x family offers 2 MHz of
bandwidth and 3 V/s of slew rate for higher-speed
applications. These devices offer comparable AC
performance while having better noise, input offset
voltage, and power dissipation than existing CMOS
operational amplifiers. The TLC227x has a noise
voltage of 9 nV/Hz, two times lower than competitive
solutions.
The TLC227x family of devices, exhibiting high input
impedance and low noise, is excellent for small-signal
conditioning for high-impedance sources such as
piezoelectric transducers. Because of the micropower
dissipation levels, these devices work well in handheld monitoring and remote-sensing applications. In
addition, the rail-to-rail output feature, with single- or
split-supplies, makes this family a great choice when
interfacing with analog-to-digital converters (ADCs).
For precision applications, the TLC227xA family is
available with a maximum input offset voltage of
950 V. This family is fully characterized at 5 V and
5 V.
TLC2274
BODY SIZE (NOM)

4.40 mm 3.00 mm
SOIC (8)
3.91 mm 4.90 mm
SO (8)
5.30 mm 6.20 mm
PDIP (8)
6.35 mm 9.81 mm
TSSOP (14)
4.40 mm 5.00 mm
SOIC (14)
3.91 mm 8.65 mm
SO (14)
5.30 mm 10.30
mm
PDIP (14)
6.35 mm 19.30
mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
Maximum Peak-to-Peak Output Voltage vs

Supply Voltage
V(OPP)
V
O(PP) Maximum Peak-to-Peak Output Voltage V
PACKAGE
TSSOP (8)
16
TA = 25C
14
12
IO = 50 A
10
IO = 500 A
4
4
10
12
14
16
|VDD | Supply Voltage V
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5

ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
TLC2272 and TLC2272A Electrical Characteristics
VDD = 5 V ................................................................... 6
VDD = 5 V................................................................ 8
VDD = 5 V ................................................................... 9
VDD = 5 V.............................................................. 11
Typical Characteristics ............................................ 13
Detailed Description ............................................ 24
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
24
24
24
24
Application and Implementation ........................ 25

8.1 Application Information............................................ 25
8.2 Typical Application .................................................. 26
9 Power Supply Recommendations...................... 28

10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30

11.1
11.2
11.3
11.4
11.5
Related Links ........................................................

Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
12 Mechanical, Packaging, and Orderable

Information ........................................................... 30
4 Revision History
Changes from Revision G (May 2004) to Revision H
Page
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Supportsection, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
Added ESD Rating table for the D and PW package devices. .............................................................................................. 5
Submit Documentation Feedback
Copyright 19972016, Texas Instruments Incorporated
Product Folder Links: TLC2272 TLC2272A TLC2272M TLC2272AM TLC2274 TLC2274A TLC2274M TLC2274AM

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5 Pin Configuration and Functions

TLC2272
D, JG, P, or PW Package
8-Pin SOIC, CDIP, PDIP, or TSSOP
Top View
1OUT
1IN
1IN +
VDD /GND
VDD +
2OUT
2IN
2IN +
1OUT
1IN
1IN +
VDD +
2IN +
2IN
2OUT
NC
1OUT
NC
VDD+
NC
TLC2272
FK Package
20-Pin LCCC
Top View
TLC2274
D, J, N, PW, or W Package
14-Pin SOIC, CDIP, PDIP, TSSOP, or CFP
Top View
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
NC
2 OUT
NC
2 IN
NC
10
12
11
10
4OUT
4IN
4IN +
VDD
3IN +
3IN
3OUT
1IN +
NC
VDD +
NC
2IN +
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
4IN +
NC
VDD
NC
3IN +
2IN
2OUT
NC
3OUT
3IN
TLC2272
U Package
10-Pin CFP
Top View
NC
1 OUT
1 IN
1 IN+
VDD/GND
13
1IN
1OUT
NC
4OUT
4IN
14
TLC2274
FK Package
20-Pin LCCC
Top View
NC
VDD/GND
NC
2 IN+
NC
NC
1 IN
NC
1 IN+
NC
NC
VDD+
2 OUT
2 IN
2 IN+

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Pin Functions
PIN
NO.
TLC2272
NAME
I/O
TLC2274
DESCRIPTION
D, JG, P,
or PW
FK
D, J, N,
PW, or W
FK
1IN+
Non-inverting input, Channel 1
1IN-
Inverting input, Channel 1
1OUT
Output, Channel 1
2IN+
12
2IN-
15
2OUT
17
10
Output, Channel 2
3IN+
10
14
3IN-
13
3OUT
12
Output, Channel 3
4IN+
12
18
4IN-
13
19
4OUT
14
20
Output, Channel 4
VDD+
20
Positive (highest) supply
VDD
11
16
Negative (lowest) supply
VDD/GND
10
Negative (lowest) supply
1, 3, 4, 6, 8,
9, 11, 13, 14,
16, 18, 19
1, 10
1, 5, 7, 11,
15, 17
No Connection
NC

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage, VDD+ (2)

VDD-
(2)
Differential input voltage, VID (3)
16
VDD+
Input current, II (any input)
mA
Output current, IO
50
mA
Total current into VDD+
50
mA
50
mA
Input voltage, VI(any input) (2)
VDD 0.3
Total current out of VDD

Duration of short-circuit current at (or below) 25C (4)
Unlimited
C level parts
Operating free-air temperature range, TA
70
I, Q level parts
40
125
M level parts
55
125
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
D, N, P or PW package
260
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds
J or U package
300
150
Storage temperature, Tstg

(1)
(2)
(3)
(4)
65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD.
Differential voltages are at IN+ with respect to IN. Excessive current will flow if input is brought below VDD 0.3 V.
The output may be shorted to either supply. Temperature or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
6.2 ESD Ratings

VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC

Q100-002 (1)
Q-grade and M-grade devices in D and

PW packages
2000
Charged-device model (CDM), per

AEC Q100-011
Q-grade and M-grade devices in D and

PW packages
1000
UNIT
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
VDD
VI
VIC
Supply voltage
Input voltage
Common-mode input voltage
MIN
MAX
C LEVEL PARTS
2.2
I LEVEL PARTS
2.2
Q LEVEL PARTS
2.2
M LEVEL PARTS
2.2
C LEVEL PARTS
VDD
VDD+ 1.5
I LEVEL PARTS
VDD
VDD+ 1.5
Q LEVEL PARTS
VDD
VDD+ 1.5
M LEVEL PARTS
VDD
VDD+ 1.5
C LEVEL PARTS
VDD
VDD+ 1.5
I LEVEL PARTS
VDD
VDD+ 1.5
Q LEVEL PARTS
VDD
VDD+ 1.5
M LEVEL PARTS
VDD
VDD+ 1.5
UNIT

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Recommended Operating Conditions (continued)

MIN
MAX
70
I LEVEL PARTS
40
125
Q LEVEL PARTS
40
125
M LEVEL PARTS
55
125
C LEVEL PARTS
TA
Operating free-air temperature
UNIT
6.4 Thermal Information

TLC2272
THERMAL METRIC (1)
TLC2274
D
(SOIC)
P
(PDIP)
PW
(TSSOP)
FK
(LCCC)
U
(CFP)
D
(SOIC)
N
(PDIP)
PW
(TSSOP)
FK
(LCCC)
J
(CDIP)
UNIT
8-PIN
8-PIN
8-PIN
20-PIN
10-PIN
14-PIN
14-PIN
14-PIN
20-PIN
14-PIN
RJA
Junction-to-ambient thermal
resistance (2) (3)
115.6
58.5
175.8
83.8
111.6
C/W
RJC(top)
Junction-to-case (top) thermal

resistance (2) (3)
61.8
48.3
58.8
18
121.3
43.2
34
41.2
16
16.2
C/W
RJB
Junction-to-board thermal
resistance
55.9
35.6
104.3
38.4
54.7
C/W
JT
Junction-to-top
characterization parameter
14.3
25.9
5.9
9.4
3.9
C/W
JB
Junction-to-board
characterization parameter
55.4
35.5
102.6
38.1
53.9
C/W
RJC(bot)
Junction-to-case (bottom)
thermal resistance
8.68
C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) TA) / JA. Operating at the absolute maximum TJ of 150C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic).
6.5 TLC2272 and TLC2272A Electrical Characteristics VDD = 5 V

at specified free-air temperature, VDD = 5 V; TA = 25C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
TLC2272
VIO
VIC = 0 V, VDD = 2.5 V,

VO = 0 V, RS = 50
Input offset voltage
TLC2272A
TLC2272
TLC2272A
VIO
Temperature coefficient of
input offset voltage
Input offset voltage long-term drift
IIO
IIB
VICR
(1)
(2)
6
(2)
Input offset current
Input bias current
MIN
TA = 25C
TYP
MAX
300
2500
300
Full Range (1)

2
VIC = 0 V, VDD = 2.5 V, VO = 0 V, RS = 50
0.002
VIC = 0 V, VDD = 2.5 V,

VO = 0 V, RS = 50
RS = 50 ; |VIO | 5 mV
V/C
V/mo
All level parts
TA = 25C
C level part
TA = 0C to 80C
100
I level part
TA = 40C to 85C
150
Q level part
TA = 40C to 125C
800
M level part
TA = 55C to 125C
All level parts
TA = 25C
C level part
TA = 0C to 80C
100
I level part
TA = 40C to 85C
150
Q level part
TA = 40C to 125C
800
M level part
TA = 55C to 125C
TA = 25C
Full Range (1)
1500
VIC = 0 V, VDD = 2.5 V, VO = 0 V, RS = 50
VIC = 0 V, VDD = 2.5 V,

VO = 0 V, RS = 50
950
3000
UNIT
0.5
60
pA
800
1
60
pA
800
0.3
2.5
2.5
3.5
TA = 55C to 125C.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150C extrapolated to
TA = 25C using the Arrhenius equation and assuming an activation energy of 0.96 eV.

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TLC2272 and TLC2272A Electrical Characteristics VDD = 5 V (continued)

PARAMETER
TEST CONDITIONS
MIN
IOH = 20 A
VOH
High-level output voltage
IOH = 200 A
IOH = 1 mA
TA = 25C
4.85
Full Range (1)
4.85
TA = 25C
4.25
Full Range (1)
4.25
IOL = 50 A
VOL
Low-level output voltage
VIC = 2.5 V
IOL = 500 A
IOL = 5 mA
C level part
Large-signal differential
voltage amplification
AVD
VIC = 2.5 V,
VO = 1 V to 4 V;
RL = 10 k (3)
I level part
Q level part
M level part
V
4.65
0.09
0.15
0.15
TA = 25C
0.9
Full Range (1)

15
TA = 0C to 80C
15
TA = 25C
15
TA = 40C to 85C
15
TA = 25C
10
TA = 40C to 125C
10
TA = 25C
10
TA = 55C to 125C
10
1.5
35
35
35
V/mV
35
175
ri
Common-mode input resistance
ci
Common-mode input capacitance
f = 10 kHz, P package
zo
Closed-loop output impedance
f = 1 MHz, AV = 10
CMRR
Common-mode rejection ratio
VIC = 0 V to 2.7 V,
VO = 2.5 V, RS = 50
TA = 25C
70
Full Range (1)
70
kSVR
Supply-voltage rejection ratio

(VDD / VIO)
VDD = 4.4 V to 16 V,
VIC = VDD / 2, no load
TA = 25C
80
Full Range (1)
80
IDD
Supply currrent
VO = 2.5 V, no load
SR
Slew rate at unity gain
VO = 0.5 V to 2.5 V,
RL = 10 k (3), CL = 100 pF (3)
Vn
Equivalent input noise voltage
VNPP
Peak-to-peak equivalent
input noise voltage
In
Equivalent input noise current
1012
12
pF
140
10
TA = 25C
75
2.2
Full Range (1)
dB
3
3
TA = 25C
2.3
Full Range (1)
1.7
3.6
50
f = 1 kHz
f = 0.1 Hz to 1 Hz
dB
95
f = 10 Hz
f = 0.1 Hz to 10 Hz
1.4
0.6
VO = 0.5 V to 2.5 V,
f = 20 kHz, RL = 10 k (3)
1.5
TA = 25C
Differential input resistance
AV = 1
0.0013%
AV = 10
0.004%
AV = 100
0.03%
Gain-bandwidth product
f = 10 kHz, RL = 10 k (3), CL = 100 pF (3)
Maximum output-swing bandwidth
VO(PP) = 2 V, AV = 1, RL = 10 k (3), CL = 100 pF (3)
ts
Settling time
AV = 1, RL = 10 k (3),
Step = 0.5 V to 2.5 V, CL = 100 pF (3)
Phase margin at unity gain
RL = 10 k (3), CL = 100 pF (3)
50
Gain margin
RL = 10 k (3), CL = 100 pF (3)
10
(3)
UNIT
4.93
Full Range (1)
rid
BOM
MAX
0.01
TA = 25C
VIC = 2.5 V, VO = 1 V to 4 V; RL = 1 M (3)
THD+N Total harmonic distortion + noise
TYP
4.99
mA
V/s
nV/Hz
V
fA/Hz
2.18
MHz
MHz
To 0.1%
1.5
To 0.01%
2.6
dB
Referenced to 0 V.

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PARAMETER
TEST CONDITIONS
TLC2272
VIO
VIC = 0 V, VO = 0 V,
RS = 50
TLC2272A
TLC2272
TLC2272A
VIO
IIO
VIC = 0 V, VO = 0 V, RS = 50
Input offset voltage long-term drift (2)
VIC = 0 V, VO = 0 V, RS = 50
IIB
Input bias current
VICR
VIC = 0 V, VO = 0 V,
RS = 50
VIC = 0 V, VO = 0 V,
RS = 50
MIN
TA = 25C
Maximum positive peak

output voltage
Full Range (1)
C level part
TA = 0C to 80C
100
I level part
TA = 40C to 85C
150
Q level part
TA = 40C to 125C
800
M level part
TA = 55C to 125C
All level parts
TA = 25C
C level part
TA = 0C to 80C
100
I level part
TA = 40C to 85C
150
Q level part
TA = 40C to 125C
800
M level part
TA = 55C to 125C
0.5
IO = 200 A
IO = 500 A
C level part
I level part
60
pA
800
1
60
pA
800
5.3
3.5
4.99
IO = 5 mA
AVD
V/mo
0.002
Full Range (1)
V/C
TA = 25C
UNIT
1500
TA = 25C
RS = 50 ; |VIO | 5 mV
VIC = 0 V,
950
3000
TA = 25C
4.85
Full Range (1)
4.85
TA = 25C
4.25
Full Range (1)
4.25
IO = 50 A
Maximum negative
peak output voltage
2500
All level parts
IO = 1 mA
VOM-
MAX
300
300
IO = 20 A
VOM+
TYP
VO = 4 V; RL = 10 k
Q level part
M level part
4.93
V
4.65
4.99
TA = 25C
4.85
Full Range (1)
4.85
TA = 25C
3.5
Full Range (1)
3.5
TA = 25C
25
TA = 0C to 80C
25
TA = 25C
25
TA = 40C to 85C
25
TA = 25C
20
TA = 40C to 125C
20
TA = 25C
20
TA = 55C to 125C
20
VO = 4 V; RL = 1 M
4.91
V
4.1
50
50
50
V/mV
50
300
rid
1012
ri
1012
ci
pF
zo
f = 1 MHz, AV = 10
130
CMRR
VIC = 5 V to 2.7 V,
VO = 0 V, RS = 50
TA = 25C
75
Full Range (1)
75
kSVR

(VDD / VIO)
VDD+ = 2.2 V to 8 V,
VIC = 0 V, no load
TA = 25C
80
Full Range (1)
80
IDD
Supply currrent
VO = 0 V, no load
(1)
(2)
8
TA = 25C
80
dB
95
2.4
Full Range (1)
dB
3
3
mA
TA = 55C to 125C.

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PARAMETER
SR
Vn
VNPP
input noise voltage
In
TEST CONDITIONS
VO = 2.3 V,
RL = 10 k, CL = 100 pF
MIN
TYP
TA = 25C
2.3
3.6
Full Range (1)
1.7
f = 10 Hz
50
f = 1 kHz
f = 0.1 Hz to 1 Hz
MAX
V/s
nV/Hz
f = 0.1 Hz to 10 Hz
1.4
0.6
VO = 2.3,
f = 20 kHz, RL = 10 k
AV = 1
0.0011%
AV = 10
0.004%
AV = 100
0.03%
UNIT
fA/Hz
f = 10 kHz, RL = 10 k, CL = 100 pF
2.25
MHz
VO(PP) = 4.6 V, AV = 1, RL = 10 k, CL = 100 pF
0.54
MHz
ts
Settling time
AV = 1, RL = 10 k,
Step = 2.3 V to 2.3 V, CL = 100 pF
RL = 10 k, CL = 100 pF
52
Gain margin
RL = 10 k, CL = 100 pF
10
BOM
To 0.1%
1.5
To 0.01%
3.2
dB

PARAMETER
TEST CONDITIONS
TLC2274
VIO
VIC = 0 V, VDD = 2.5 V,

VO = 0 V, RS = 50
TLC2274A
TLC2274
TLC2274A
VIO
IIO
IIB
VICR
MIN
TA = 25C
2500
950
3000
Full Range (1)
UNIT
1500
VIC = 0 V, VDD = 2.5 V, VO = 0 V, RS = 50
V/C
VIC = 0 V, VDD = 2.5 V, VO = 0 V, RS = 50
0.002
V/mo
Input bias current
VIC = 0 V, VDD = 2.5 V,

VO = 0 V, RS = 50
VIC = 0 V, VDD = 2.5 V,

VO = 0 V, RS = 50
RS = 50 ; |VIO | 5 mV
IOH = 200 A
IOH = 1 mA
(1)
(2)
MAX
300
300
All level parts
TA = 25C
C level part
TA = 0C to 80C
100
I level part
TA = 40C to 85C
150
Q level part
TA = 40C to 125C
800
M level part
TA = 55C to 125C
All level parts
TA = 25C
C level part
TA = 0C to 80C
100
I level part
TA = 40C to 85C
150
Q level part
TA = 40C to 125C
800
M level part
TA = 55C to 125C
TA = 25C
Full Range (1)
0.5
60
pA
800
1
60
pA
800
0.3
2.5
2.5
3.5
IOH = 20 A
VOH
TYP
4.99
TA = 25C
4.85
Full Range (1)
4.85
TA = 25C
4.25
Full Range (1)
4.25
4.93
V
4.65
TA = 55C to 125C.

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PARAMETER
TEST CONDITIONS
MIN
IOL = 50 A
VOL
IOL = 500 A
VIC = 2.5 V
IOL = 5 mA
C level part
AVD
VIC = 2.5 V, VO = 1 V to
4 V;
RL = 10 k (3)
I level part
Q level part
M level part
TYP
MAX
UNIT
0.01
TA = 25C
0.09
Full Range (1)
0.15
0.15
TA = 25C
0.9
Full Range (1)
1.5
1.5
TA = 25C
15
TA = 0C to 80C
15
TA = 25C
15
TA = 40C to 85C
15
TA = 25C
10
TA = 40C to 125C
10
TA = 25C
10
TA = 55C to 125C
10
VIC = 2.5 V, VO = 1 V to 4 V; RL = 1 M (3)
35
35
35
V/mV
35
175
rid
1012
ri
1012
ci
pF
zo
f = 1 MHz, AV = 10
140
CMRR
VIC = 0 V to 2.7 V,
VO = 2.5 V, RS = 50
TA = 25C
70
Full Range (1)
70
kSVR

(VDD / VIO)
VDD = 4.4 V to 16 V,
VIC = VDD / 2, no load
TA = 25C
80
Full Range (1)
80
IDD
Supply currrent
VO = 2.5 V, no load
SR
VO = 0.5 V to 2.5 V,
RL = 10 k (3), CL = 100 pF (3)
Vn
VNPP
input noise voltage
In
BOM
TA = 25C
75
4.4
2.3
Full Range (1)
1.7
3.6
f = 10 Hz
50
f = 1 kHz
9
1
1.4
0.6
VO = 0.5 V to 2.5 V,
f = 20 kHz, RL = 10 k (3)
AV = 1
0.0013%
AV = 10
0.004%
AV = 100
0.03%
f = 10 kHz, RL = 10 k (3), CL = 100 pF (3)
VO(PP) = 2 V, AV = 1, RL = 10 k (3), CL = 100 pF (3)

(3)
mA
V/s
nV/Hz
V
fA/Hz
MHz
MHz
To 0.1%
1.5
To 0.01%
2.6
Settling time
AV = 1, RL = 10 k ,
Step = 0.5 V to 2.5 V, CL = 100 pF (3)
RL = 10 k (3), CL = 100 pF (3)
50
Gain margin
RL = 10 k (3), CL = 100 pF (3)
10
10
2.18
ts
(3)
dB
TA = 25C
f = 0.1 Hz to 10 Hz
dB
95
Full Range (1)
f = 0.1 Hz to 1 Hz
dB
Referenced to 0 V.

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PARAMETER
TEST CONDITIONS
TLC2274
VIO
VIC = 0 V, VO = 0 V,
RS = 50
TLC2274A
TLC2274
TLC2274A
VIO
IIO
VIC = 0 V, VO = 0 V, RS = 50
VIC = 0 V, VO = 0 V, RS = 50
IIB
Input bias current
VICR
VIC = 0 V, VO = 0 V,
RS = 50
VIC = 0 V, VO = 0 V,
RS = 50
MIN
TA = 25C
Maximum positive peak

output voltage
Full Range (1)
V/mo
0.002
TA = 0C to 80C
100
I level part
TA = 40C to 85C
150
Q level part
TA = 40C to 125C
800
M level part
TA = 55C to 125C
All level parts
TA = 25C
C level part
TA = 0C to 80C
100
I level part
TA = 40C to 85C
150
Q level part
TA = 40C to 125C
800
M level part
TA = 55C to 125C
0.5
60
Full Range (1)
pA
800
1
TA = 25C
60
pA
800
5.3
3.5
4.99
IO = 200 A
IO = 500 A
C level part
I level part
V/C
C level part
IO = 5 mA
AVD
UNIT
1500
TA = 25C
RS = 50 ; |VIO | 5 mV
VIC = 0 V
950
3000
TA = 25C
4.85
Full Range (1)
4.85
TA = 25C
4.25
Full Range (1)
4.25
IO = 50 A
Maximum negative peak
output voltage
2500
All level parts
IO = 1 mA
VOM-
MAX
300
300
IO = 20 A
VOM+
TYP
VO = 4 V; RL = 10 k
Q level part
M level part
4.93
V
4.65
4.99
TA = 25C
4.85
Full Range (1)
4.85
TA = 25C
3.5
Full Range (1)
3.5
TA = 25C
25
TA = 0C to 80C
25
TA = 25C
25
TA = 40C to 85C
25
TA = 25C
20
TA = 40C to 125C
20
TA = 25C
20
TA = 55C to 125C
20
VO = 4 V; RL = 1 M
4.91
V
4.1
50
50
50
V/mV
50
300
rid
1012
ri
1012
ci
pF
zo
f = 1 MHz, AV = 10
130
CMRR
VIC = 5 V to 2.7 V,
VO = 0 V, RS = 50
TA = 25C
75
Full Range (1)
75
kSVR

(VDD / VIO)
VDD+ = 2.2 V to 8 V,
VIC = 0 V, no load
TA = 25C
80
Full Range (1)
80
IDD
Supply currrent
VO = 0 V, no load
(1)
(2)
TA = 25C
80
dB
95
4.8
Full Range (1)
dB
6
6
mA
TA = 55C to 125C.
11

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PARAMETER
SR
Vn
VNPP
input noise voltage
In
TEST CONDITIONS
VO = 2.3 V,
RL = 10 k, CL = 100 pF
MIN
TYP
TA = 25C
2.3
3.6
Full Range (1)
1.7
f = 10 Hz
50
f = 1 kHz
f = 0.1 Hz to 1 Hz
MAX
f = 0.1 Hz to 10 Hz
1.4
0.6
VO = 2.3,
f = 20 kHz, RL = 10 k
AV = 1
0.0011%
AV = 10
0.004%
AV = 100
0.03%
UNIT
V/s
nV/Hz
V
fA/Hz
f = 10 kHz, RL = 10 k, CL = 100 pF
2.25
MHz
VO(PP) = 4.6 V, AV = 1, RL = 10 k, CL = 100 pF
0.54
MHz
ts
Settling time
AV = 1, RL = 10 k,
Step = 2.3 V to 2.3 V, CL = 100 pF
RL = 10 k, CL = 100 pF
52
Gain margin
RL = 10 k, CL = 100 pF
10
BOM
12
To 0.1%
1.5
To 0.01%
3.2
dB

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6.9 Typical Characteristics

Table 1. Table of Graphs
FIGURE (1)
Distribution
1, 2, 3, 4
VIO
VIO
Input offset voltage temperature coefficient
Distribution
IIB /IIO
Input bias and input offset current
vs Free-air temperature
VI
Input voltage
VOH
vs Common-mode voltage
5, 6
7, 8, 9, 10 (2)
vs Supply voltage
11 (2)
12
13 (2)
vs High-level output current
14 (2)
VOL
vs Low-level output current
15, 16 (2)
VOM+
Maximum positive peak output voltage
vs Output current
17 (2)
VOM-
Maximum negative peak output voltage
vs Output current
18 (2)
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
19
vs Supply voltage
20
IOS
Short-circuit output current
VO
Output voltage
vs Differential input voltage
Large-signal differential voltage amplification
vs Load resistance
Large-signal differential voltage amplification and phase margin
vs Frequency
Large-signal differential voltage amplification
Output impedance
vs Frequency
29, 30
vs Frequency
31
32
AVD
z0
CMRR
kSVR
IDD
Supply current
SR
Slew rate
VO
Vn
vs Frequency
27 (2), 28 (2)
33, 34
35 (2)
vs Supply voltage
36 (2), 37 (2)
38 (2), 39 (2)
vs Load Capacitance
40
41 (2)
42, 43
Voltage-follower large-signal pulse response
44, 45
Inverting small-signal pulse response
46, 47
Voltage-follower small-signal pulse response
48, 49
vs Frequency
50, 51
52
Integrated noise voltage
vs Frequency
53
Total harmonic distortion + noise
vs Frequency
54
(1)
(2)
24
25, 26
Noise voltage over a 10-second period
22, 23
Inverting large-signal pulse response
THD+N
21 (2)
vs Supply voltage
55
56 (2)
Phase margin
vs Load capacitance
57
Gain margin
vs Load capacitance
58
For all graphs where VDD = 5 V, all loads are referenced to 2.5 V.
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
13

15
20
891 Amplifiers From

2 Wafer Lots
VDD = 2.5 V
TA = 25C
Percentage of Amplifiers %
20
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10
0
1.6 1.2 0.8 0.4
0.4
0.8
1.2
15
10
0
1.6 1.2 0.8 0.4
1.6
0.4
0.8
1.2
1.6
VIO Input Offset Voltage mV
Figure 1. Distribution of TLC2272 Input Offset Voltage
20
20
992 Amplifiers From
2 Wafer Lots
VDD = 5 V
992 Amplifiers From

2 Wafer Lots
VDD = 2.5 V
15
10
0
1.6 1.2 0.8
0.4
0.4
0.8
1.2
15
10
0
1.6 1.2 0.8
1.6
0.4
0.4
0.8
1.2
1.6

1
VDD = 5 V
TA = 25C
RS = 50

VIO
VIO
0.5
0.5
1
1
VIC Common-Mode Voltage V
Figure 5. Input Offset Voltage vs Common-Mode Voltage
14
891 Amplifiers From

2 Wafer Lots
VDD = 5 V
TA = 25C
VDD = 5 V
TA = 25C
RS = 50
0.5
0.5
1
6 5 4 3 2
VIC Common-Mode Voltage V
Figure 6. Input Offset Voltage vs Common-Mode Voltage

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20
25
128 Amplifiers From
2 Wafer Lots
VDD = 2.5 V
P Package
25C to 125C
15
10
0
5 4
128 Amplifiers From

2 Wafer Lots
VDD = 5 V
P Package
25C to 125C
20
25
15
10
0
5 4
Figure 7. Distribution of TLC2272 vs

Input Offset Voltage Temperature Coefficient
25
20
128 Amplifiers From

2 Wafer Lots
VDD = 2.5 V
N Package
TA = 25C to 125C
15
10
128 Amplifiers From

2 Wafer Lots
VDD = 2.5 V
N Package
TA = 25C to 125C
20
15
10
0
4
1 0
VIO Temperature Coefficient V/C
VIO Temperature Coefficient V/C


12
35
30
TA = 25C
RS = 50
10
VDD = 2.5 V
VIC = 0 V
VO = 0 V
RS = 50
8
6
25
20
IIB
15
IIO
10
V I Input Voltage V
IIB
I IO Input Bias and Input Offset Currents pA
IIB and IIO

25
0
5
V IO Temperature Coefficient V/C
V IO Temperature Coefficient V/C
4
2
|VIO| 5 mV
0
2
4
6
8
10
0
25
45
65
85
105
125
TA Free-Air Temperature C
Figure 11. Input Bias and Input Offset Current vs

Free-Air Temperature
Figure 12. Input Voltage vs Supply Voltage
15

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6
VDD = 5 V
V0H
V
OH High-Level Output Voltage V
VDD = 5 V
V I Input Voltage V
3
|VIO| 5 mV
1
75 50
4
TA = 125C
3
TA = 25C
2
TA = 55C
1
0
25
25
50
75
100
125
Figure 13. Input Voltage vs Free-Air Temperature
1.4
VOL
VOL Low-Level Output Voltage V
VOL
VOL Low-Level Output Voltage V
VDD = 5 V
TA = 25C
1
VIC = 0 V
0.8
VIC = 1.25 V
0.6
VIC = 2.5 V
0.2
0
1
2
3
4
IOL Low-Level Output Current mA
VDD = 5 V
VIC = 2.5 V
1.2
1
TA = 125C
0.8
TA = 25C
0.6
TA = 55C
0.4
0.2
Figure 15. Low-Level Output Voltage vs

Low-Level Output Current
5
VDD = 5 V
4
TA = 55C
TA = 25C
3
TA = 125C
1
0
|IO| Output Current mA
Figure 17. Maximum Positive Peak Output Voltage vs

Output Current
5
1
2
3
4
IOL Low-Level Output Current mA
Figure 16. Low-Level Output Voltage vs

Low-Level Output Current
V OM Maximum Negative Peak Output Voltage V
V OM + Maximum Positive Peak Output Voltage V
0
0
16
Figure 14. High-Level Output Voltage vs

High-Level Output Current
1.2
0.4
IOH High-Level Output Current mA
3.8
VDD = 5 V
VIC = 0 V
4
TA = 125C
4.2
TA = 25C
4.4
TA = 55C
4.6
4.8
5
0
IO Output Current mA
Figure 18. Maximum Positive Peak Output Voltage vs

Output Current

10
16
RL = 10 k
TA = 25C
IIOS
OS Short-Circuit Output Current mA
V(OPP)
V O(PP) Maximum Peak-to-Peak Output Voltage V
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8
7
6
VDD = 5 V
5
4
VDD = 5 V
3
2
1
VID = 100 mV
12
0
VID = 100 mV
4
VO = 0 V
TA = 25C
10 k
100 k
10 M
1M
f Frequency Hz
VO Output Voltage V
IIOS
OS Short-Circuit Output Current mA
0
800
125
VDD = 5 V
TA = 25C
RL = 10 k
VIC = 0 V
800
400
0
400
VID Differential Input Voltage V
1200
Figure 22. Output Voltage vs Differential Input Voltage

1000
VO = 1 V
TA = 25C
AVD
AVD Large-Signal Differential
Voltage Amplification dB
25
0
25
50
75 100
Figure 21. Short-Circuit Output Current vs

VO Output Voltage V
VID = 100 mV
VDD = 5 V
TA = 25C
RL = 10 k
VIC = 2.5 V
VID = 100 mV
11
50
Figure 20. Short-Circuit Output Current vs Supply Voltage
VO = 0 V
VDD = 5 V
75
Figure 19. Maximum Peak-to-Peak Output Voltage vs

Frequency
15
100
VDD = 5 V
10
VDD = 5 V
5
0
250 500 750 1000
1000 750 500 250
VID Differential Input Voltage V
Figure 23. Output Voltage vs Differential Input Voltage
0.1
0.1
1
10
RL Load Resistance k
100
Figure 24. Large-Signal Differential Voltage Amplification vs

Load Resistance
17

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80
135
60
40
90
20
45
20
45
40
1k
10 k
100 k
1M
90
10 M
90
20
45
20
45
40
1k
10 k
AVD
Voltage Amplification V/mV
AVD
Voltage Amplification V/mV
1k
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
RL = 1 M
100
RL = 10 k
10
75
50
25
0
25
50
75 100
VDD = 5 V
VIC = 0 V
VO = 4 V
RL = 1 M
100
RL = 10 k
10
75
125

125
VDD = 5 V
TA = 25C
zo
O
zo Output Impedance
zo
O
zo Output Impedance
25
0
25
50
75 100
1000
VDD = 5 V
TA = 25C
18
50

1000
100
AV = 100
10
AV = 10
0.1
100
90
10 M
100 k
1M
f Frequency Hz
Figure 26. Large-Signal Differential Voltage Amplification

and Phase Margin vs Frequency
1k
135
40
f Frequency Hz
Figure 25. Large-Signal Differential Voltage Amplification

and Phase Margin vs Frequency
180
VDD = 5 V
RL = 10 k
CL = 100 pF
TA = 25C
om
m Phase Margin
AVD
60
180
AVD
VDD = 5 V
RL = 10 k
CL = 100 pF
TA = 25C
om
m Phase Margin
80
AV = 1
100
AV = 100
10
AV = 10
1
AV = 1
1k
10 k
100 k
1M
0.1
100
1k
10 k
100 k
1M
f Frequency Hz
f Frequency Hz
Figure 29. Output Impedance vs Frequency
Figure 30. Output Impedance vs Frequency

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90
TA = 25C
CMRR Common-Mode Rejection Ratio dB
CMRR Common-Mode Rejection Ratio dB
100
VDD = 5 V
80
VDD = 5 V
60
40
20
100
1k
10 k
100 k
1M
82
VDD = 5 V
VIC = 5 V to 2.7 V
78
VDD = 5 V
74
VIC = 0 V to 2.7 V
70
75
0
10
86
10 M
50
Figure 31. Common-Mode Rejection Ratio vs Frequency
kSVR
k
SVR Supply-Voltage Rejection Ratio dB
kSVR
k SVR Supply-Voltage Rejection Ratio dB
50
75
100
125
80
60
kSVR+
40
kSVR
20
100
1k
10 k
100 k
1M
VDD = 5 V
TA = 25C
80
60
kSVR+
40
kSVR
20
20
10
10 M
100
f Frequency Hz
1k
10 k
100 k
1M
10 M
f Frequency Hz
Figure 33. Supply-Voltage Rejection Ratio vs Frequency
Figure 34. Supply-Voltage Rejection Ratio vs Frequency
110
VDD = 2.2 V to 8 V
VO = 0 V
VO = 0 V
No Load
105
2.4
IIDD
DD Supply Current mA
kSVR
k
SVR Supply Voltage Rejection Ratio dB
25
100
VDD = 5 V
TA = 25C
100
95
1.8
TA = 25C
TA = 55C
1.2
TA = 125C
0.6
90
85
75
Figure 32. Common-Mode Rejection Ratio vs

100
20
10
25
f Frequency Hz
50
25
25
50
75
100
125
Figure 35. Supply-Voltage Rejection Ratio vs

2
3
4
5
6
Figure 36. TLC2272 Supply Current vs Supply Voltage
19

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3
6
VO = 0 V
No Load
VDD = 5 V
VO = 0 V
2.4
3.6
IIDD
IIDD
4.8
TA = 25C
TA = 55C
2.4
TA = 125C
1.2
VDD = 5 V
VO = 2.5 V
1.8
1.2
0.6
0
75
50
25
25
50
75
125
Figure 37. TLC2274 Supply Current vs Supply Voltage
Figure 38. TLC2272 Supply Current vs Free-Air Temperature
5
VDD = 5 V
AV = 1
TA = 25C
VDD = 5 V
VO = 0 V
4
SR Slew Rate V/ s
IIDD
4.8
VDD = 5 V
VO = 2.5 V
3.6
2.4
0
75
SR
3
2
SR +
1.2
50
25
25
50
75
100
0
10
125
100
1k
CL Load Capacitance pF
VDD = 5 V
RL = 10 k
CL = 100 pF
TA = 25C
AV = 1
SR
4
VO Output Voltage mV
VO
SR Slew Rate V/ s
4
SR +
3
VDD = 5 V
RL = 10 k
CL = 100 pF
AV = 1
0
75
10 k
Figure 40. Slew Rate vs Load Capacitance
Figure 39. TLC2274 Supply Current vs Free-Air Temperature
20
100
0
50
25
25
50
75
100
125
t Time s
Figure 41. Slew Rate vs Free-Air Temperature
Figure 42. Inverting Large-Signal Pulse Response

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5
3
2
VO Output Voltage V
VO
V
VO
O Output Voltage V
VDD = 5 V
RL = 10 k
CL = 100 pF
TA = 25C
AV = 1
1
0
1
2
VDD = 5 V
RL = 10 k
CL = 100 pF
AV = 1
TA = 25C
3
4
5
0
0
t Time s
Figure 43. Inverting Large-Signal Pulse Response

5
VDD = 5 V
RL = 10 k
CL = 100 pF
TA = 25C
AV = 1
2.6
VO Output Voltage V
VO
Figure 44. Voltage-Follower Large-Signal Pulse Response

2.65
VDD = 5 V
RL = 10 k
CL = 100 pF
TA = 25C
AV = 1
VO Output Voltage V
VO
t Time s
1
0
1
2
3
2.55
2.5
2.45
4
5
2.4
0
0.5
1 1.5
2 2.5 3
3.5 4
4.5
5 5.5
t Time s
t Time s
Figure 45. Voltage-Follower Large-Signal Pulse Response
Figure 46. Inverting Small-Signal Pulse Response

2.65
VDD = 5 V
RL = 10 k
CL = 100 pF
TA = 25C
AV = 1
50
2.6
VO Output Voltage V
VO
VO
100
50
VDD = 5 V
RL = 10 k
CL = 100 pF
TA = 25C
AV = 1
2.55
2.5
2.45
2.4
100
0
0.5
1.5
2.5
3.5
0.5
1.5
t Time s
t Time s
Figure 47. Inverting Small-Signal Pulse Response
Figure 48. Voltage-Follower Small-Signal Pulse Response
21

VDD = 5 V
RL = 10 k
CL = 100 pF
TA = 25C
AV = 1
50
Vn
nV HzHz
Vn Equivalent Input Noise Voltage nV/
VO
100
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50
VDD = 5 V
TA = 25C
RS = 20
40
30
20
10
100
100
1k
f Frequency Hz
Figure 49. Voltage-Follower Small-Signal Pulse Response
Figure 50. Equivalent Input Noise Voltage vs Frequency
1.5
60
1000
VDD = 5 V
TA = 25C
RS = 20
500
40
30
20
250
0
250
500
10
750
0
10
1000
10 k
100
1k
f Frequency Hz
10
0.1
100
1k
10
Figure 52. Noise Voltage Over a 10 Second Period

THD + N Total Harmonic Distortion Plus Noise %
Calculated Using
Ideal Pass-Band Filter
Lower Frequency = 1 Hz
TA= 25C
10
t Time s
100
Figure 51. Equivalent Input Noise Voltage vs Frequency
V RMS
Integrated Noise Voltage uVRMS
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25C
750
Noise Voltage nV
Vn
nV HzHz
Vn Equivalent Input Noise Voltage nV/
0.5
10
10 k
t Time s
22
60
10 k
100 k
1
VDD = 5 V
TA = 25C
RL = 10 k
0.1
AV = 100
0.01
AV = 10
0.001
0.0001
100
AV = 1
1k
10 k
100 k
f Frequency Hz
f Frequency Hz
Figure 53. Integrated Noise Voltage vs Frequency
Figure 54. Total Harmonic Distortion + Noise vs Frequency

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3
f = 10 kHz
RL = 10 k
CL = 100 pF
TA = 25C
2.4
VDD = 5 V
f = 10 kHz
RL = 10 k
CL = 100 pF
2.8
Gain-Bandwidth Product MHz
Gain-Bandwidth Product MHz
2.5
2.3
2.2
2.1
2.6
2.4
2.2
2
1.8
1.6
1.4
2
0
6
2
3
4
5
Figure 55. Gain-Bandwidth Product vs Supply Voltage

75
50
25
0
25
50
75 100
125
Figure 56. Gain-Bandwidth Product vs Free-Air Temperature

15
VDD = 5 V
TA = 25C
Rnull = 100
60
12
Rnull = 50
Gain Margin dB
m Phase Margin
om
75
45
Rnull = 20
30
VDD = 5 V
AV = 1
RL = 10 k
TA = 25C
10 k
15
10 k
0
10
VDD +
Rnull
VI
Rnull = 0
CL
VDD
Rnull = 10
100
1000
10000
Figure 57. Phase Margin vs Load Capacitance
0
10
100
1000
10000
Figure 58. Gain Margin vs Load Capacitance
23

www.ti.com
7 Detailed Description
7.1 Overview
The TLC227x and TLC227xA families of devices are rail-to-rail output operational amplifiers. These devices
operate from 4.4-V to 16-V single supply and 2.2-V 8-V dual supply, are unity-gain stable, and are suitable for
a wide range of general-purpose applications.
7.2 Functional Block Diagram

VDD +
Q3
Q6
Q9
Q12
Q14
Q16
IN +
OUT
C1
IN
R5
Q1
Q4
Q13
Q15
Q17
D1
Q2
Q5
R3
R4
Q7
Q8
Q10
Q11
R1
R2
VDD
Table 2. Device Component Count (1)
(1)
Component
TLC2272
TLC2274
Transistors
38
76
Resistors
26
52
Diodes
18
Capacitors
Includes both amplifiers and all ESD, bias, and trim circuitry.
7.3 Feature Description

The TLC227x and TLC227xA family of devices feature 2-MHz bandwidth and voltage noise of 9 nV/Hz with
performance rated from 4.4 V to 16 V across an automotive temperature range (40C to 125C). LinMOS suits
a wide range of audio, automotive, industrial, and instrumentation applications.
7.4 Device Functional Modes

The TLC227x and TLC227xA families of devices is powered on when the supply is connected. The devices may
operate with single or dual supply, depending on the application. The devices are in its full performance once the
supply is above the recommended value.
24

www.ti.com
8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

8.1.1 Macromodel Information
Macromodel information provided was derived using MicroSim Parts, the model generation software used with
MicroSim PSpice. The Boyle macromodel (1) and subcircuit in Figure 59 were generated using the TLC227x
typical electrical and operating characteristics at TA = 25C. Using this information, output simulations of the
following key parameters can be generated to a tolerance of 20% (in most cases):
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity gain frequency
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
99
DIN
3
EGND +
VCC +
9
RSS
10
VC
IN
J1
DP
J2
11
VAD
VCC
DC
12
VIN
7
+
GCM
GA
VLIM
RD2
60
+ DIP
C2
6
C1
RD1
R2
53
IN +
HLIM
91
+
VIP
90
RO2
VB
RP
2
92
FB
ISS
RO1
DE
54
+
VE
.SUBCKT TLC227x 1 2 3 4 5
C1
11
1214E12
C2
6
760.00E12
DC
5
53DX
DE
54
5DX
DLP
90
91DX
DLN
92
90DX
DP
4
3DX
EGND
99
0POLY (2) (3,0) (4,) 0 .5 .5
FB
99
0POLY (5) VB VC VE VLP VLN 0
+ 984.9E3 1E6 1E6 1E6 1E6
GA
6
011 12 377.0E6
GCM 0 6 10 99 134E9
ISS
3
10DC 216.OE6
HLIM
90
0VLIM 1K
J1
11
210 JX
J2
12
110 JX
R2
6
9100.OE3
OUT
RD1
60
112.653E3
RD2
60
122.653E3
R01
8
550
R02
7
9950
RP
3
44.310E3
RSS
10
99925.9E3
VAD
60
4.5
VB
9
0DC 0
VC 3 53 DC .78
VE
54
4DC .78
VLIM
7
8DC 0
VLP
91
0DC 1.9
VLN
0
92DC 9.4
.MODEL DX D (IS=800.0E18)
.MODEL JX PJF (IS=1.500E12BETA=1.316E-3
+ VTO=.270)
.ENDS
Figure 59. Boyle Macromodel and Subcircuit

(1)
Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974).
25

www.ti.com
8.2 Typical Application

8.2.1 High-Side Current Monitor
VBAT
V1
ILOUD
V2
RS
0.1 F
R1
R
ILOAD
VOUT
+
_
R2
47 k
Rg
Figure 60. Equivalent Schematic (Each Amplifier)

8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
PARAMETER
VALUE
VBAT
Battery Voltage
12 V
RSENSE
Sense Resistor
ILOAD
Load Current
0.1
0 A to 10 A
Operational Amplifier
Set in Differential configuration with Gain = 10
8.2.1.2 Detailed Design Procedure

This circuit is designed for measuring the high-side current in automotive body control modules with 12-V battery
or similar applications. The operational amplifier is set as differential with an external resistor network.
8.2.1.2.1 Differential Amplifier Equations
Equation 1 and Equation 2 are used to calculate VOUT.
VOUT
VOUT
R R
1 R
R
1+ 1 +
- 1
2 R2 Rg
Rg Rg R2 V1 + V2
=
R
R
R
2
1+ 1
1+ 1
R2
R2
R R
1 R
R
1+ 1 +
- 1
2 R2 Rg
Rg Rg R2
=
VBAT +
R1
R
R
1+
1+ 1
R2
R2
(V - V )
1
2
(1)
R I
S
Load
(2)
In an ideal case R1 = R and R2 = Rg, and VOUT can then be calculated using Equation 3:
Rg
VOUT =
RS ILoad
R
26
(3)

www.ti.com
However, as the resistors have tolerances, they cannot be perfectly matched.

R1 = R R1
R2 = R2 R2
R = R R
Rg = Rg Rg
DR
Tol =
R
(4)
By developing the equations and neglecting the second order, the worst case is when the tolerances add up.
This is shown by Equation 5.
Rg
2R Rg
VOUT = (4 Tol)
VBAT + 1 2 Tol 1 +
RS ILOAD
R + Rg
R + Rg R
where
Tol = 0.01 for 1%

Tol = 0.001 for 0.1%
(5)
If the resistors are perfectly matched, then Tol = 0 and VOUT is calculated using Equation 6.
Rg
VOUT =
RS ILOAD
R
(6)
The highest error is from the Common mode, as shown in Equation 7.

Rg
4 (Tol)
VBAT
R + Rg
(7)
Gain of 10, Rg / R = 10, and Tol = 1%:

Common mode error = ((4 0.01) / 1.1) 12 V = 0.436 V
Gain of 10 and Tol = 0.1%:
Common mode error = 43.6 mV
The resistors were chosen from 2% batches.
R1 and R 12 k
R2 and Rg 120 k
Ideal Gain = 120 / 12 = 10
The measured value of the resistors:
R1 = 11.835 k
R = 11.85 k
R2 = 117.92 k
Rg = 118.07 k
27

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1.2
12
10
Output Voltage (V)
Output Voltage (V)
8.2.1.3 Application Curves
0.8
0.6
0.4
0.2
8
6
4
2
Measured
Ideal
Measured
Ideal
0.2
0.4
0.6
0.8
Load Current (A)
Figure 61. Output Voltage Measured vs Ideal

(0 to 1 A)
1.2
D001
6
8
Load Current (A)
10
12
D001
Figure 62. Output Voltage Measured vs Ideal

(0 to 10 A)
9 Power Supply Recommendations

Supply voltage for a single supply is from 4.4 V to 16 V, and from 2.2 V to 8 V for dual supply. In the high-side
sensing application, the supply is connected to a 12-V battery.
28

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10 Layout
10.1 Layout Guidelines
The TLC227x and TLC227xA families of devices are wideband amplifiers. To realize the full operational
performance of the devices, good high-frequency printed-circuit-board (PCB) layout practices are required. Lowloss 0.1-F bypass capacitors must be connected between each supply pin and ground as close to the device as
possible. The bypass capacitor traces should be designed for minimum inductance.
10.2 Layout Example
Figure 63. Layout Example
29

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11 Device and Documentation Support

11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLC2272
Click here
Click here
Click here
Click here
Click here
TLC2272A
Click here
Click here
Click here
Click here
Click here
TLC2272M
Click here
Click here
Click here
Click here
Click here
TLC2272AM
Click here
Click here
Click here
Click here
Click here
TLC2274
Click here
Click here
Click here
Click here
Click here
TLC2274A
Click here
Click here
Click here
Click here
Click here
TLC2274M
Click here
Click here
Click here
Click here
Click here
TLC2274AM
Click here
Click here
Click here
Click here
Click here
11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
MicroSim Parts, PSpice are trademarks of MicroSim.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
5962-9318201M2A
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629318201M2A
TLC2274
MFKB
5962-9318201MCA
ACTIVE
CDIP
14
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9318201MC
A
TLC2274MJB
5962-9318201QDA
ACTIVE
CFP
14
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9318201QD
A
TLC2274MWB
5962-9318202Q2A
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629318202Q2A
TLC2274
AMFKB
5962-9318202QCA
ACTIVE
CDIP
14
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9318202QC
A
TLC2274AMJB
5962-9318202QDA
ACTIVE
CFP
14
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9318202QD
A
TLC2274AMWB
5962-9555201NXD
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
Q2272M
5962-9555201NXDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
Q2272M
5962-9555201Q2A
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629555201Q2A
TLC2272
MFKB
5962-9555201QHA
ACTIVE
CFP
10
TBD
A42
N / A for Pkg Type
-55 to 125
9555201QHA
TLC2272M
5962-9555201QPA
ACTIVE
CDIP
JG
TBD
A42
N / A for Pkg Type
-55 to 125
9555201QPA
TLC2272M
5962-9555202Q2A
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629555202Q2A
TLC2272
AMFKB
Addendum-Page 1
Samples
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20-Oct-2015
Orderable Device
Status
(1)

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
5962-9555202QHA
ACTIVE
CFP
10
TBD
A42
N / A for Pkg Type
-55 to 125
9555202QHA
TLC2272AM
5962-9555202QPA
ACTIVE
CDIP
JG
TBD
A42
N / A for Pkg Type
-55 to 125
9555202QPA
TLC2272AM
TLC2272ACD
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272AC
TLC2272ACDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272AC
TLC2272ACDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272AC
TLC2272ACDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272AC
TLC2272ACP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC2272AC
TLC2272ACPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC2272AC
TLC2272ACPW
ACTIVE
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P2272A
TLC2272ACPWG4
ACTIVE
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P2272A
TLC2272ACPWLE
OBSOLETE
TSSOP
PW
TBD
Call TI
Call TI
TLC2272ACPWR
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P2272A
TLC2272ACPWRG4
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P2272A
TLC2272AID
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272AI
TLC2272AIDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272AI
TLC2272AIDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272AI
TLC2272AIDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272AI
TLC2272AIP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Addendum-Page 2
TLC2272AI
Samples
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20-Oct-2015
Orderable Device
Status
(1)

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC2272AIPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC2272AI
TLC2272AMD
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272AMDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272AMDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272AMDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272AMFKB
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629555202Q2A
TLC2272
AMFKB
TLC2272AMJGB
ACTIVE
CDIP
JG
TBD
A42
N / A for Pkg Type
-55 to 125
9555202QPA
TLC2272AM
-55 to 125
2272AM
2272AM
-55 to 125
2272AM
2272AM
TLC2272AMP
OBSOLETE
PDIP
TBD
Call TI
Call TI
-55 to 125
TLC2272AMUB
ACTIVE
CFP
10
TBD
A42
N / A for Pkg Type
-55 to 125
9555202QHA
TLC2272AM
TLC2272AQD
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C2272A
TLC2272AQDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272AQDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272AQDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272CD
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2272C
TLC2272CDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2272C
TLC2272CDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2272C
TLC2272CDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2272C
Addendum-Page 3
C2272A
-40 to 125
C2272A
C2272A
Samples
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20-Oct-2015
Orderable Device
Status
(1)

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC2272CP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC2272CP
TLC2272CPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC2272CP
TLC2272CPSR
ACTIVE
SO
PS
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P2272
TLC2272CPW
ACTIVE
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P2272
TLC2272CPWG4
ACTIVE
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P2272
TLC2272CPWLE
OBSOLETE
TSSOP
PW
TBD
Call TI
Call TI
0 to 70
TLC2272CPWR
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P2272
TLC2272CPWRG4
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P2272
TLC2272ID
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272I
TLC2272IDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272I
TLC2272IDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272I
TLC2272IDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2272I
TLC2272IP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC2272IP
TLC2272IPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC2272IP
TLC2272IPW
ACTIVE
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Y2272
TLC2272IPWG4
ACTIVE
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Y2272
TLC2272IPWLE
OBSOLETE
TSSOP
PW
TBD
Call TI
Call TI
TLC2272IPWR
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Y2272
TLC2272IPWRG4
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Y2272
Addendum-Page 4
Samples
www.ti.com
20-Oct-2015
Orderable Device
Status
(1)

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC2272MD
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
2272M
TLC2272MDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272MDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272MDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272MFKB
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629555201Q2A
TLC2272
MFKB
TLC2272MJG
ACTIVE
CDIP
JG
TBD
A42
N / A for Pkg Type
-55 to 125
TLC2272MJG
TLC2272MJGB
ACTIVE
CDIP
JG
TBD
A42
N / A for Pkg Type
-55 to 125
9555201QPA
TLC2272M
2272M
-55 to 125
2272M
2272M
TLC2272MP
OBSOLETE
PDIP
TBD
Call TI
Call TI
-55 to 125
TLC2272MUB
ACTIVE
CFP
10
TBD
A42
N / A for Pkg Type
-55 to 125
TLC2272QDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272QDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2272QPWRG4
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274ACD
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2274AC
TLC2274ACDG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2274AC
TLC2274ACDR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2274AC
TLC2274ACDRG4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2274AC
TLC2274ACN
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC2274ACN
TLC2274ACNE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC2274ACN
Addendum-Page 5
9555201QHA
TLC2272M
C2272Q
-40 to 125
C2272Q
T2272Q
Samples
www.ti.com
20-Oct-2015
Orderable Device
Status
(1)

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC2274ACPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P2274A
TLC2274ACPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P2274A
TLC2274ACPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P2274A
TLC2274ACPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P2274A
TLC2274AID
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274AI
TLC2274AIDG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274AI
TLC2274AIDR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274AI
TLC2274AIDRG4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274AI
TLC2274AIN
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLC2274AIN
TLC2274AINE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLC2274AIN
TLC2274AIPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y2274A
TLC2274AIPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y2274A
TLC2274AIPWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 125
TLC2274AIPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y2274A
TLC2274AIPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y2274A
TLC2274AMD
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
2274AM
TLC2274AMDG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274AMDR
OBSOLETE
SOIC
14
TBD
Call TI
Call TI
TLC2274AMDRG4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 6
2274AM
-55 to 125
2274AM
Samples
www.ti.com
20-Oct-2015
Orderable Device
Status
(1)

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC2274AMFKB
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629318202Q2A
TLC2274
AMFKB
TLC2274AMJB
ACTIVE
CDIP
14
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9318202QC
A
TLC2274AMJB
TLC2274AMWB
ACTIVE
CFP
14
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9318202QD
A
TLC2274AMWB
TLC2274AQD
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC2274A
TLC2274AQDG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274AQDR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274AQDRG4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PJ2274A
TLC2274CD
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274C
TLC2274CDG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274C
TLC2274CDR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274C
TLC2274CDRG4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274C
TLC2274CN
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC2274CN
TLC2274CNE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC2274CN
TLC2274CNSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274
TLC2274CPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P2274
TLC2274CPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P2274
TLC2274CPWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
Addendum-Page 7
PJ2274A
-40 to 125
TLC2274A
Samples
www.ti.com
20-Oct-2015
Orderable Device
Status
(1)

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC2274CPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274CPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274ID
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274I
TLC2274IDG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274I
TLC2274IDR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274I
TLC2274IDRG4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274I
TLC2274IN
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC2274IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Y2274
TLC2274IPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Y2274
TLC2274IPWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
TLC2274IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Y2274
TLC2274IPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Y2274
TLC2274MD
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274MDG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274MDR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274MDRG4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC2274MFKB
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629318201M2A
TLC2274
MFKB
TLC2274MJ
ACTIVE
CDIP
14
TBD
A42
N / A for Pkg Type
-55 to 125
TLC2274MJ
Addendum-Page 8
P2274
0 to 70
P2274
TLC2274IN
-55 to 125
TLC2274M
PJ2274M
-55 to 125
TLC2274M
PJ2274M
Samples
www.ti.com
20-Oct-2015
Orderable Device
Status
(1)

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC2274MJB
ACTIVE
CDIP
14
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9318201MC
A
TLC2274MJB
TLC2274MN
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
TLC2274MN
TLC2274MWB
ACTIVE
CFP
14
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9318201QD
A
TLC2274MWB
TLC2274QD
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC2274
TLC2274QDG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
Call TI
Call TI
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
Call TI
Call TI
TLC2274QDR
OBSOLETE
SOIC
14
TLC2274QDRG4
ACTIVE
SOIC
14
TLC2274Y
PREVIEW
DIESALE
TLC2274
-40 to 125
TLC2274
TLC2274
(1)
The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 9
Samples
www.ti.com
20-Oct-2015
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC2272, TLC2272A, TLC2272AM, TLC2272M, TLC2274, TLC2274A, TLC2274AM, TLC2274M :
Catalog: TLC2272A, TLC2272, TLC2274A, TLC2274

Automotive: TLC2272-Q1, TLC2272A-Q1, TLC2272A-Q1, TLC2272-Q1, TLC2274-Q1, TLC2274A-Q1, TLC2274A-Q1, TLC2274-Q1
Enhanced Product: TLC2272A-EP, TLC2272A-EP, TLC2274-EP, TLC2274A-EP, TLC2274A-EP, TLC2274-EP
Military: TLC2272M, TLC2272AM, TLC2274M, TLC2274AM
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Military - QML certified for Military and Defense Applications
Addendum-Page 10
PACKAGE MATERIALS INFORMATION

www.ti.com
17-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
5962-9555201NXDR
Package Package Pins

Type Drawing
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC2272ACDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC2272ACPWR
TSSOP
PW
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLC2272AIDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC2272AMDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC2272AMDRG4
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC2272CDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC2272CPWR
TSSOP
PW
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLC2272IDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC2272IPWR
TSSOP
PW
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLC2272MDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC2274ACDR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC2274ACPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC2274AIDR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC2274AIPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC2274AQDR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC2274CDR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC2274CNSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1

www.ti.com
17-Feb-2016
Device
Package Package Pins

Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC2274CPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC2274IDR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC2274IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC2274MDR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC2274MDRG4
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC2274QDRG4
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
5962-9555201NXDR
SOIC
2500
367.0
367.0
38.0
TLC2272ACDR
SOIC
2500
340.5
338.1
20.6
TLC2272ACPWR
TSSOP
PW
2000
367.0
367.0
35.0
TLC2272AIDR
SOIC
2500
340.5
338.1
20.6
TLC2272AMDR
SOIC
2500
367.0
367.0
38.0
TLC2272AMDRG4
SOIC
2500
367.0
367.0
38.0
TLC2272CDR
SOIC
2500
340.5
338.1
20.6
TLC2272CPWR
TSSOP
PW
2000
367.0
367.0
35.0
TLC2272IDR
SOIC
2500
340.5
338.1
20.6
TLC2272IPWR
TSSOP
PW
2000
367.0
367.0
35.0
TLC2272MDR
SOIC
2500
367.0
367.0
38.0

www.ti.com
17-Feb-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC2274ACDR
SOIC
14
2500
333.2
345.9
28.6
TLC2274ACPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLC2274AIDR
SOIC
14
2500
333.2
345.9
28.6
TLC2274AIPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLC2274AQDR
SOIC
14
2500
367.0
367.0
38.0
TLC2274CDR
SOIC
14
2500
333.2
345.9
28.6
TLC2274CNSR
SO
NS
14
2000
367.0
367.0
38.0
TLC2274CPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLC2274IDR
SOIC
14
2500
333.2
345.9
28.6
TLC2274IPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLC2274MDR
SOIC
14
2500
367.0
367.0
38.0
TLC2274MDRG4
SOIC
14
2500
367.0
367.0
38.0
TLC2274QDRG4
SOIC
14
2500
367.0
367.0
38.0
MECHANICAL DATA
MCER001A JANUARY 1995 REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
0.280 (7,11)
0.245 (6,22)
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX

Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
015
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).

This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height

SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
0.1 C
6X 0.65
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A

8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
4
(5.8)
LAND PATTERN EXAMPLE

SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK

DEFINED
SOLDER MASK DETAILS

NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A

8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL

SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
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TLC 2274

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Product

TLC2272, TLC2272A, TLC2272M, TLC2272AM

TLC227x, TLC227xA: Advanced LinCMOS Rail-to-Rail Operational Amplifiers

Output Swing Includes Both Supply Rails

The TLC227x also make great upgrades to the

BODY SIZE (NOM)

(1) For all available packages, see the orderable addendum at

Maximum Peak-to-Peak Output Voltage vs

|VDD | Supply Voltage V

TLC2272, TLC2272A, TLC2272M, TLC2272AM

Absolute Maximum Ratings ...................................... 5

Detailed Description ............................................ 24

Application and Implementation ........................ 25

9 Power Supply Recommendations...................... 28

11 Device and Documentation Support ................. 30

Related Links ........................................................

12 Mechanical, Packaging, and Orderable

Submit Documentation Feedback

Copyright 19972016, Texas Instruments Incorporated

TLC2272, TLC2272A, TLC2272M, TLC2272AM

SLOS190H FEBRUARY 1997 REVISED MARCH 2016

5 Pin Configuration and Functions

Copyright 19972016, Texas Instruments Incorporated

Submit Documentation Feedback

TLC2272, TLC2272A, TLC2272M, TLC2272AM

Non-inverting input, Channel 1

Inverting input, Channel 1

Non-inverting input, Channel 2

Inverting input, Channel 2

Non-inverting input, Channel 3

Inverting input, Channel 3

Non-inverting input, Channel 4

Inverting input, Channel 4

Positive (highest) supply

Negative (lowest) supply

Negative (lowest) supply

Submit Documentation Feedback

Copyright 19972016, Texas Instruments Incorporated

TLC2272, TLC2272A, TLC2272M, TLC2272AM

SLOS190H FEBRUARY 1997 REVISED MARCH 2016

Supply voltage, VDD+ (2)

Differential input voltage, VID (3)

Input current, II (any input)

Total current into VDD+

Input voltage, VI(any input) (2)

Total current out of VDD

Operating free-air temperature range, TA

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds

Storage temperature, Tstg

6.2 ESD Ratings

Human-body model (HBM), per AEC

Q-grade and M-grade devices in D and

Charged-device model (CDM), per

Q-grade and M-grade devices in D and

6.3 Recommended Operating Conditions

Common-mode input voltage

Copyright 19972016, Texas Instruments Incorporated

Submit Documentation Feedback

TLC2272, TLC2272A, TLC2272M, TLC2272AM

Recommended Operating Conditions (continued)

Operating free-air temperature

6.4 Thermal Information