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Index
Terms-Grid-connected
PV,high
step-up
converter,
1. INTRODUCTION
53
PVn
Micro-Inverter Based
Grid cOlmected-PV
PVn
DC-DC
Converter
Central
Inverter
DC-DC
Converter
PV
Central
Inverter
Central
Inverter
Micro-Inverter
3phase
( a)
To Grid
3phase
(b)
(c)
(d)
PVI
PV2
1---.......
--1 To Grid
---
Power Conditioner
. ---------------------------
,-----------------------------------------Do
12 :
MultiPort Cell
----------------------------
54
II.
PROPOSED TOPOLOGY
D[
I
I
I,
________________-+__w-___
1m
------+----
1m f++----+-+f--+---t-H--
IIA
Interval 1: [to, I
t l This interval starts when 51 and 53 are
turned on, simultaneously. Switch 52 is off in this interval.
Inductor Ll charges and L2 discharges into capacitor Ci.
During this interval diode Do is on and the power of load is
supplied by PV sources. Due to low value ofCk the current of
secondary side of the boosting transfonner varies sinusoidally
1
with the frequency of
0, and at the end of this interval,
27r L'""2
diode Do turns off and . s interval finishes.
Interval 2: [l
t ,2
t l This interval starts when diode Do turns
off. During this interval the state of switches remains constant
and no power is transfered to the output. In this interval the
output power is supplied by Co and the voltage of Ck remains
constant.i2 still charges Ci. at the end of this interval 53 is
turned off.
Interval 3: This interval occurs fast that during it, the
current that flew through switch 53 charges drain-source
capacitor(Coss) of 53 and discharges Coss of 52. when the
voltage of switch 52 reaches zero value, body diode of this
switch starts to conduct and now the currentiS3 flows through
body diode of switch 52. Due to AC current of capacitor
Ci, this phenomena occurs certainly. As a result Switch 52,
always, is turned on inZVS condition.
Interval 4: [2
t , t3l At start of this interval switch 52 is
turned on in zero-voltage condition. During this interval,
both switches 51 and 52 are on and input inductors store
------+---I
t(
I
I
t2
t4
t;
t7
55
--,
.:..
r"-rv'---==-.-t==-!f-;r-
"
.L.....l
'-----,---- __-+_
(b)
(a)
l:n
L. -
' I
D
."
\0,
D,
Co
:::" "
"
(c)
D
(::,-,
+
"I/o
V()
(d)
(f)
(g)
( 2)
3) Calculating Vrna:,,:
f!J;;.
III.
VCk(t)
ffi
Vrnin-nV2
Where WI is equal to
t5 +
.l:.k..
2C"
.
smwl (t - t4)
Vc"
nV2 +
JoTs
2Ck
(4)
nV2
(5)
lli
c"
.J
- t5 + 7r
at t 6) As the average
then the output
,
(1)
2
2V:max -Va + 1D2V
- D2
Where W2 is equal to
L"C"
2 '
L' C"
2
sinW2 (t-to )
(6)
n(V2 + Va,)
(7)
v2
7r V2LkCk.
Vrnax
(3)
k
2
nV2-(nV2- Vrnin)COSW(t-t4)
vc" (t5)
at t
n(V2 + Va,)
lvh
=
56
VI
(8)
35
ir====
=====------
Voltage gain for n=2
30 .......... Voltage gain for n=3
Voltage gain for n=4
25
........ . Conventional boost
--
20
15
10
0.4
0.5
0.6
Duty eycle D 1
0.7
0.8
B. Passive components
il
n(2Vc; -V2)
=
VI
i 2
( 9)
V.
V2D2T.,
2L2
(12)
(13)
EXPERIMENTAL RESULTS
DESIGN EXAMPLE
2Ll
(10)
VIDIT.,
IV.
A. Power Semiconductors
57
Tek
Stop
JL
..
M POS: 0,0005
n Vn'l
,.-J
"
CH1 5.001/
CH2 50,01,1
M 2.S0..us
eStop
..
..
JL
Tek
MPo;:-300,Ons
,JlJlj
2'
"
JL
Tek
MP05:1O.00n;
VOS2
eStop
..
M Pos: -300,On5
c
JlJlJ
'
CHl 50,(1\1
(b)
(a)
..
eStop
VDS2
UV""
JL
Tek
CH2"'S,OO,.,
(c)
M 5,OOw
(d)
:
,.
CHl 5.00\'/
CH2 50.0\'/
M 2.50)J
CHl 50.01,1
CH2 5.00A
(e)
M 5,oo)J5
(f)
Tek
JL
eStop
..
CHl 51),011
M Po;: -300,01"15
Tek
,JlJLj
CHl 50,01,1
CH2 2.00A
M 5,OO
CH2 5,00,0,
JL
CHl 50,0\'/
5,00)J5
(g)
eStop
CHl+-S.OOA
..
CH 50OV
M Po,: -300.0ns
CH2 5.00A
M 5.00
(h)
M 5.00)J5
(i)
Fig. 7: Experimental results. (a) VDS and Vcs of switch 51 , ( b) Vcs and ID of switch 51 , (c) VDS and Vcs of switch 52, (d)
Vcs and ID of switch 52, ( e) VDS and Vcs of switch 53, (f) Vcs and ID of switch 53, ( g) Vcs of switch 52 and primary
side current of the transformer, (h) secondary side voltage and current of the transformer, ( i) cathode-anode voltage and anode
current of the mUltiplier diodes, (j) cathode-anode voltage and anode current of the output diode.
VI.
CONCLUSION
58