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Data Sheet
December 8, 2015
FN2969.11
Features
L7 Process
2.5mA Drive Capability on All I/O Ports
Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10A
Ordering Information
PART NUMBERS
5MHz
PART
MARKING
8MHz
CP82C55A-5
(No longer available,
recommended
replacement:
CP82C55A-5Z)
CP82C55A-5
CP82C55A
CP82C55A-5Z (Note)
PART
MARKING
CP82C55A
CP82C55AZ
TEMP.
RANGE (C)
PACKAGE
0 to +70
40 Ld PDIP
0 to +70
40 Ld PDIP (Pb-free)
IP82C55A
-40 to +85
IP82C55AZ (Note)
IP82C55AZ
-40 to +85
CS82C55A*
CS82C55A*
0 to +70
PKG. DWG. #
E40.6
40 Ld PDIP
40 Ld PDIP (Pb-free)
CS82C55A-5*
(No longer available,
recommended
replacement:
CS82C55A-5Z)
CS82C55A-5
CS82C55A-5Z* (Note)
IS82C55A-5*
IS82C55A-5
IS82C55A*
IS82C55A*
-40 to +85
44 Ld PLCC
IS82C55A-5Z* (Note)
IS82C55A-5Z
IS82C55AZ* (Note)
IS82C55AZ
-40 to +85
44 Ld PLCC (Pb-free)
CQ82C55AZ (Note)
CQ82C55AZ
0 to +70
44 Ld MQFP (Pb-free)
IQ82C55AZ* (Note)
IQ82C55AZ
-40 to +85
44 Ld MQFP (Pb-free)
ID82C55A
ID82C55A
-40 to +85
40 Ld CERDIP
F40.6
MD82C55A/B
MD82C55A/B
-55 to +125
8406602QA
8406602QA
SMD#
8406602XA
8406602XA
SMD#
44 Ld CLCC
J44.A
0 to +70
44 Ld PLCC
N44.65
44 Ld PLCC (Pb-free)
Q44.10x10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2005, 2006, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
82C55A
Pinouts
WR
PA7
PA6
PA5
PA4
PA3
PA1
RD
CS
PA2
2 1 44 43 42 41 40
39 NC
38 RESET
37 D0
36 D1
35 D2
34 D3
33 D4
32 D5
31 D6
30 D7
29 NC
7
8
9
10
11
12
13
14
15
16
17
NC
VCC
PB7
PB6
PB5
PB4
PB3
WR
PA7
PA6
PA5
PA4
NC
PA3
PA1
RD
PA0
82C55A (MQFP)
TOP VIEW
RD
PA0
PA1
PA2
PA3
NC
PA4
PA5
PA6
PA7
WR
82C55A (PLCC)
TOP VIEW
PB2
18 19 20 21 22 23 24 25 26 27 28
PA2
13
14
15
16
17
18
19
20
6 5 4 3
GND
NC
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PB1
31
30
29
28
27
26
25
24
23
22
21
PA4
PA5
PA6
PA7
WR
RESET
D0
D1
D2
D3
D4
D5
D6
D7
VCC
PB7
PB6
PB5
PB4
PB3
PB0
40
39
38
37
36
35
34
33
32
1
2
3
4
5
6
7
8
9
10
11
12
PC3
PA3
PA2
PA1
PA0
RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
82C55A (CLCC)
TOP VIEW
PA0
6 5 4 3 2 1 44 43 42 41 40
44 43 42 41 40 39 38 37 36 35 34
33
2
32
RESET
A1
31
D1
A0
30
D2
PC7
29
D3
CS
GND
D0
25
D7
PC1
10
24
VCC
PC2
11
23
12 13 14 15 16 17 18 19 20 21 22
PB7
NC
D6
PC0
PB6
26
PB5
PB4
D5
PC4
PB3
D4
27
NC
28
PB2
PB1
PC6
PC5
NC
PB2
NC
PB3
PB4
PB5
PB6
PB7
18 1920 21 22 23 24 25 26 27 28
RESET
D0
D1
D2
D3
NC
D4
D5
D6
D7
VCC
PB0
39
38
37
36
35
34
33
32
31
30
29
PC3
7
8
9
10
11
12
13
14
15
16
17
PC2
PC3
PB0
PB1
CS
GND
A1
A0
PC7
NC
PC6
PC5
PC4
PC0
PC1
FN2969.11
December 8, 2015
82C55A
Pin Description
SYMBOL
TYPE
DESCRIPTION
VCC
VCC: The +5V power supply pin. A 0.1F capacitor between VCC and GND is recommended for decoupling.
GND
GROUND
D0-D7
I/O
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET
RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the Bus
Hold circuitry turned on.
CS
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU
communications.
RD
READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.
WR
WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A.
A0-A1
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three
ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus
A0, A1.
PA0-PA7
I/O
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port.
PB0-PB7
I/O
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PC0-PC7
I/O
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
Functional Diagram
+5V
POWER
SUPPLIES
GND
GROUP A
PORT A
(8)
GROUP A
CONTROL
GROUP A
PORT C
UPPER
(4)
BIDIRECTIONAL
DATA BUS
DATA BUS
BUFFER
D7-D0
8-BIT
INTERNAL
DATA BUS
RD
READ
WRITE
CONTROL
LOGIC
WR
A1
A0
GROUP B
CONTROL
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
I/O
PA7-PA0
I/O
PC7-PC4
I/O
PC3-PC0
I/O
PB7-PB0
RESET
CS
FN2969.11
December 8, 2015
82C55A
Functional Description
Data Bus Buffer
This three-state bidirectional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status
information are also transferred through the data bus buffer.
A1
A0
RD
WR
CS
POWER
SUPPLIES
+5V
GND
BIDIRECTIONAL
DATA BUS
DATA
BUS
D7-D0
BUFFER
RD
WR
A1
A0
RESET
READ
WRITE
CONTROL
LOGIC
GROUP A
CONTROL
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
8-BIT
INTERNAL
DATA BUS
GROUP B
CONTROL
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
I/O
PA7PA0
I/O
PC7PC4
I/O
PC3PC0
I/O
PB7PB0
CS
Ports A, B, and C
OUTPUT OPERATION
(WRITE)
DISABLE FUNCTION
X
The 82C55A contains three 8-bit ports (A, B, and C). All can
be configured to a wide variety of functional characteristics
by the system software but each has its own special features
or personality to further enhance the power and flexibility of
the 82C55A.
Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both pull-up and pull-down bus-hold devices
are present on Port A. See Figure 2A.
Port B One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.
Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
FN2969.11
December 8, 2015
82C55A
two 4-bit ports under the mode control. Each 4-bit port
contains a 4-bit latch and it can be used for the control signal
output and status signal inputs in conjunction with ports A
and B. See Figure 2B.
ADDRESS BUS
CONTROL BUS
DATA BUS
INPUT MODE
MASTER
RESET
OR MODE
CHANGE
RD, WR
INTERNAL
DATA IN
EXTERNAL
PORT A PIN
MODE 0
INTERNAL
DATA OUT
(LATCHED)
I/O
PB7-PB0
MODE 1
VCC
RESET
OR MODE
CHANGE
EXTERNAL
PORT B, C
PIN
INTERNAL
DATA OUT
(LATCHED)
I/O
PC7-PC4
I/O
CONTROL CONTROL
OR I/O
OR I/O
C
I/O
PA7-PA0
A
8
I/O
PA7-PA0
A
BIDIRECTIONAL
I/O
PB7-PB0
OUTPUT MODE
I/O
PC3-PC0
B
8
PB7-PB0
MODE 2
B
8
INTERNAL
DATA IN
A0-A1
CS
B
8
OUTPUT MODE
D7-D0
82C55A
CONTROL
PA7-PA0
Operational Description
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
Mode Selection
There are three basic modes of operation than can be
selected by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bidirectional Bus
When the reset input goes high, all ports will be set to the
input mode with all 24 port lines held at a logic one level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional
initialization required. This eliminates the need to pull-up or
pull-down resistors in all-CMOS designs. The control word
register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheral devices with a simple software
maintenance routine. Any port programmed as an output
port is initialized to all zeros when the control word is written.
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP A
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
FN2969.11
December 8, 2015
82C55A
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be tailored to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display
computational results, Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an interruptdriven basis.
Operating Modes
BIT SET/RESET
1 = SET
0 = RESET
DONT
CARE
BIT SELECT
0 1 2 3 4
0 1 0 1 0
0 0 1 1 0
0 0 0 0 1
5
1
0
1
6
0
1
1
7
1 B0
1 B1
1 B2
GROUP A
PORT C
PORT A (Upper)
GROUP B
#
PORT C
PORT B (Lower)
D4
D3
D1
D0
Output
Output
Output
Output
Output
Output
Output
Input
Output
Output
Input
Output
Output
Output
Input
Input
Output
Input
Output
Output
Output
Input
Output
Input
Output
Input
Input
Output
Output
Input
Input
Input
Input
Output
Output
Output
Input
Output
Output
Input
Input
Output
10
Input
Output
Input
Output
11
Input
Input
Input
Input
12
Output
Output
Input
Input
13
Output
Input
Input
Input
14
Input
Output
Input
Input
15
Input
Input
FN2969.11
December 8, 2015
82C55A
Mode 0 (Basic Input)
tRR
RD
tIR
tHR
INPUT
tAR
tRA
CS, A1, A0
D7-D0
tRD
tDF
WR
tWD
tDW
D7-D0
tAW
tWA
CS, A1, A0
OUTPUT
tWB
Mode 0 Configurations
CONTROL WORD #0
CONTROL WORD #2
D7 D6 D5 D4 D3 D2 D1 D0
1
A
82C55A
1
8
4
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
0
A
PC7 - PC4
C
D7 - D0
PC3 - PC0
PB7 - PB0
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
CONTROL WORD #3
0
D7 D6 D5 D4 D3 D2 D1 D0
1
A
82C55A
D7 - D0
82C55A
D7 D6 D5 D4 D3 D2 D1 D0
0
PA7 - PA0
CONTROL WORD #1
1
8
4
PA7 - PA0
A
82C55A
PC7 - PC4
D7 - D0
PC3 - PC0
PB7 - PB0
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
FN2969.11
December 8, 2015
82C55A
Mode 0 Configurations (Continued)
CONTROL WORD #4
CONTROL WORD #8
D7 D6 D5 D4 D3 D2 D1 D0
1
A
82C55A
1
8
4
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
PB7 - PB0
PC7 - PC4
PC3 - PC0
PB7 - PB0
1
A
PC7 - PC4
C
D7 - D0
PC3 - PC0
PB7 - PB0
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
D7 D6 D5 D4 D3 D2 D1 D0
1
8
4
D7 - D0
PA7 - PA0
A
82C55A
C
D7 - D0
PC3 - PC0
PB7 - PB0
8
4
PC7 - PC4
CONTROL WORD #7
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
D7 D6 D5 D4 D3 D2 D1 D0
1
D7 D6 D5 D4 D3 D2 D1 D0
1
A
82C55A
D7 - D0
82C55A
82C55A
PA7 - PA0
PA7 - PA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 - D0
8
4
PC3 - PC0
CONTROL WORD #6
0
A
D7 D6 D5 D4 D3 D2 D1 D0
D7 - D0
PC7 - PC4
82C55A
CONTROL WORD #9
82C55A
D7 D6 D5 D4 D3 D2 D1 D0
0
PA7 - PA0
CONTROL WORD #5
1
8
4
PA7 - PA0
A
82C55A
PC7 - PC4
D7 - D0
PC3 - PC0
PB7 - PB0
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
FN2969.11
December 8, 2015
82C55A
Mode 0 Configurations (Continued)
CONTROL WORD #12
D7 D6 D5 D4 D3 D2 D1 D0
1
A
82C55A
1
8
4
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
0
8
A
82C55A
PC7 - PC4
C
D7 - D0
PC3 - PC0
PB7 - PB0
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
D7 D6 D5 D4 D3 D2 D1 D0
0
PA7 - PA0
1
A
82C55A
1
8
4
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
PA7 - PA0
A
82C55A
PC7 - PC4
C
D7 - D0
PC3 - PC0
PB7 - PB0
Operating Modes
Mode 1 - (Strobed Input/Output). This functional
configuration provides a means for transferring I/O data to or
from a specified port in conjunction with strobes or hand
shaking signals. In mode 1, port A and port B use the lines
on port C to generate or accept these hand shaking
signals.
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
MODE 1 (PORT A)
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
1/0
INTE
A
PC6, PC7
1 = INPUT
0 = OUTPUT
PA7-PA0
PC4
STBA
PC5
IBFA
INTRA
PC3
RD
PC6, PC7
I/O
MODE 1 (PORT B)
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
PB7-PB0
INTE
B
PC2
STBB
PC1
IBFB
PC0
INTRB
(Figures 6 and 7)
RD
FN2969.11
December 8, 2015
82C55A
tST
STB
tSIB
IBF
tSIT
tRIB
INTR
tRIT
RD
tPH
INPUT FROM
PERIPHERAL
tPS
INTE A
INTE A
Controlled by bit set/reset of PC4.
INTE B
INTE B
Controlled by Bit Set/Reset of PC2.
NOTE:
1. To strobe data into the peripheral device, the user must operate
the strobe line in a hand shaking mode. The user needs to send
OBF to the peripheral device, generates an ACK from the
peripheral device and then latch data into the peripheral device
on the rising edge of OBF.
MODE 1 (PORT A)
PA7-PA0
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
1/0
PC4, PC5
1 = INPUT
0 = OUTPUT
INTE
A
PC7
OBFA
PC6
ACKA
INTRA
PC3
WR
PC4, PC5
MODE 1 (PORT B)
PB7-PB0
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
INTE
B
PC1
OBFB
PC2
ACKB
PC0
INTRB
WR
10
FN2969.11
December 8, 2015
82C55A
tWOB
WR
tAOB
OBF
INTR
tWIT
ACK
tAK
tAIT
OUTPUT
tWB
PA7-PA0
RD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
1/0
0
PC6, PC7
1 = INPUT
0 = OUTPUT
PC4
STBA
PC5
IIBFA
PC3
INTRA
PC6, PC7
PB7, PB0
WR
PA7-PA0
WR
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
1/0
I/O
PC7
OBFA
PC6
ACKA
INTRA
PC3
1
PC4, PC5
1 = INPUT
0 = OUTPUT
PC4, PC5
PB7, PB0
I/O
PC1
OBFB
PC2
STBB
PC2
ACKB
PC1
IBFB
PC0
INTRB
PC0
INTRB
RD
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
FIGURE 10. COMBINATIONS OF MODE 1
Operating Modes
Output Operations
ACK - (Acknowledge). A low on this input enables the threestate output buffer of port A to send out the data. Otherwise,
the output buffer will be in the high impedance state.
INTE 1 - (The INTE flip-flop associated with OBF).
Controlled by bit set/reset of PC4.
Input Operations
STB - (Strobe Input). A low on this input loads data into the
input latch.
IBF - (Input Buffer Full F/F). A high on this output indicates
that data has been loaded into the input latch.
INTE 2 - (The INTE flip-flop associated with IBF). Controlled
by bit set/reset of PC4.
FN2969.11
December 8, 2015
82C55A
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
INTRA
PC3
PA7-PA0
PC2-PC0
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
PC7
OBFA
INTE
1
PC6
ACKA
INTE
2
PC4
STBA
PC5
IBFA
WR
GROUP B MODE
0 = MODE 0
1 = MODE 1
PC2-PC0
RD
I/O
DATA FROM
CPU TO 82C55A
WR
tAOB
OBF
tWOB
INTR
tAK
ACK
tST
STB
tSIB
IBF
tAD
tPS
tKD
PERIPHERAL
BUS
tRIB
tPH
RD
DATA FROM
PERIPHERAL TO 82C55A
DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD + OBF MASK
ACK WR)
FIGURE 13. MODE 2 (BIDIRECTIONAL)
12
FN2969.11
December 8, 2015
82C55A
MODE 2 AND MODE 0 (INPUT)
1/0
PC2-PC0
1 = INPUT
0 = OUTPUT
PA7-PA0
8
OBFA
PC7
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
PC6
ACKA
PC4
STBA
PC5
IBFA
PC2-PC0
PC3
INTRA
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
I/O
PB7-PB0
PC7
OBFA
PC6
ACKA
PC4
STBA
IBFA
PC5
PC2-PC0
PB7, PB0
I/O
WR
OBFA
ACKA
PC4
STBA
PC5
IBFA
PC1
RD
WR
PA7-PA0
PC6
PB7-PB0
PC3
INTRA
PC7
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
1/0
RD
WR
PC2-PC0
1 = INPUT
0 = OUTPUT
RD
INTRA
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
PC7
OBFA
PC6
ACKA
PC4
STBA
PC5
IBFA
PB7-PB0
8
OBFB
PC2
ACKB
PC0
INTRB
RD
WR
INTRA
PC2
STBB
PC1
IBFB
PC0
INTRB
13
FN2969.11
December 8, 2015
82C55A
MODE DEFINITION SUMMARY
MODE 0
MODE 1
MODE 2
IN
OUT
IN
OUT
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
INTRB
IBFB
STBB
INTRA
STBA
IBFA
I/O
I/O
INTRB
OBFB
ACKB
INTRA
I/O
I/O
ACKA
OBFA
GROUP A ONLY
Mode 0
or Mode 1
Only
I/O
I/O
I/O
INTRA
STBA
IBFA
ACKA
OBFA
INPUT CONFIGURATION
D7
D6
D5
I/O
I/O
IBFA
D4
D3
D2
GROUP A
D1
D0
IBFB
INTRB
GROUP B
OUTPUT CONFIGURATION
D7
D6
OBFA INTEA
D5
D4
I/O
I/O
D3
D2
D1
D0
GROUP A
GROUP B
D6
OBFA INTE1
D5
IBFA
D4
D3
INTE2 INTRA
GROUP A
D2
D1
D0
GROUP B
14
FN2969.11
December 8, 2015
82C55A
Modes 1 or 2, Port C generates or accepts hand shaking
signals with the peripheral device. Reading the contents of
Port C allows the programmer to test or verify the status of
each peripheral device and change the program flow
accordingly.
There is not a special instruction to read the status
information from Port C. A normal read operation of Port C is
executed to perform this function.
INTERRUPT
ENABLE FLAG
POSITION
ALTERNATE PORT C
PIN SIGNAL (MODE)
INTE B
PC2
INTE A2
PC4
INTE A1
PC6
INTERRUPT
REQUEST
PC3
MODE 1
(OUTPUT)
82C55A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC7
PC6
PC5
PC4
HIGH SPEED
PRINTER
HAMMER
RELAYS
DATA READY
ACK
PAPER FEED
FORWARD/REV.
PB0
PB1
PB2
PB3
PB4
MODE 1 PB5
(OUTPUT) PB6
PB7
PC1
PC2
PAPER FEED
FORWARD/REV.
RIBBON
CARRIAGE SEN.
DATA READY
ACK
PC0
INTERRUPT
REQUEST
CONTROL LOGIC
AND DRIVERS
15
FN2969.11
December 8, 2015
82C55A
INTERRUPT
REQUEST
PC3
MODE 1
(INPUT)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
R0
R1
R2
FULLY
R3
DECODED
R4
KEYBOARD
R5
SHIFT
CONTROL
PC4
PC5
STROBE
ACK
INTERRUPT
REQUEST
PC3
MODE 1
(INPUT)
82C55A
PB0
PB1
PB2
PB3
PB4
MODE 1 PB5
(OUTPUT) PB6
PB7
B0
B1
B2
BURROUGHS
SELF-SCAN
B3
DISPLAY
B4
B5
BACKSPACE
CLEAR
MODE 0
(INPUT)
DATA READY
ACK
BLANKING
CANCEL WORD
PC1
PC2
PC6
PC7
82C55A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
R0
R1
R2
FULLY
R3
DECODED
R4
KEYBOARD
R5
SHIFT
CONTROL
PC4
PC5
PC6
PC7
STROBE
ACK
BUST LT
TEST LT
TERMINAL
ADDRESS
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
INTERRUPT
REQUEST
INTERRUPT
REQUEST
PA0
PA1
PA2
PA3
PA4
MODE 0 PA5
(OUTPUT) PA6
PA7
PC4
PC5
PC6
PC7
82C55A
PC0
PC1
BIT
SET/RESET PC2
PC3
PB0
PB1
PB2
MODE 0
(INPUT)
PB3
PB4
PB5
PB6
PB7
LSB
PC3
12-BIT
D/A
CONVERTER
(DAC)
ANALOG
OUTPUT
PA0
PA1
PA2
PA3
PA4
PA5
MODE 1 PA6
(OUTPUT)
PA7
MSB
82C55A
STB DATA
SAMPLE EN
STB
LSB
8-BIT
A/D
CONVERTER
(ADC)
ANALOG
INPUT
MSB
16
R0
R1
R2
CRT CONTROLLER
R3
CHARACTER GEN.
REFRESH BUFFER
R4
CURSOR CONTROL
R5
SHIFT
CONTROL
PC7
PC6
PC5
PC4
DATA READY
ACK
BLANKED
BLACK/WHITE
PC2
PC1
PC0
ROW STB
COLUMN STB
CURSOR H/V STB
PB0
MODE 0 PB1
(OUTPUT) PB2
PB3
PB4
PB5
PB6
PB7
CURSOR/ROW/COLUMN
ADDRESS
H&V
FN2969.11
December 8, 2015
82C55A
INTERRUPT
REQUEST
INTERRUPT
REQUEST
PC3
MODE 2
82C55A
PC3
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
D0
D1
D2
D3
D4
D5
D6
D7
PC4
PC5
PC7
PC6
DATA STB
ACK (IN)
DATA READY
ACK (OUT)
PC2
PC1
PC0
TRACK 0 SENSOR
SYNC READY
INDEX
PB0
PB1
PB2
MODE 0 PB3
(OUTPUT) PB4
PB5
PB6
PB7
FLOPPY DISK
CONTROLLER
AND DRIVE
ENGAGE HEAD
FORWARD/REV.
READ ENABLE
WRITE ENABLE
DISC SELECT
ENABLE CRC
TEST
BUSY LT
17
MODE 1
(INPUT)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
R0
R1
R2
R3
R4
R5
R6
R7
PC4
PC5
PC6
STB
ACK
STOP/GO
MACHINE TOOL
82C55A
MODE 0
(INPUT)
B LEVEL
PAPER
TAPE
READER
PC0
PC1
PC2
PB0
PB1
PB2
MODE 0 PB3
(OUTPUT) PB4
PB5
PB6
PB7
START/STOP
LIMIT SENSOR (H/V)
OUT OF FLUID
CHANGE TOOL
LEFT/RIGHT
UP/DOWN
HOR. STEP STROBE
VERT. STEP STROBE
SLEW/STEP
FLUID ENABLE
EMERGENCY STOP
FN2969.11
December 8, 2015
82C55A
Absolute Maximum Ratings TA = +25C
Thermal Information
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V
Operating Temperature Range
CX82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
IX82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 85C
MX82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55C to 125C
Die Characteristics
JA (C/W)
JC(C/W)
CERDIP Package. . . . . . . . . . . . . . . . .
50
10
CLCC Package . . . . . . . . . . . . . . . . . .
65
14
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
PLCC Package. . . . . . . . . . . . . . . . . . .
55
N/A
MQFP Package . . . . . . . . . . . . . . . . . .
62
N/A
Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C
Maximum Junction Temperature
CDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175C
PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C
(PLCC and MQFP Lead Tips Only)
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
VIH
2.0
2.2
VIL
0.8
3.0
VCC -0.4
0.4
VOH
IOH = -2.5mA,
IOH = -100A
VOL
IOL +2.5mA
II
-1.0
+1.0
IO
VO = VCC or GND, D0 - D7
-10
+10
VO = 3.0V. Ports A, B, C
TA = -55C
-50
-450
TA = +128C
-50
-400
TA = -55C
50
450
TA = +128C
50
400
-2.5
Note 2, 4
mA
IBHH
IBHL
IDAR
ICCSB
10
ICCOP
mA/MHz
NOTES:
2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current.
3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0s I/O Read/Write cycle time = 1mA).
4. Tested as VOH at -2.5mA.
Capacitance TA = +25C
SYMBOL
PARAMETER
TYPICAL
UNITS
CIN
Input Capacitance
10
pF
CI/O
I/O Capacitance
20
pF
18
TEST CONDITIONS
FREQ = 1MHz, All Measurements are referenced to
device GND
FN2969.11
December 8, 2015
82C55A
AC Electrical Specifications
SYMBOL
PARAMETER
82C55A
MIN
MAX
MIN
MAX
UNITS
TEST
CONDITIONS
READ TIMING
(1) tAR
ns
(2) tRA
ns
(3) tRR
RD Pulse Width
250
150
ns
(4) tRD
200
120
ns
(5) tDF
10
75
10
75
ns
(6) tRV
300
300
ns
WRITE TIMING
(7) tAW
ns
(8) tWA
20
20
ns
(9) tWW
WR Pulse Width
100
100
ns
(10) tDW
100
100
ns
(11) tWD
30
30
ns
OTHER TIMING
(12) tWB
WR = 1 to Output
350
350
ns
(13) tIR
ns
(14) tHR
ns
(15) tAK
200
200
ns
(16) tST
100
100
ns
(17) tPS
20
20
ns
(18) tPH
50
50
ns
(19) tAD
ACK = 0 to Output
175
175
ns
(20) tKD
20
250
20
250
ns
(21) tWOB
WR = 1 to OBF = 0
150
150
ns
(22) tAOB
ACK = 0 to OBF = 1
150
150
ns
(23) tSIB
STB = 0 to IBF = 1
150
150
ns
(24) tRIB
RD = 1 to IBF = 0
150
150
ns
(25) tRIT
RD = 0 to INTR = 0
200
200
ns
(26) tSIT
STB = 1 to INTR = 1
150
150
ns
(27) tAIT
ACK = 1 to INTR = 1
150
150
ns
(28) tWIT
WR = 0 to INTR = 0
200
200
ns
(29) tRES
500
500
ns
1, (Note)
NOTE: Period of initial Reset pulse after power-on must be at least 50sec. Subsequent Reset pulses may be 500ns minimum.
19
FN2969.11
December 8, 2015
82C55A
Timing Waveforms
tRR (3)
RD
tIR (13)
tHR (14)
INPUT
tAR (1)
tRA (2)
CS, A1, A0
D7-D0
tRD (4)
tDF (5)
tWW (9)
WR
tDW
(10)
tWD (11)
D7-D0
tAW (7)
tWA (8)
CS, A1, A0
OUTPUT
tWS (12)
tST (16)
STB
tSIB
(23)
IBF
tSIT
(26)
tRIB (24)
tRIT
(25)
INTR
RD
tPH
(18)
INPUT FROM
PERIPHERAL
tPS (17)
20
FN2969.11
December 8, 2015
82C55A
Timing Waveforms
(Continued)
tWOB (21)
WR
tAOB (22)
OBF
tWIT
(28)
INTR
ACK
tAK (15)
tAIT (27)
OUTPUT
tWB (12)
DATA FROM
CPU TO 82C55A
WR
(NOTE)
tAOB
(22)
OBF
tWOB
(21)
INTR
tAK
(15)
ACK
tST
(16)
STB
(NOTE)
tSIB
(23)
IBF
tAD (19)
tPS (17)
tKD
(20)
PERIPHERAL
BUS
tRIB (24)
tPH (18)
RD
DATA FROM
PERIPHERAL TO 82C55A
DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
21
FN2969.11
December 8, 2015
82C55A
Timing Waveforms
(Continued)
A0-A1,
CS
tWA (8)
tAW (7)
DATA
BUS
tDW (10)
tWD (11)
A0-A1,
CS
tRA (2)
tAR (1)
tRR (3)
RD
(4) tRD
WR
tDF (5)
DATA
BUS
VALID
tWW (9)
HIGH IMPEDANCE
AC Test Circuit
INPUT
OUTPUT
VIH + 0.4V
VOH
1.5V
R1
OUTPUT FROM
DEVICE UNDER
TEST
TEST
POINT
R2
C1
(SEE NOTE)
1.5V
VIL - 0.4V
VOL
22
TEST CONDITION
V1
R1
R2
C1
1.7V
523
Open
150pF
VCC
2k
1.7k
50pF
1.5V
750
Open
50pF
FN2969.11
December 8, 2015
82C55A
Burn-In Circuits
CERDIP
37
F14
36
F2
F3
35
F5
GND
34
GND
F2
F4
F14
F9
F13
F13
F11
38
F12
F6
F12
F8
F7
F11
39
F8
40
F9
F7
F4
F6
F3
CLCC
1 44 43 42 41 40
39
F15
38
F5
F0
33
F11
F0
37
F15
F1
32
F12
10
36
F10
10
31
F13
F1
F10
11
35
F11
F12
F6
11
30
F14
F6
12
34
F13
F7
13
33
F14
F8
14
32
F15
F9
15
31
F11
F10
16
30
F12
F6
17
29
26
F6
16
25
F13
F7
17
24
F14
F8
18
23
F15
F9
19
22
F11
F10
20
21
F12
NOTES:
C1
18 19 20 21 22 23 24 25 26 27 28
C1
F13
15
VCC
VCC
F10
F12
F14
27
F15
14
F11
F9
F12
F11
F10
F15
28
F9
29
13
F8
12
F8
F7
F7
NOTES:
1. C1 = 0.01F minimum
3. f0 = 100kHz 10%
4. GND = 0V
4. f1 = f0 2; f2 = f1 2; . . . ; f15 = f14 2
23
FN2969.11
December 8, 2015
82C55A
GLASSIVATION:
Die Characteristics
Type: SiO2
Thickness: 8k 1k
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11k 1k
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7 WR
RESET
CS
D0
GND
D1
A1
D2
A0
D3
PC7
D4
PC6
D5
PC5
D6
PC4
D7
PC0
VCC
PC1
PC2
24
PC3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
FN2969.11
December 8, 2015
82C55A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
December 8, 2015
FN2969.11
CHANGE
- Ordering Information Table on page 1.
- Added Revision History.
- Added About Intersil Verbiage.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
25
FN2969.11
December 8, 2015
82C55A
Dual-In-Line Plastic Packages (PDIP)
E40.6 (JEDEC MS-011-AC ISSUE B)
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-
-C-
SEATING
PLANE
A2
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MAX
NOTES
0.250
6.35
0.015
0.39
A2
0.125
0.195
3.18
4.95
0.014
0.022
0.356
0.558
C
L
B1
0.030
0.070
0.77
1.77
eA
0.008
0.015
0.204
0.381
1.980
2.095
D1
0.005
A
L
D1
MIN
A
E
BASE
PLANE
MAX
A1
-AD
MILLIMETERS
MIN
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the MO Series Symbol List in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
50.3
53.2
0.13
0.600
0.625
15.24
15.87
E1
0.485
0.580
12.32
14.73
0.100 BSC
2.54 BSC
eA
0.600 BSC
15.24 BSC
eB
0.700
17.78
0.115
0.200
2.93
5.08
40
40
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
26
FN2969.11
December 8, 2015
82C55A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)
40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
(c)
E
M
-Bbbb S
C A-B S
Q
-C-
SEATING
PLANE
S1
b2
b
ccc M
C A-B S
eA/2
0.225
5.72
0.026
0.36
0.66
b1
0.014
0.023
0.36
0.58
b2
0.045
0.065
1.14
1.65
b3
0.023
0.045
0.58
1.14
0.008
0.018
0.20
0.46
c1
0.008
0.015
0.20
0.38
2.096
53.24
0.510
0.620
15.75
aaa M C A - B S D S
D S
NOTES
0.014
eA
e
MAX
A A
MIN
A
L
MILLIMETERS
MAX
M
(b)
BASE
PLANE
MIN
b1
SECTION A-A
D S
INCHES
SYMBOL
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturers identification shall not be used
as a pin one identification mark.
12.95
0.100 BSC
2.54 BSC
eA
0.600 BSC
15.24 BSC
eA/2
0.300 BSC
7.62 BSC
0.125
0.200
3.18
5.08
0.015
0.070
0.38
1.78
S1
0.005
0.13
105o
90o
105o
90o
aaa
0.015
0.38
bbb
0.030
0.76
ccc
0.010
0.25
0.0015
0.038
2, 3
40
40
8
Rev. 0 4/94
27
FN2969.11
December 8, 2015
82C55A
Ceramic Leadless Chip Carrier Packages (CLCC)
J44.A
0.010 S E H S
D
INCHES
D3
SYMBOL
j x 45o
E3
h x 45o
0.010 S E F S
A
A1
PLANE 2
PLANE 1
-E-
B1
e
L
-H-
L3
MILLIMETERS
MAX
MAX
NOTES
0.064
0.120
1.63
3.05
6, 7
0.054
0.088
1.37
2.24
0.033
0.039
0.84
0.99
B1
0.022
0.028
0.56
0.71
2, 4
B2
0.072 REF
1.83 REF
B3
0.006
0.022
0.15
0.56
0.640
0.662
16.26
16.81
D1
0.500 BSC
12.70 BSC
D2
0.250 BSC
6.35 BSC
D3
0.662
0.640
0.662
16.26
16.81
16.81
E1
0.500 BSC
12.70 BSC
E2
0.250 BSC
6.35 BSC
E3
e
0.662
0.050 BSC
0.015
16.81
1.27 BSC
0.38
2
-
0.040 REF
1.02 REF
0.020 REF
0.51 REF
0.045
0.055
1.14
1.40
L1
0.045
0.055
1.14
1.40
L2
0.075
0.095
1.90
2.41
L3
0.003
0.015
0.08
0.38
ND
11
11
NE
11
11
44
44
-F-
3
Rev. 0 5/18/94
B3
E1
E2
MIN
A1
e1
0.007 M E F S H S
MIN
L2
B2
L1
D2
e1
D1
NOTES:
28
FN2969.11
December 8, 2015
82C55A
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
0.025 (0.64)
R
0.045 (1.14)
0.050 (1.27) TP
C
L
D2/E2
E1 E
C
L
D2/E2
VIEW A
0.020 (0.51)
MIN
A1
A
D1
D
SEATING
-C- PLANE
0.026 (0.66)
0.032 (0.81)
MAX
MILLIMETERS
MIN
MAX
NOTES
0.165
0.180
4.20
4.57
A1
0.090
0.120
2.29
3.04
0.685
0.695
17.40
17.65
D1
0.650
0.656
16.51
16.66
D2
0.291
0.319
7.40
8.10
4, 5
0.685
0.695
17.40
17.65
E1
0.650
0.656
16.51
16.66
E2
0.291
0.319
7.40
8.10
4, 5
44
44
6
Rev. 2 11/97
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
MIN
VIEW A TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. N is the number of terminal positions.
29
FN2969.11
December 8, 2015
82C55A
Metric Plastic Quad Flatpack Packages (MQFP)
D
D1
-D-
INCHES
SYMBOL
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.076
0.003
-C-
12o-16o
0.40
0.016 MIN
0.20
M
0.008
C A-B S
0o MIN
D S
b
A2 A1
0o-7o
b1
30
MILLIMETERS
MIN
MAX
NOTES
0.096
2.45
A1
0.004
0.010
0.10
0.25
A2
0.077
0.083
1.95
2.10
0.012
0.018
0.30
0.45
b1
0.012
0.016
0.30
0.40
0.515
0.524
13.08
13.32
D1
0.389
0.399
9.88
10.12
4, 5
0.516
0.523
13.10
13.30
E1
0.390
0.398
9.90
10.10
4, 5
0.029
0.040
0.73
1.03
44
44
0.032 BSC
0.80 BSC
Rev. 2 4/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
BASE METAL
WITH PLATING
MAX
0.13/0.17
0.005/0.007
12o-16o
MIN
FN2969.11
December 8, 2015
Mouser Electronics
Authorized Distributor
Intersil:
CP82C55A CS82C55A ID82C55A IP82C55A IS82C55A IS82C55A-5 CP82C55A-5Z CP82C55AZ CQ82C55AZ
CS82C55A-5Z CS82C55A-5Z96 CS82C55AZ CS82C55AZ96 IP82C55AZ IQ82C55AZ IQ82C55AZ96 IS82C55A5Z IS82C55A-5Z96 IS82C55AZ IS82C55AZ96