Conductivity behavior in polycrystalline semiconductor thin film transistors

J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider

Citation: Journal of Applied Physics 53, 1193 (1982); doi: 10.1063/1.330583
View online: http://dx.doi.org/10.1063/1.330583
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Conductivity behavior in polycrystalline semiconductor thin film transistors

J. Levinson, a) F. R. Shepherd, P. J. Scanlon, b) W. D. Westwood, G. Este, and M. Rider
Bell-Northern Research, P. O. Box 3511, Station C, Ottawa, Canada Kl Y 4H7

(Received 7 May 1981; accepted for publication 12 August 1981)

CdSe thin film transistor (TFT) structures which have been ion implanted with 50 keY 52Cr, 50
keY 27AI, or 15 keY lIB have a very steeply rising conductivity above some threshold dose and
exhibit modulated transistor characteristics over certain ranges of implant dose, even though
there is no thermal annealing during or after ion implantation. These results are interpreted using
a model based on grain boundary trapping theory. The dependence ofleakage current on implant
dose, and of drain current (at a fixed dose) on gate voltage are described very well by this model,
when the drain voltage is very small. Using this simple model, the important parameters of the
polycrystalline CdSe film, namely the trap density per unit area in the grain boundary, the donor
density, grain size, and electron mobility can be deduced. The effect of thermal annealing on
implanted and unimplanted CdSe TFT's has also been studied and the model appears to give a
general description of the conductivity behavior in polycrystalline semiconductor TFT's. This is
illustrated by applying the model to devices fabricated by other groups from polycrystalline CdSe,
poly-Si and laser-annealed poly-Si semiconductor layers.
PACS numbers: 85.30.De, 73.60.Fw
I. INTRODUCTION

Thin film transistors (TFT's) are of interest for addressing flat panel displays where the desired circuitry extends to
dimensions larger than Si wafers. 1.2 Most of the work reported uses evaporated CdSe as the semiconductor but FET's
with other deposited materials including poly-SV laser an5
nealed polycrystalline sV and amorphous hydrogenated Si
have recently been demonstrated. CdSe TFT's have been
fabricated by evaporation of successive layers through thin
metal masks in contact with the substrate,6 and by conventional photoengraving techniques,1 but in both cases a thermal annealing cycle is usually required. Device characteristics are often very dependent on thermal annealing. It has
been suggested that diffusion of metal either from the
source-drain contacts7 H (usually Cr or AI) or from a thin
metal layer (e.g., In), deposited adjacent to the semiconduclO
tor,9 causes n-type doping in the CdSe, but other authors
have reported no significant diffusion from Cr contacts during annealing.
The conductivity in polycrystalline CdSe and CdS films
has been described by many authors 1 1-14 in terms of potential
barriers at the grain boundaries. Although the barrier height
was related to the difference in carrier concentrations between the grains and grain boundaries, no explicit expressio~
for the dependence of barrier height on donor and trap denSIties was given. Others,'5-'9 mainly in the case ofpoly-Si, have
assumed a grain depletion and grain boundary trapping
model to be responsible for the barrier formation and derived explicit expressions for the barrier dependence on do20
nor and trap densities. We have recently shown that the
same theory can be applied to poly crystalline CdSe, doped
by ion implantation.

'Permanent address: Soreq Nuclear Research Center, Yavne 70600, Israel.

"'Permanent address: Physics Department, Queen's University, Kingston,
Ontario.
1193

J. Appl. Phys. 53(2), February 1982

Here we describe how this model can explain the behavior of conductivity in both thermally annealed and ion implanted CdSe TFT's. The model accounts for the effect of
different donor densities and gate-induced charge carriers,
and provides an estimate of trap density, donor density,
grain size, and mobility. This in turn allows a comparison to
be made between TFT's fabricated by various groups and
with different polycrystalline semiconductors.
II. THE GRAIN BOUNDARY TRAPPING MODEL

Many authors (e,g., Refs. 15-19) have described this

model in detail. For example Kamins, 16 Seto, 18 and Baccarani et al. 19 have successfully used this model to describe the
dependence of the conductivity of poly-Si on donor concentration and trap density. Here we summarize the important
features of the model, and give the basic equations which are
referred to in the discussion below.
It is assumed that the polycrystalline material is composed of a linear chain of identical crystallites having a grain
size L. There is a concentration of shallow donors N D (per
unit volume) which are uniformly distributed and totally
ionized. The grain boundary is of negligible thickness compared to L and contains a concentration ,'V, (per unit area) of
traps located at energy E, with respect to the intrinsic Fermi
level. The traps are assumed to be initially neutral and become charged by trapping a carrier. In order to calculate the
energy band diagram, the above assumptions and an abrupt
depletion approximation are used, as is shown in Fig. 1.
The transport properties are calculated in one dimension, assuming that the current is governed by thermionic
emission above the grain boundary barrier and that no scattering is taking place in the grains. For q Vd <kT, where Vd is
the voltage drop across a grain boundary, one can then write

(Vc)

J = q2 no kT Vd exp ( - EBlkT),

(1 )

where J is the current density across a barrier, no is the con-

0021-8979/82/021193-10$02.40

1982 American Institute of PhYSics

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grain boundary

crystallite

-- -

On

U
~

Ec = 1/2 EG

conductivity depends on the grain boundary barrier height

E B which decreases with increasing donor concentration
[Eq. (4)]. This means that for donor concentrations below
Nt the conductivity is very low due to the lack of carriers,
which are all trapped, whereas above Nt the conductivity
increases rapidly with increasing donor concentration due to
both the increase in free carrier concentration and the decrease in barrier height. The conductivity described by thermionic emission above the grain boundary barrier E B' in Eq.
(4), can be written as 21

r-'1r

j(-----JE B

- - - - - - - - - - - - - - - - - - -- EF

- __C

-l--

A ... ________ ~_,l ' .... _____ E

-- - -_ ...,-\,

_ _...... ,,_ _ _ _ J , , _ _ _

Ev

where/-to

FIG. I. Grain structure, charge distribution and band diagram assumed in

the grain boundary trapping model.

centration of free carriers in the grain, and E B is the barrier

height. Vd = VDIN, where VD is the total voltage drop
across the sample, N is the number of grain boundaries, and
Vc = [(kT)I(21Tm*)] 1/2 is a thermal collection velocity,
where m* is the effective mass of the carriers.
According to this theory for a monoenergetic trap level,
the properties of the films change markedly, depending on
the combination of two conditions. One is the degree of depletion of the grains and the other is the degree of trap occupancy. There will be an impurity concentration N 1; such
that when N D < N 1; the crys~allites are fully depleted, while
partial depletion of the grain occurs when N D > Nt. When
the traps are filled,

Nt-:::=. JV,IL.

(2)

For fully depleted grains (ND < N 1;) and either partially
filled or filled traps, the conductivity has the form 19
(7

q2L 2NcNDVc ex [_ (1I2EG - E, )],

2kT(JV, _ LND) P
kT

(3)

where Nc is the effective density of states in the conduction

band in the grain, EG is the band gap, and all the energies are
measured from the intrinsic Fermi level in the grain.
For partially depleted grains (ND > N 1;) and filled
traps, such that the Fermi level is well above the trap level,
(compared to kT), the conductivity will have the form 19
(7

= (q2LnovclkT) exp (- EBlkT),

(4)

where EB-:::=.q2~/8END'
Baccarani et al. 19 also described the case in which both
the grains are partially depleted and the traps partially filled.
This situation was not observed in our experimental results
and will not be discussed further. As one can see for
N D < N 1;, when the grains are fully depleted the conductivity is characterized by an activation energy equal to the difference between the conduction band and the trapping level
[Eq. (3)], which does not depend on the donor concentration.
Since the grains are fully depleted, conductivity only occurs
by excitation of electrons out of the traps. For N D > N 1;, the
1194

J. Appl. Phys., Vol. 53, No.2, February 1982

(7

----;:r- ,

qno /-to exp ( -EB)

(5)

qLv c

= --.

kT
For the interpretation ofthe Hall effect it was assumed 22 that
the carrier concentration taking part in the conductivity is
the total grain carrier concentration no, and the mobility is
activated and has the form /-t = /-toe - E,,/kT. We prefer to assume that conductivity is taking place by an activated carrier
.
. 0 f earners
.
concentratIOn
n = noe - E.lkT,and t h at scattenng
takes place only at the grain boundaries (i.e., the mean free
path is of the order of the grain size). Ifwe allow scattering at
the grain boundaries other than that due to the barrier itself,
/-to should be modified and we can write
I

-=-+-

(6)

/-t b /-to /-t s

where /-ts accounts for the additional scattering at the grain
boundaries.
When the mean free path in the grain is short compared
to the grain size, account should be taken of the scattering in
the grain. In the general case the total resistivity P has contributions from both thegrainsPG and their boundariesPB' We
then can write
P=PG +PB

q/-tGnO

q/-tbnO exp ( - EBlkT)

=--+

(7)

where /-tG is the grain mobility [in good quality grains this
might approach the single crystal value (-:::=.659 cm 2 /V s in
the case ofCdSef 3 ]. We can now define a total effective mobili ty /-t as,
I
I
-=-+

/-t

/-tG

/-tb exp ( - EBlkT)

(8)

For a thin film transistor with a semiconductor film

thickness t, a channel width wand a source-drain gap I, the
leakage current (measured at very low drain voltage) can be
written as

IL = qND/-tbwt (VDIl) exp (

~:B ).

(9)

where EB is given by Eq. (4) with nO-:::=.ND assuming a uniform distribution of donors which are all ionized, with the
traps full, and /-tG >/-tb'
Application of a positive gate voltage will cause a
change equivalent to adding donors, thereby influencing
both the barrier height and the source-drain current. 15 For
N D > N 1), the source-drain I D can be written as
Levinson et al.

1194

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VD

IV. RESULTS AND DISCUSSIONS

ID = WqPb -(NDLc +ffG)

q2~/'2.L
)
. Ie,
( 8kT(N L +ctr )
D c
G

Xexp-

(10)

where Lc is the thickness of the induced channel (~the field

penetration depth) and f f G is the gate-induced charge concentration per unit area. This neglects the relatively small
contribution to the total current from the part of the film in
which charge is not induced. When f f G = 0, the leakage
current is given by Eq. (9).
III. EXPERIMENT

Staggered inverted TFT structures were fabricated as

described previously,? using a photoengraving process. The
source-drain metallization was defined in Cr by a lift-off procedure and in Al by etching in warm H 3P0 4 ; in the latter
case the Al 20 3 gate dielectric ( - 1500 A), the CdSe semiconductor ( - 1000 A) and the source-drain metal ( - 500 A)
were all deposited in the same vacuum cycle. The fully fabricated structure was then either thermally annealed? in flowing nitrogen (- 375C for I h) or implanted 20 with 50 keY
Cr, 50 keY AI, or 15 keY B ions at doses in the range 5 X 10 '4
to 1 X 10 '6 ions cm -2. The projected ranges, estimated from
Winterbon's Tables 24 were 275 Afor Cr, 495 Afor Al and
370 A for B; the predicted distributions are broad, with a
width of the same order as the projected range. The temperature of the CdSe film during implantation was monitored in
a separate experiment by using a calibrated Ta-N resistor
with high negative TCR, fabricated immediately under the
CdSe layer. This showed that the bulk film temperature increased by a maximum of about 15C. 20 Most implanted
devices received no subsequent thermal annealing.
After annealing or implantation, the electrical characteristics of the devices were measured on a curve tracer (Tektronix 576).

ru
B

t:. Cr
o Al

o
I

...I

...I

c9
at>
,,

..
....'"'"
'"

tl

, I

"",

I
I

,Q
'/
P,

,
I

II

I
I

10-7

I I

I,

,'t:.

10-8

p
1
1

00

Dose,

q, (ions.cm- 2 )

FIG. 2. Dependence ofleakage current (I L) on ion implant dose.p, for TFT's

with channel dimensions 30 /lmX 1200 /lm. IL was measured for Va = 0.5
V.
1195

J. Appl. Phys., Vol. 53, No.2, February 1982

A. Ion implanted devices (unannealed)

For transistor structures implanted with Cr, AI, and B

ions, the leakage current increases very rapidly with dose, as
shown in Fig. 2. This steep rise in current, above the unimplanted value of - I nA, occurs at some threshold dose and
has also been observed in the saturated region with an applied gate voltage. 2o To describe these results in terms of the
grain boundary trapping model, we assume that the donor
density N D is proportional to the implant dose ifJ (ions cm- 2 )
i.e., ND = rJifJ It, where rJ is a constant effective doping efficiency and t is the semiconductor thickness. This assumes a
uniform donor distribution; alternatively, we may choose t
to be the projected range but this will have only a small effect
on the results, as shown below. According to the model, the
leakage current 1L' at a constant temperature and source-todrain voltage, for doses ifJ'>ifJ *, (where rJifJ * = N~) can be
written as
(
VD
IL = qPbW-rJifJ exp
I

where the slope of In

F=

q~~~t . I)
,

8rJkT

ifJ

(11)

(I;) versus lIifJ is

q2o./~t

and ED = F

8rJkT

kT

ifJ'

Figure 3 shows the data from Fig. 2 replotted as In(1L I ifJ ) vs

lIifJ. For Al and B implanted samples, the data is linear over
most of the range of doses, in good agreement with Eq. (11).
The Cr data shows a greater scatter at the highest doses
(small lIifJ ), but thisomay be due to a larger sputtering yield;
approximately 100 A of CdSe was eroded 2s after implantation with 10'6Cr+cm- 2 , whereas much less material was
lost when implanting with the same dose ofB or Al ions. For
B at low doses, N D may be small compared to N 1; and Eq.
(I I) will not apply; this would account for the departure
from linearity in Fig. 3. The slopes of the straight line fits in
Fig. 3 and the corresponding barrier heights as a function of
dose are given in Table I. For B, the barrier decreases from
0.20 eY at ifJ = 2 X to'Scm -2 to 0.04 eY at
if! = I X IO l6cm -2. For Al at if! = 5 X 1Q15cm -2, E8 = 0.02
eY, so that E8 < kT; therefore, the pre-exponential term in
Eq. (II) will dominate the behavior at and above this dose.
The grain boundary trap density can be calculated if the
doping efficiency rJ is known, and this can be deduced from
the gate voltage dependence of the drain current measured at
low drain voltage. For VG '> VD' application of a gate voltage
VG will induce a uniform carrier concentration per unit area
A/'

Cox VG
q

Jr G - - - - ,

where Cox is the oxide capacitance per unit area. This neglects any loss of charge to slow states at the oxide interface,
which effectively reduces Cox. If Lc is the characteristic penetration depth of the surface space charge, the drain current
from Eq. (10) is then
Levinson et al.

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or

In ( -ID) =In
IL

0.2 0.4

0.6 0.8

1.0 1.2

1015 x

1!cP

1.4 1.6

1.8

2 2.2

(cm 2 1

FIG. 3. Plot of (IL/t/J ) vs 1/.;6 for ion implanted TFT's with channel dimensions 30.umX I2oo.um. IL was measured for VD = 0.5 V.

0.6

0.5

...J

G/1J

Cox
+ F / )-VG'

(13)
q1J
where F = (q2vf~t )I(81JkT) is the slope of the leakage current presented in Fig. 3. Figure 4 is a plot ofln(IDI I L) as a
function of the gate voltage VG for a boron implanted dose of
1016cm - 2, which is sufficiently high for ,/J!GI1J< 1 to be
valid. This shows an excellent agreement ofthe experimental
results with Eq. (13). The slope of the straight line obtained is
[1 + F(l/ )]Co xiq1J, where F= 1.5 X 10 15cm- 2 is the
slope from Fig. 3, which describes the leakage current of the
boron implanted transistors. Using these two slopes enables
us to calculate 1J. We obtain 1JB = 1.3 X 10- 3 for the boron
implantation. Assuming f , is the same for all implants, the
ratio between the slopes of curves obtained with different
implants in Fig. 3 and that of boron gives the 1J values for the
other implants. For Al implantation, 1JAI -4.4x 10- 3 and
for Cr implantation, 1Jcr = 8.9 X 10- 4 Using the value obtained for 1J, we obtain [Eq. (11)] for the grain boundary trap
density of the ion implanted samples..#', = 1.6X 10 12cm- 2 .
The grain size in annealed CdSe TFT's is - 400 A10.11 and
- 250 A in unannealed films. 10 Since x-ray diffractometer
scans showed a small increase in grain size from the as-deposited value on implantation with Cr or AI,20 we will use an
average value of L = 300 A for implanted films and L = 400
Afor annealed films. For implanted films, the critical donor
density [Eq. (2)] isN~ - 5 X 10 17cm -3. Ifthe departure from
linearity at low doses in Fig. 3 for B occurs at
10 15 X l/ = 0.6, then N~ = 1J */t = 2.2X lO 17cm- 3 ,
which agrees well with the previous value.

From the absolute values of the leakage currents, the

mobility f..lb can be estimated using Eq. (7) over the range of
doses which give linear plots in Fig. 3. For B, f..lb = 5
cm 2/VsforAI,f..lb = 20 cm 2/Vsand forCrf..lb = 1~20
cm 2/V s. These values off..lb are considerably lower than the

0.4

t:::!

Ifwecan assume: (1) thatLJt-I and does not change with

gate voltage (for example, if the gate field penetrates all the
way through the semiconductor for all gate voltages used),
and (2) c/Y'G/1J< 1, the gate induced charge carrier concentration is small compared to the carrier concentration available at VG = 0, then
In (IDIIL)=(l

t
1J
q2JV2;t

+ - - - ------'---'--8kT1J (LJt) + (A/'GI1J )

OAl
[
[]
\ Cr

(Lc
fG)
-+-

0.3

0
t:!

J;
0.2

TABLE I. Slope F = q'. J

(unannealed) devices.

;t /87JkT and barrier height EB for implanted

0.1

EB(eV)

Implanted ion

F(cm- ')

I.S X 10'0

Cr

2.2x lO'n

AI

4.4X 10"

(for> in cm

-'I

0
0

FIG. 4. Plot ofIn(/,,/1,1 vs V" for a high dose (.;6 = 1O"'cm ') B implanted
TFT, with channel dimensions 30.um X 1200 .urn, CdSe thickness 1000 A,
AI,Oj thickness 1500 A; If) and I,. measured for V" = I V.
1196

J. Appl. Phys., Vol. 53, No.2, February 1982

3.9xlO'4
.;6
5.8 X 10 14
>

I.lx 10'4

t/J

Levinson et al.

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calculated value of f.La and the single crystal value of ~650

cm 2/V S,23 and probably reflect increased scattering in the
grain boundary due to radiation damage, i.e., f.Ls <!-La in Eq.
(6). We have assumed thatf.Lb is independent of dose (i.e., f.Ls
is constant under the conditions used here). However, iff.Lb is
dominated by scattering from ionized impurities or defects,
then f.L s a: 1/>, and this would remove the > dependence from
the pre-exponential term [Eq. (II)]. Since the exponential
term usually dominates the behavior, it is hard to distinguish
the true dependence of f.L b' In fact, plots of In{h ) vs 1/>
similar to those in Fig. 3 are also found to be linear over
approximately the same ranges of dose. Temperature-dependent measurements ofI L might give more information about
scattering mechanisms.
At sufficiently low doses, we may arrive at the situation
whereA'e>1]> It inEq.(12)andsinceL c - t [assumption
(I) above], the drain current should be described by:

( - q2o/r;t)
VD
ID = wqf.Lb -v;f/e exp
,
/

8cfle kT

where
or,
VD
( - q3J11;t )
ID = Wf.Lb Cox Ve exp
.
/
8ckTCox Ve

(14)

In Fig. 5 a plot ofln(IDIVG) vs 1/VG for an unannealed Al

device implanted with a low dose of 5 X 10 14 ions cm - 2 is
shown. The agreement of the points in Fig. 5 with Eq. (14) is
indeed good, indicating that the approximation is valid.
From the slope in Fig. 4, we estimate A', -2x lOn cm -I,
which is very close to the value of 1.6X 1012cm -2 deduced
for the ion implanted samples from the dose dependence of
I L' From the data in Fig. 5, we estimate f.Lb = 59 cm 2IV s,
which is higher than the value of 20 cm 2 IV s derived from
the dose dependence.

B. Thermally annealed transistors

With good operating transistors having a high switching ratio, the gate-induced carrier concentration should be
large compared to that contributed by the donors, or if we
again assume that the conducting channel forms through the
full thickness of the semiconductor, we have Ne>NDt. Under such conditions we can again use Eq. (I4) to describe the
drain current as a function of gate voltage.
Figure 6 is a plot of In(1DI Ve ) as a function of 11 Ve for
an unimplanted, (20 f.Lm gap between Cr source drain electrodes, annealed at 395 C for 1 h) transistor with VD = 0.5
V. All the points except for the one at the lowest gate voltage
(Ve = 2V), agree well with Eq. (14). With Ve = 2V, jY'e is
not large compared to N D t and VG is not large compared to
VD and therefore the approximations made are not valid.
From the slope of the straight line in Fig. 6 we deduce A/,
~5.9 X 10" cm- 2 which is 30% of that obtained for the
boron implanted transistors above. The mobility calculated
from the pre-exponential term is in this casef.Lb = 121
cm 2 /V s. This compares well with the saturated value of the
Hall mobility measured by Van Heek '3 (-IOOcm 2 /V s); this
1197

J. Appl. Phys . Vol. 53, No.2, February 1982

is consistent with our interpretation since for E B < k T,

f.L H ""-'f.L b' Assuming that the departure from linearity at low

Ve in Fig. 6 occurs when fl elt~N 1j and that

N 1j =-ff, I L, we can estimate .ff,. For L~400 A this gives
fl,,,,,-,2.6X lO 'l cm- 2 , in reasonable agreement with the value of fl, obtained from the slope.
Figure 7 shows a similar plot ofln{IDI Ve ) vs 1/ VG for a
thermally annealed TFT with Al SoD electrodes; this device
was annealed at 320 C for 1 h. From the slope we estimate
fl, - 7 X 10 11 cm - 2, which is very close to the value for the
thermally annealed device with Cr electrodes above. However, the mobility f.Lb -490 cm 2/V s is considerably higher and
much closer to that obtained in single crystals. In this case
scattering at the grain boundary appears to be much lower.
In other Al diffused TFT's, we have observed lower values of
f.Lb similar to those given for Cr SoD devices.
The effect of annealing the B implanted devices was also
investigated. Small pieces cut from each implanted substrate
were annealed at 250 C for 20 min, 270 C for 30 min, and
350 C for 30 min. At a given dose, the leakage current increased substantially with annealing temperature, for the
two lower temperatures, as shown in Fig. 8 where In(1L I is
plotted against 1/>; for comparison the results for as-implanted devices (from Fig. 3) are also shown. No significant
diffusion from the source-drain electrodes across the sourcedrain gap is expected to occur under these annealing conditions. The linear part of these plots becomes steeper and
moves to lower doses (higher 1/> ) with increasing anneal
temperature. (/LI decreases slightly at high doses for the
annealed samples [Fig. 8(b),(c)]; in this range I L still increases with dose for samples annealed at 270 C, but decreases above > = 6X IO l5 cm -2 for the samples annealed at
250 DC. Since the curves in Fig. 8 move to lower doses with
increasing annealing temperature, it appears that annealing
has increased the efficiency of producing donors (i.e., 1] has

-1.5

-2

-2.5

-3.5

-4
-4.5
0.05

0.055

0.06

0.065

0.07

l/VG (V-l)

FIG. 5. Plot ofln(If)IV,,) vs (liVe;) for unannealed Al implanted

(q, = 5 X 1O'4cm - ') TFT with channel dimensions 10 flm X 1200flm, CdSe
thickness 1000 A, AI,O, thickness 1500 A. If) measured for VI) = 0.15 V.
Levinson et al.

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CJ
>

2.0

!::!
c:

ex

1.5

0.5

O~L-L-~L-~~~~~~~~~~~

02

0.25

0.3

0.35

0.4

l/V

0.45

0.5

0.55

0.6

(y-l)

FIG. 6. Plot ofln(I a/V,,) vs(l/V(,"I for a TFT with Crsource-drain metallization which was thermally annealed at 395C for 60 min. The channel
dimensions are 20,um X 1200 ,urn, CdSe thickness 1000 Aand AI,O, thickness 1500 A, ID measured with V{) = 0.5 V.

(11) we might expect h 0:: 4; or I L /4; = constant, giving a fiat

part of the curve at the left hand side of Fig. 8. We must also
consider the effect of scattering in the grain, through Eq. (8).
At high doses,,uG may not be large compared to ,ub' and
ionized impurity scattering may dominate the conductivity
which would have a mobility,,u 0:: 1/4;; since the carrier concentration is also proportional to 4;, IL should then be independent of 4;. In fact the samples annealed at 350C for 30
min had leakage currents which decreased with increasing
dose; Figure 9 shows that in this case, I L 0:: 1/4; to a good
approximation. This indicates that the carrier concentration
does not change with 4;, and,u 0:: 1/4;. A fixed concentration
of active sites into which the implanted ions could move (for
sufficiently high annealing temperatures and/or times)
could give rise to such a saturation in the carrier
concentration.
These results are not well understood. Hall measurements as a function of implant dose and annealing temperature would provide useful information about the carrier concentration and mobility, and temperature dependent
measurements might also help to understand the scattering
mechanisms important in the high dose implanted samples.
C. TFT's fabricated by other groups

increased), or decreased c/V,. However, attempts to verify

this by determiningff, ,17, and,ub from the modulated transistor characteristics were inconclusive; the approximations
used earlier (i.e., that the gate induced charge is either very
large or very small compared to this donor density) did not
hold in most of the samples after annealing, making it difficult to interpret the data in Fig. 8. The departure from linearity at low 1/4; in Fig. 8 occurs when the barriers at the
grain boundaries are <kT, i.e., the exponential term in Eq.
(11) is approximately unity. The pre-exponential term will
then dominate the behavior of the leakage current. From Eq.

We will now compare these results with those from devices fabricated by other groups.
1. CdSe TFT's

Devices fabricated by mechanical masking in a single

pump-down were purchased from the Imperial College

a Unannealed

~.~~\

b Annealed 250C for

20 Minutes

, b\

c Annealed 270C for

30 Minutes

*-+c

+
2.0

\.

\,

1.5

C]

<C

1.0

\
\

c:

""

~
\.
\

0.5

--. -'--+<
----+

--

0.2

0.25

0.3

lNG (y-l)

FIG. 7. Plot ofln(Io/VcJ vs (l/VG ) for a TFTwith Al source-drain metallization which was thermally annealed at 320C for 60 min. Channel dimen
sions are30,um X 1200,um CdSe thickness 1000 A, AI,O, thickness 1500 A,
fa measured with VD = 0.5 V.
1198

J. Appl. Phys., Yol. 53, No.2, February 1982

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1015 x 1/ (cm 2 )

FIG. 8. Plot of (Ij<,6) vs l/<,6 for B ion implanted TFT's before and after
annealing. Channel dimensions 30,um X 1200 ,urn, II. measured for
Vo = 0.5 V. Curve A: unannealed; curve B: annealed at 250C for 20 min.;
curve C: annealed at 270C for 30 min.
Levinson et at.

1198

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500

400

300
l..?

>

...J

-17

200

"

C><

100
-18
X

0.5

0.3

0.1

1015 x 1/rJ> (cm 2 )

FIG. 9. Plot of IL vs l/tP of B implanted TFT's annealed at 350 'C for 30

min. Channel dimensions 30 fJm X 1200 fJm, IL measured for VD = 0.5 V.

group26 and had Cr S-D electrodes, CdSe semiconductor,

and Si0 2 dielectric layers. They were annealed at Imperial
College. From measurements made in our laboratory, a
similar plot ofln(IDIVG) vs 1/VG is obtained, as shown in
Fig. 10. Using film thicknesses indicated by the vendor, we
estimate~.1/"t ~4.3 X 10 1I cm- 2 , which is again similar to the
values determined above for our CdSe TFT's. The mobility
obtained f-Lb = 94 cm 2IV s is also similar to both the value
obtained for our Cr S-D annealed TFT's and to the saturated
value of f-L H measured by Van Heek. 13 There is a departure
from linearity at low VG in Fig. 10, similar to that observed

l..?

>

C
!:::!
~

2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-0.2
- 0.4

t.
0

0.2

0.3

0.4

0.5

FIG. 10. Plot ofln(ID/Va) YS II/Va) ofa TFT fabricated and annealed at
Imperial College. 26 This device had Cr source drain electrodes, CdSe thickness 1300 A, Si0 2 thickness 1200 A, ID measured with VD = I V.
1199

J. Appl. Phys., Vol. 53, No.2, February 1982

FIG. II. Replot of Fig. 4 of Ref. 27 as In(ID/VGI vs (I/VG)

in Fig. 5. Again, if we assume that this occurs when

~Glt~Nl:;, we deduce a value of A/"t~1.8X 10 11 cm- 2

compared with 4.3X 10 11 cm- 2 calculated from the slope.

The drain current!gate voltage characteristics of a double-gated TFT with a thin -100 A CdSe layer have recently
been reported. 27 Figure 11 shows this data plotted as
In(IDIVG) vs 1/VG. From the slope of the linear region
(VG > 10 V) we estimate a trap density of ~t
~2.7X 10 12cm- 2 At VG = 10 V, the induced charge concentration is ~G = 2.2X 10 12cm- 2, where the departure
from linearity begins, and this suggests that N 1:;
~2.2 X 10 18cm -3 since the film thickness is 100 A. Then
from Eq. (2) we estimate~t~2.2X 10 12 cm- 2 in good
agreement with the value obtained above from the slope in
Fig. 11. At VG = 0, we are well below N 1:; and the traps will
not be filled. The conductivity will therefore be very low [Eq.
(3)] and this accounts for the very low leakage currents
achieved in this device. From the absolute current, we estimatef-Lb ~63 cm 2/V s using Eq. (14); the quoted 27 field effect
mobility at VG = 20 V, f-LFE = 18.43 cm 2 /V s is lower than
f-Lb' as expected.
2. Poly-Si TFT's
There is considerable interest in making FET's from
poly-Si and Kamins and Pianetta4 recently described the
characteristics oflaser recrystallized poly-Si TFT's fabricated on quartz substrates. Again, if we assume the gate induced charge carrier concentration is large compared to the
donor concentration, and plot In(ID I VG) vs 1/ VG' a straight
line is obtained (Fig. 12) down to VG = 3 V. The gate oxide
Levinson et s/.

1199

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thickness in these devices was about 1050 A, and from the

slope in Fig. 12 we estimatefi, ~1.9 X 10 1I cm- 2 The mobility, estimated from the pre-exponential term, is,ub~165
cm 2 /V s, compared with a field effect mobility of 121
cm 2/V s. If the grain size is about 10 ,um4, then the critical
carrier concentration is 1.9X 10 14cm- 3 in the 5500 A polySi film; we will always be above N 1j even at very low gate
voltages ( > 0.1 V). This is consistent with no departure from
linearity at high values of l/VG in Fig. 12. Unlike CdSe,
where p-type conduction does not occur, the contribution
from holes in Si can be important. In this example, where the
contacts are doped n + , no significant leakage will occur if
the net (donor-acceptor) concentration is less than
-1.9 X 10 14cm -3; implanting this channel with ap-type dopant, as described by the authors,4 is usually sufficient to
ensure this condition. In CdSe TFT's, where the trap densities are higher and the grain size smaller, N 1j is much bigger
(- 2 X 1Ol7cm -3) and much higher donor densities can be
tolerated, while still maintaining very low leakage.
Since gate-induced carriers affect the conductivity in a
similar way to ionized donors, un doped polycrystalline semiconductors can also be used in TFT's, as has recently been
demonstrated by Depp et al. 2x These authors used un doped
poly-Si which was not laser annealed; nevertheless, the trap
density is still sufficiently low and the grain size large enough
that the critical carrier concentration (N 1j) can easily be induced by the applied gate voltage for voltages above a
threshold voltage of - 8 V. Lower threshold voltages will
result from doping the poly-Si andlor increasing the grain
size (e.g., by laser annealing), as has already been seen. For
these undoped poly-Si TFT's, experimental data of the drain
current as a function of gate voltage for low drain voltages,
together with a theoretical curve from numerical model calculations presented in Ref. 28 are reproduced in Fig. 13.
Depp et al. used .IV, ~8 X 10 ll cm -2 and,ub = 50 cmIIV s
as values of the parameters in their model. The full curve in
Fig. 13 was calculated from our model with A/',
~3.9X IO ll cm- 2 [deduced from the slope ofln(IDIVG) versus l/VG ] and,ub = 68.6 cm 2 /V s (deduced from the preexponential at VG = 10 V) and is in much better agreement
with the experimental data. If the calculated curve from Ref.
28 (dashed line in Fig. 13) is a "best fit" to the experimental
points, the agreement is not very good.

v. CONCLUSION
The results of applying the grain boundary trapping
model to the devices described above are summarized in Table II. CdSe TFT's with Cr SoD electrodes fabricated by two
independent groups and annealed in the usual way both have
similar trap densities (./V, ) and grain boundary mobilities
(,ub)' whereas the ion implanted (unannealed) and thinner
CdSe TFT's26 have significantly higher trap densities. Grain
boundary mobilities in the CdSe films are typically - 100
cm 2 IV s; much lower values of - 10 cm 2 IV s are obtained
from implanted (unannealed) films. For some thermally annealed devices with Al SoD electrodes, mobilities (,ub ~490
cm 2IV s) approaching those found in good single crystal
CdSe have been observed. The sharp increase in film conductivity occurs at a critical carrier concentration N1j, which in
1200

J. Appl. Phys., Vol. 53, No.2, February 1982

1.4
1.3
1.2
1.1
1.0
0.9
(!l

.?:

0
!:!
c:

C<

0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1

FIG. 12. Plot ofln(I DIV,;) vs (l/VG ) for the results reported in Ref. 4, Fig. 2,
for V{) = I V for a laser annealed polysilicon TFT.

12

11

10

I
I

.3- 6
.....0

I
I

I
I

I
I

I.

OL-__~__~__~Z-~__~__~__~__~~

10

12

14

16

VG (V)

FIG. 13. If) vs VG dots and dashed curve are the experimental points and
theoretical curve taken from Figs. 4 and 5 in Ref. 28. The full curve is
obtained by analyzing the experimental results according to our model.
Levinson et at.

1200

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TABLE II. Table of trap density If,). mobility 11th)' and critical donor density IN~) for ion implanted and thermally annealed CdSe TFr's. and poly-Si
TFr's. deduced from device characteristics. Also shown is the approximate grain size IL ). Figures in brackets are reference numbers.
N~(cm-3)

L(A)

4X JOI7

-350

1.6 X JOI2

10

4X JOI7

-350

CdSe
AI implanted

1.6 X JOI2
2x JO"

20
60

4X JOI7

-350

CdSe
Cr S-D. thermally
annealed

3-6X JO"

120

I X J017

400

CdSe
AI S-D. thermally
annealed

7x JO"

490

2X JO'7

400

2-4 X 10"

94

I X JOI7

400

2.7X 10'2

63

2X 10 ' "

100

Poly-Si'
laser annealed

1.9XIO"

165

Poly-Si d

3.9X 10"

2X 10 "
2XIO '7

Type of device

u,y",lcm- 2 )

CdSe
B implanted

J.6X JOI2

CdSe
Cr implanted

CdSe'
thermally annealed
CdSe"
thermally annealed
thin layer

fLb(cm 2V-'S-'j

68.6

10'_10'

400

'Reference 26.
bReference 27.
'Reference 4.
"Reference 28.

these devices includes both ionized donors and gate induced

charge. For all the CdSe devices with film thickness in the
range 850- - 1300 A, N"b is 1-2 X 10 17cm -3 but for the thin
-100 A films it is -2X 10 18 cm- 3 . At sufficiently high gate
voltages, when the induced carrier concentration is much
greater than N1>, the potential barriers at the grain boundaries become small (-kT) and the field effect mobility may
approach the value offib' In comparison, the device fabricated from laser annealed poly-Si has a much lower trap density
( - 1.9 X 10 II cm - 2) than the CdSe films, and since the grain
size is thought to be much bigger (- 10 fim) the value of N 1>
is much lower (- 2 X 10 14 cm -3). The mobility V-tb) is similar
in the laser annealed poly-Si on quartz and thermally annealed CdSe films at present.
In general, the degree of doping has a controlling effect
on the device behavior as is seen, for example, in the implanted transistors. The doping level, together with the parametersff" N1>,fib' and t allow the device behavior to be
calculated in a simple manner, as shown above. In CdSe
TFT's, which are always n-channel devices, N 1> is high, and
quite a high donor concentration can be introduced into the
film without causing high leakage currents. If the donor concentration is just below N 1>, applying a small positive gate
voltage will induce more carriers and a high switching ratio
will result. Very thin CdSe films have a higher trap density
and higher N 1>, but in this case, because the layer is so thin,
the volume concentration of gate induced charge can be very
high and for double-gated TFT's,27 this makes it possible to
maintain very low leakage by keeping the donor density well
below N1> and still have high switching ratios for moderately high gate voltage. In general, in most devices, the gate can
1201

J. Appl. Phys., Vol. 53, No.2, February 1982

potentially induce charge carrier concentrations many times

N"b so that no doping of the semiconductor layer is really
necessary. In practice, such charge must be supplied from
the source contact and the requirement to make a sufficiently ohmic contact may be achieved by thermal diffusion of the
contact metallization (which is usally an n-type dopant). The
donor density (ND) in the semiconductor relative to the critical concentration N "b will affect the threshold voltage. Thermal annealing also probably reduces ,/V, and increases the
grain size, both of which reduce N 1>. All of these factors
presumably result in the lack of modulation observed in fabricated unannealed structures previously reported. However, implantation in such structures results in conductivity
behavior characteristic of the polycrystalline film as described above. Since no implant mask was used, the contacts
were also implanted and must then be able to inject sufficient
current into the films.
The same kind of behavior is found in the laser annealed
polysilicon TFT,4 and in TFT's made from undoped poly-Si
without laser annealing2X; in both cases n + contacts were
fabricated for n channel devices, to ensure good ohmic contacts. However, since N"b is much lower in this case, the
channel is preferably doped p-type to ensure low leakage and
all of the electron concentration is induced by the gate.
In summary, the grain boundary trapping model has
been successfully applied to describe the variation in conductivity of thin film transistors as a function of carrier concentration. The charge carriers in CdSe TFT's can either be
provided by donors, induced by the gate, or a combination of
both. The modulated transistor characteristics, measured at
sufficiently low drain voltage, and the implant dose depenLevinson et al.

1201

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dence of the leakage current have been used to characterize a

number ofTFT's in terms of the grain boundary trap density, critical carrier concentration, mobility, and grain size.
The effect of these parameters on device performance has
been illustrated for various kinds of CdSe TFT's and for
TFT's fabricated from poly-Si. Despite its simplicity, the
model describes the behavior of the conductivity in polycrystalline TFT's remarkably well. The omission of other effects
such as trapping of carriers by slow states in the gate oxide,
may have introduced small numerical errors in the device
parameters deduced. However, with a better understanding
of these critical parameters and their impact on device behavior, the realization of cheap, large area TFT circuits fabricated on amorphous substrates may be one step nearer.

'T. P. Brody and P. Malmberg, Int. J. Hybrid Microelectron. 2, 2911979).

2E. W. Greenwich and P. C. Luo, in Proceedings of the 24th IEEEIESC
Conference, Washington, D. C.1I974).
'T. 1. Kamins, Solid State Electron. 15,78911972).
'T.1. Kamins and P. A. Pianetta, IEEE Electron Device Lett. 1, 21411980).
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Sci. Techno!' 17,485 (1980).
S. J. Ingrey, P. R. Shepherd, and W. D. Westwood, J. Vac. Sci. Techno!.
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1202

J. Appl. Phys., Vol. 53, No.2, February 1982

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11980).
"J. C. Anderson, in Active and Passive Thin Films, edited by T. J. Coults
IAcademic, New York. 1978).
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Weimer, J. Appl. Phys. 36, 16811965).
"c. A. Neugebauer, J. Appl. Phys. 39. 317711968).
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20p. R. Shepherd. P. J. Scanlon, W. D. Westwood, J. Levinson, and 1. V.
Mitchell, J. Vac. Sci. Technol. 18 lin press. 1981).
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22J. W. Orton and M. J. Powell. Rep. Prog. Phys. 43, 81 (1980).
21M. Neuberger, II- VI Semiconductor Data Tables, (Electronic Properties
Information Center, Hughes Aircraft Corp., Culver City, California,
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edited by M. Aven and J. S. Prener INorth Holland, Amsterdam, 1967).
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Plattner, J. Nuclear Instrum. and Methods 182/183,261 (1981).
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Levinson et a/.

1202

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