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CMOS Design

Chapter 6 : Low-Level Power

Optimization
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6. Low-level power optimization

C. Chen

Low-Level Power Optimization

Circuit and Logic Levels:

Combinational:
gate sizing, pin ordering, multiple threshold voltages,
network restructuring/logic optimization, technology
decomposition and mapping.

Sequential:
signal/state encoding, clock gating, precomputation
logic, glitch reduction.

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6. Low-level power optimization

C. Chen

Gate Sizing for Low Power

Gate sizing problem:
Given a cell library where there are some choices of
predefined gates (each type of gate with several transistor
sizes, delay and power), choose a set of gate sizes such that
power is minimized while design constraints are met.
Basic idea:
To drive a large load, a large gate is needed for acceptable
delay, which requires more power. To reduce power, the
gates that toggle with high frequency should be made
smaller. Since gates may have different area-power-delay
tradeoff curves and timing criticality, the optimization
problem could become very complicated.
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6. Low-level power optimization

C. Chen

Gate Sizing for Low Power

In most standard cell libraries, the gate delay can
be defined as
d i i ki w j / wi
jFO ( i )

where i and wi are the intrinsic delay and width

(size) of gate i, respectively, FO(i) is a set of gate is
fanout gates, and ki is a constant.
If gate i is downsized by wi, the power reduction
will be:
FI(i): gate is fanins
Pi wi ( i k )
kFI ( i )

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i : switching activity

6. Low-level power optimization

C. Chen

Gate Sizing for Low Power

If we neglect the delay change of gate is fanins,
the delay increase is given by
1
1
d i (
)ki w j
wi wi wi
Define a weight function:

gi = Pi / di

Intuitively, gates with high weight are better candidates for

gate sizing, unless downsizing it will violate timing
constraints. After downsizing a gate with maximum weight,
update the delay and power info, and repeat the process
until no further sizing is possible.
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6. Low-level power optimization

C. Chen

Pin Ordering for Low Power

Most logic gates have input pins that are
logically equivalent, but may have different circuit
characteristics. This means that pins can be ordered
for low power design.
Take a two-input NAND gate for example.
From low power point of view, the input with
more frequent transition should be connected to
the output.
The exact power savings depend on capacitance,
transistor size, and switching activity.
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6. Low-level power optimization

C. Chen

Multiple Threshold Voltages

delay

Vdd
(Vdd Vt ) 2

A good strategy:
For performance of critical parts, a low threshold
voltage is to be used. For the rest of the circuit, a
high threshold voltage is used for low power
consumption.
Note: A low threshold voltage results in a rapid
increase in subthreshold current !!
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6. Low-level power optimization

C. Chen

Network Restructuring
Network restructuring is the task of composing
different transistor networks that can implement
the same functionality.
In general, network restructuring requires an
automatic tool for large networks logic
synthesis. However, the designers can use local
restructuring rules to transform one network to
another. Some typical restructuring operations
are:
Decomposition, gate duplication, wire deletion,
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6. Low-level power optimization

C. Chen

State Encoding for Sequential Circuits

The logic designer can choose different encoding schemes
which may lead to different power, area and delay. Look at a
3-bit counting sequence based on binary code and Gray code
below.
Binary code
Sequence
# toggles
000
3
001
1
010
2
011
1
100
3
101
1
110
2
111
1
Total:
14
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Gray code
sequence
000
001
011
010
110
111
101
100

# toggles
1
1
1
1
1
1
1
1
8
C. Chen

6. Low-level power optimization

State Encoding for Sequential Circuits

A very important step in state machine synthesis is
to assign binary codes to represent the symbolic
states.
Two functionally-identical state machines with different encoding
0.1
11
0.3
00

0.4
0.1

0.1
01

State transition
probabilities

0.1
01
0.3
00

0.4
0.1

0.1
11

M1
M2
Expected state transitions: E[M1] = 2(0.3+0.4) +1(0.1+0.1) = 1.6
E[M2] = 1 (0.3 + 0.4 + 0.1) + 2 (0.1) = 1.0
more power efficient
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6. Low-level power optimization

C. Chen

Glitch Reduction
Glitch power estimation is computationally
expensive because it depends upon the timing
relationship between signals inside the circuit. In
general, a deeper circuit lead to higher glitch
power.
Adding buffers to enable path balancing can
reduce spurious transitions. Another way to reduce
glitches is to shorten the depth of combinational
logic by adding some pipeline registers.
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6. Low-level power optimization

C. Chen