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2014 5th IEEE PES Innovative Smart Grid Technologies Europe (ISGT Europe), October 12-15, Istanbul

Effects of Loss of Time Synchronization in Differential


Protection of Transformers Using Process Bus
According to IEC 61850-9-2
G. Igarashi

J. C. Santos

Escola Politcnica
Universidade de So Paulo
So Paulo, Brazil
gigarashi@usp.br

Escola Politcnica
Universidade de So Paulo
So Paulo, Brazil
josemir@pea.usp.br

Abstract Our aim is to show the results from a mathematical


simulation of the behavior of a differential protection algorithm
for power transformers compared with the loss of the time
synchronization signal in the process bus according to IEC
61850-9-2. Described herein are an original model for simulating
the samples in the process bus, a proposed algorithm for
differential protection of power transformers adapted for
protective relays operating with process bus according to
standard and response analysis of the protection algorithm from
this loss of sync.
Index Terms ethernet networks, IEC 61850-9 Standard,
instrument
transformers,
power
system
protection,
telecommunication network reliability.

I.

INTRODUCTION

The Substation Automation System (SAS), proposed by


IEC 61850 [1], organizes all the devices and data
communication networks present in a substation at different
levels and buses according to Fig. 1.

process a certain logic of protection, control and measurement.


These sampled and digitized values need to be synchronized
in time so that they can be properly used by the devices in the
process bus.
This article describes a study of how the sampled values
sent through the process bus to a differential protection relay
for power transformer can interfere with the operation of the
relay in a situation of loss of synchronization.
For this study, first an algorithm was developed to
simulate sequences of the sampled values generated. Each
sequence was subsequently applied to another algorithm that
simulates the operation of a transformer differential protection
function. After validating the sequence of values and the
differential protection algorithm, a simulation was made of the
drift variation of the internal clocks of IEDs responsible for
sending the values sampled in the bus process for evaluating
the effects of time synchronization loss in the operation of the
differential protection relay. The results are presented at the
end of this article. Suggestions on parameters to be followed
for a safer operation of the process bus in these circumstances
are also offered.
II.

Figure 1. Basic architecture of a SAS

The IEC 61850-9-2 establishes a standard for operating the


SAS process bus. According to this standard, the current value
measured by a Current Transformer (CT), present at process
level, is sampled and digitized by either a CT or a Merging
Unit (MU), which accounts for sending these samples via the
process bus to Intelligent Electronic Devices (IEDs), present at
the bay level, responsible for using this measured value to

SIMULATION OF SAMPLES IN PROCESS BUS

The IEC 61850-9-2 defines that the measured current in


the primary of a CT is transmitted in the bus through sampling
and digitizing the instantaneous value of this current in its
primary, according to predefined sampling rates (80
samples/cycle for protection, or 256 samples/cycle for
measurement purposes [2]). Sampling may be performed by
either the CT itself, or a MU connected to the secondary of a
CT. Then each sample, or several sequential samples, are
inserted into a network message and sent in multicast format
through the process bus devices connected to this bus. This
message is called Sample Value Message (SV Message), and
is part of the SV Services provided by IEC 61850.
Each sample must be synchronized in time so that it can be
used properly by the IEDs. Historically, there has been an

978-1-4799-7720-8/14/$31.00 2014 IEEE

evolution in the methods used to ensure time synchronization


between IEDs. In its first edition in April 2004, IEC 61850-92 did not exactly define the process of time synchronization
adopted. In July the same year, document IEC 61850-9-2LE
[2] proposed the installation of a separate distribution network
for timing signal, or 1pps format, or IRIG-B format. The new
IEC 61869-9 [3], which is in its final stages of preparation,
will propose the use of the Precision Time Protocol (PTP)
defined by the IEEE 1588v2 [4] standard, originally
developed for generic timing equipment via Ethernet, and
undergoing some adjustments needed for applications in SAS
[5]. Through message exchange, which works together with a
specific hardware present in the IED network interface, the
PTP is able to offer a precision time synchronization between
two devices with error in the order of sub-microseconds [6].
The representation of the moment at which the sample was
taken is made by a sample counter (SmpCnt), whose value is
incremented at each sample taken and inserted into the SV
Message. At each transition of a new second, this counter is
reset, as shown in Fig. 2.

TABLE I.
sample
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

i(t)
t=0s=1s=2s
0.000000
54.119610
100.000000
130.656296
141.421356
130.656293
100.000000
54.119610
0.000000
-54.119610
-100.000000
-130.656296
-141.421356
-130.656293
-100.000000
-54.119610

SIMULATION RESULTS
t=0s
0.000000
54.119610
100.000000
130.656296
141.421356
130.656293
100.000000
54.119610
0.000000
-54.119610
-100.000000
-130.656296
-141.421356
-130.656293
-100.000000
-54.119610

ir(t)
t=1s
0.888571
54.940498
100.627901
130.995015
141.418537
130.311519
99.364970
53.290408
-0.897456
-54.948685
-100.634145
-130.998363
-141.418480
-130.308066
-99.358647
-53.282177

t=2s
1.777106
55.758190
101.250259
131.327286
141.410134
129.963722
98.730729
52.466285
-1.785991
-55.766356
-101.256463
-131.330582
-141.410022
-129.960218
-98.724367
-52.458033

Analyzing the results, in an IED with sync signal, in each


new second, the first 16 samples are observed to have the
same value. In turn, in an IED without sync, the samples
undergo a slight change, which seems similar to the effect of a
sinusoidal signal whose delay gradually rises over time,
although the measured signal at the input of the CT does not
show this variation in lag.
III.

ALGORITHM FOR PERCENTAGE TRANSFORMER


DIFFERENTIAL PROTECTION

The operating principles of the differential protection


function for power transformers are well documented [7].
Basically, this consists of the measurement and analysis of the
difference between the normalized current of the primary and
the secondary of a transformer as shown in Fig. 3.
Figure 2. Sample Value signal example

According to IEC 61850-9-2, in a scenario where a loss of


sync signal occurs, the transmission of SV does not cease,
letting each IED of the process level use its own internal clock
as a time base for controlling sampling instants and SmpCnt
counter. As most IEDs use microprocessor digital technology,
such internal clocks are usually electronic, based on the
oscillation frequency of the crystal oscillator. In a scenario
where the error is 20ppm (value equivalent to the accuracy of
quartz watches found in the market), every second the time at
which the sample is performed by an IED suffers an error of
20s. That is, the ideal sampled value i(t), without any
synchronization error, and the real sampled value ir(t), with
synchronization error, can be expressed by (1) and (2):

Table 1 shows an example of the results for the first 16


values sampled at the beginning of each new second, from
simulations of an IED with sync signal and an IED without
sync signal, both measuring the same current. For this
simulation, a primary current Ip equal to 100 2A and the zero
crossing at time t = 0s, the grid frequency equal to 50Hz, the
lag zero, the sampling rate of 16 samples/cycle and the drift
error Df of +20 ppm were admitted.

Figure 3. Differential power transformer protection in the event of an


external fault (a) and an internal fault (b)

If a fault occurs outside the protection zone (Fig. 3a) the


currents measured by the CT primary (Ip) will rise in
proportion to the currents measured by the CT secondary (Is),
making their differences close to zero. In another situation
where a fault occurs inside the protection zone (Fig. 3b), there
will be reasonable differences between these currents, which
sensitize the differential protection.
Before the measured currents can be compared effectively,
they need to be normalized, offsetting the following aspects:
transformation ratio of the power transformer;
configurations of primary and secondary windings of
power transformer (e.g. delta, grounded wye,
ungrounded star, etc.);
difference between the transformation ratios of CTs
(TAP compensation);

connection configuration of CTs (e.g. delta or star,


towards the center of the star, etc.).
In protection systems using relays with digital technology,
all these compensations and obtaining module and phase of
currents Ip and Is are implemented through internal
mathematical algorithms of relay [8]-[15]. Fig. 4 illustrates an
example of architecture used in digital protection relays.

Figure 4. Example of architecture for digital differential protection of


power transformers

In this example, the CT reduces the Ip1 current to Ip2


current that is later applied to digital differential protection
relay. The first block, called COND, conditions and protects
other relay circuits against surges. The second block, called
LPF, acts as a low pass filter anti-aliasing, necessary for the
correct functioning of the algorithms of digital filters. The
next block, called MUX, functions as a multiplexer circuit,
which switches the various signals measured to a single digital
analog converter circuit, the ADC block. Finally, the digitized
value is sent to the uP block, normally a microprocessor,
capable of performing all the digital logic and algorithms
required for the operation of the relay.
At this stage, the microprocessor begins executing a
sequence of algorithms at each new sample received, as shown
in Fig. 5.

In the first block of Fig. 5, called DFT, modules and


phases of the primary current phasor (Ia1, Ib1 and Ic1) and
secondary current phasor (Ia2, Ib2 and Ic2) of the power
transformer are obtained via digital filters based on the
Discrete Fourier Transform, according (3) to (7):

The result is a phasor for each phase, as shown in example


(7) for the current Ia1 (A-phase primary current of the
protected transformer).
Subsequently, phasors modules are compensated in TAP
block in order to standardize them based on the power of
transformer to be protected and the ratios used in each CT
according (8) to primary winding, and (9) to secondary
winding. The term MVA refers to protected transformer power
(in MVA), KV1 and KV2 terms refer, respectively, to the
voltages of primary and secondary (in KV), and CTR1 and
CTR2 terms refer, respectively, to the CTs ratios used in the
primary and secondary.

The correction is made by dividing the current phasor


obtained by DFT for the corresponding TAP, as shown in
example (10), for current Ia1tp (Ia1 with TAP1
compensation).

Figure 5. Flowchart depicting the sequence of algorithms executed on the


microprocessor

A common system topology can be used to describe the


operation of these algorithms, as illustrated in Fig. 6.

Figure 6. Example system for differential protection of three-phase


transformers

Then, in the CONEC block, phasors already normalized


are multiplied by compensation matrices to offset the
connection configuration of primary and secondary windings
of the power transformer. In the example of Fig. 6, the
connection is DY1; therefore, the matrices used by the
CONEC block are expressed by (11) and (12):

With compensated currents, the last step is to establish the


operate/restrain plan for each phase of the power transformer,
as shown in Fig. 7.

This plan is based on two currents: the differential current


(Idiff), which corresponds to the module of vector sum of the
primary and secondary currents of each phase and the restrain
current (Ibias), which is the sum of the modules of the primary
and secondary currents of each phase, according (13) and (14),
to the differential phase unit A.
Figure 8. Example of architecture for digital differential protection of
transformers using digital process bus

These two currents eventually define a working point in


the operate/restrain plan. If this point is inside the operation
zone the relay trips. If inside the restrain zone, it does not trip.

Figure 7. Operate/restrain plan for differential transformer protection

The restrain zone and operate zone are separated by AB,


BC and CD segments, defined from lines 1, 2 and 3. Each
segment has a specific goal [13] [16], changing the
operate/restrain behavior of the differential unit according to
errors generated by the dynamics of the system being
protected. The goal of segment AB is to prevent the relay from
operating mainly due to sources of constant error, which do
not directly depend on the intensity of the transformer currents
(e.g. magnetizing currents of power transformer). This
segment is set on line 1, which is parallel to the axis Ibias and
intersects the Idiff axis at minimum differential current (Id).
The goal of the BC segment, also called slope 1, is to prevent
the relay from operating mainly due to sources of proportional
error, whose values depend directly on the intensity of the
current of transformer (e.g. TAP switch of power transformer,
CT accuracy, relay accuracy). It is defined on line 2, which
crosses the Ibias axis at point S1 and has slope . The CD
segment, also called slope 2, has the same goals of slope 1,
besides improving the performance of the relay in extreme
situations in which the saturation of the CTs occurs (e.g. high
short circuit currents, superimposed exponential component).
It is defined on line 3, which crosses the Ibias axis at point S2
and has slope . The slopes inclinations are expressed as a
percentage and defined according to (15).

With the implementation of the digital process bus, this


architecture undergoes some changes. Sampling and
digitalization of the current signals are to be performed in
secondary converters of CTs, or in MUs, as shown in Fig. 8.
Subsequently, the digitized values are sent to the process bus
in a SV Message through a network interface, represented by
the NET block.

This SV Message is received by the differential relay


through a network interface, represented by the NET block,
which extracts the sampled value and sends it to the uP block
to execute its algorithms. The IEC 61850-9-2LE establishes
the rate of 80 samples/cycle for protection. In practice, this
rate is high and unnecessary, since most differential protection
relays achieve excellent performances in their protection
algorithms with lower sampling rates (for example, 16 or 24
samples/cycle). Fig. 9 is the flowchart of the proposed
simulation algorithm. In this diagram, the BUF block was
inserted to memorize the last 80 samples received by the NET
block and to send them to the DFT block at every 5 samples
received. This procedure aims to match the frequency
implemented in the DFT block of Digital Differential
Protection Relay with the same periodicity of conventional
digital relays, without compromising the sampling rate used
by ADC and LPF blocks of the Merging Unit. The other
blocks follow the same principles discussed in the diagram of
Fig. 5.

Figure 9. Diagram representing the simulated algorithm

Other models of proposed algorithms [17] [18] at this


point, instead of the BUF block, added a resampling block
based on interpolation algorithms which generates a new
sequence of sampled values. These values are sent to the DFT
block at a sampling rate equal to the one at which the
protection algorithm originally operates. It is worth observing
that the application of resampling the signal must take into
account the configuration of the LPF block for the correct
functioning of the DFT block.
The validation of this algorithm was based on the power
system shown in Fig. 10.

Figure 10. Proposed system for the simulation of the differential algorithm

Fig. 11 shows a typical parameterization scheme of the


operate/restrain plan adopted for the differential protection
unit of phase A.

Figure 11. Operate/restrain plan with the simulation results (white points)

Table 2 shows some results from the application of various


current values. Each phasor generated a series of sampled
values based on (1). The series of values were applied to the
algorithm represented by Fig. 9. All faults were simulated on
the secondary side of the transformer to be protected. Points A
and B represent failures that occurred outside the protection
zone and which generated projections inside the restrain zone.
Points C and D represent failures that occurred inside the
protection zone and that generated projections inside the
operate zone.
TABLE II.
Point

Fault

L1-L2-L3
external fault

L1-L2
external fault

L1-L2-L3
internal fault

L1-L2
internal fault

IV.

RESULTS OF SIMULATIONS
Currents (A)
IA1 = 418.40 30o
IB1 = 418.40 -90o
IC1 = 418.40 150o
IA2 = 4184.00 0o
IB2 = 4184.00 -120o
IC2 = 4184.00 +120o
IA1 = 483.10 0o
IB1 = 241.60 180o
IC1 = 241.60 180o
IA2 = 4184.00 0o
IB2 = 4184.00 180o
IC2 = 0.00 0o
IA1 = 418.40 30o
IB1 = 418.40 -90o
IC1 = 418.40 150o
IA2 = 0.00 0o
IB2 = 0.00 -120o
IC2 = 0.00 +120o
IA1 = 483.10 0o
IB1 = 241.60 180o
IC1 = 241.60 180o
IA2 = 0.00 0o
IB2 = 0.00 0o
IC2 = 0.00 0o

Idiff and Ibias (TAP)

with the CTs present in the secondary. To study some of the


effects that could cause loss of synchronization in the
operation of the differential algorithm, samples generated by
(2) were applied to the transformer differential protection
algorithm represented by Fig. 9. The simulations were
performed on the basis proposed by Fig. 10 and the
parameterization of the differential unit according to Fig. 11.
In the first case, a charging current was applied according
to the rated power of the transformer, with a frequency of
60Hz, drift of +20ppm for CTs in the primary and drift of 20ppm for CTs in the secondary. Table 3 shows the results for
the differential unit of phase A. The Ibias current was kept
constant at 2.000 multiples of TAP and the Idiff current
gradually increased over time (average of 0.015 multiple of
TAP per second). For the differential units of phases B and C,
the same values were observed.
TABLE III.

SIMULATION RESULTS FOR FREQUENCY OF 60HZ

Currents (A)
IA1 = 83.70
IB1 = 83.70
IC1 = 83.70
IA2 = 837.00
IB2 = 837.00
IC2 = 837.00

30o
-90o
150o
0o
-120o
+120o

time (s)
0
1
2
3
4
5
33.5

Idiff (TAP)
0.000
0.015
0.030
0.046
0.061
0.076
0.500

Ibias (TAP)
2.000
2.000
2.000
2.000
2.000
2.000
2.000

Following this trend, it can be assumed that, in the


operate/restrain plan of the differential unit, the unit will enter
the operate zone when crossing slope 1 for a current Idiff close
to 0.500 multiples of TAP, which will occur approximately
33.5 seconds after the time at which there was a loss of time
synchronization signal, as shown in line B of Fig. 12.

IdiffA = 0.00
IbiasA = 10.00

IdiffA = 0.00
IbiasA = 11.55

IdiffA = 5.00
IbiasA = 5.00

IdiffA = 5.77
IbiasA = 2.89

BEHAVIOR OF THE DIFFERENTIAL PROTECTION

CONSIDERING LOSS OF SYNCHRONISM IN PROCESS BUS

According to IEC 61850, in a situation in which IED


accounts for sending the SV Message pass to operate without
its time synchronization signal via the network, it must
continue to send the samples to the process bus, to be used as
a time reference in its internal clock. In the case of a
differential protection of power transformer, this implies that
CTs present in the primary would then operate asynchronously

Figure 12. Effects of loss of time synchronization in the operate/restrain plan

In the second case, simulation was run in a situation


similar to the first case, this time assuming that the power
system operates at a frequency of 50Hz. Table 4 shows the
results for the differential unit of phase A.
TABLE IV.

SIMULATION RESULTS FOR FREQUENCY OF 50HZ

Currents (A)
IA1 = 83.70
IB1 = 83.70
IC1 = 83.70
IA2 = 837.00
IB2 = 837.00
IC2 = 837.00

30o
-90o
150o
0o
-120o
+120o

time (s)
0
1
2
3
4
5
40

Idiff (TAP)
0.000
0.013
0.025
0.038
0.051
0.063
0.500

Ibias (TAP)
2.000
2.000
2.000
2.000
2.000
2.000
2.000

The simulation results show that the Ibias current


remained constant at 2.000 multiples of TAP and the Idiff
current showed a lower trend (around 0.013 multiples of TAP

per second). Keeping this trend, the differential unit enters the
operate zone after the Idiff reaches slope 1 in 0.500 multiples
of TAP, which will occur about 40 seconds after the loss of
the synchronization signal, as shown in line B of Fig. 12.
In the latter case, the simulation was also run in a situation
similar to that of the first case, assuming this time that the
power transformer is operating at half its rated output. Table 5
shows the results for the differential unit of phase A.
TABLE V.

SIMULATION RESULTS FOR HALF OF RATED LOAD CURRENT


AND FREQUENCY OF 60HZ

Currents (A)
IA1 = 83.70
IB1 = 83.70
IC1 = 83.70
IA2 = 837.00
IB2 = 837.00
IC2 = 837.00

30o
-90o
150o
0o
-120o
+120o

time (s)
0
1
2
3
4
5
40

Idiff (TAP)
0.000
0.008
0.015
0.023
0.030
0.038
0.300

Ibias (TAP)
1.000
1.000
1.000
1.000
1.000
1.000
1.000

In this case, the behavior of the Idiff current kept its


gradual and steady rise, now 0.008 multiples of TAP per
second. The Ibias current remained constant over time, with
half the previous value. Following this behavior, the
differential unit will enter the operate zone when the current
exceeds the minimum differential of 0.300 multiple of TAP,
which should occur about 40 seconds after the moment the
synchronization signal reception has stopped, as shown in line
A of Fig. 12.
Some fault currents with CT saturation were applied.
Responses of algorithm were similar to that exposed in [13],
presenting a curve shape (example of Point E in Fig. 11).
Differential protection did not trip because fault evolution was
restrained by slope 2.
V. CONCLUSIONS AND COMMENTS
The algorithms proposed for samples simulation and
differential protection unit showed satisfactory results and
enabled to analyze the effects caused by the loss of
synchronization signal in both the samples sent by the CT with
IEC 61850-9 interface and the relays for differential protection
of power transformers.
The loss of time synchronization signal interferes only
with the Idiff current calculated by the differential protection
unit causing the relay to act after a certain time without the
synchronization signal. The frequency of the power system,
the working power of the power transformer and the ppm
specification of IEDs internal clocks directly interfere with the
action of the differential unit in a situation of loss of time
synchronization.
In CTs with non-conventional technologies in their project
(e.g. optical Faraday Effect or Rogowski coil), no CT
saturation occurs. Therefore, depending on the situation, slope
2 of the differential protection unit would become

unnecessary, simplifying the operate/restrain plan. In contrast,


the use of the process bus according to IEC 61850-9-2 added
one more factor to existing errors that should be taken into
account for calculating the parameters that will define the
operate/restrain plan.
The behavior that the SAS shall provide in a situation of
loss of synchronization signal is not defined by the IEC61850
standard, leaving it to the IEDs developers and SAS
integrators to take an appropriate action. One of the ways to
treat this problem is making the IED wait a certain time for the
return of the synchronization signal [17]. If this time is
exceeded, the IED signals to other devices that are operating
without synchronization signal. For this situation, we suggest
that the protection relay could, for example, block its
differential protection unit (which depends on the phase
information of currents) and activate rear protections based on
overcurrent units (which do not depend on the phase
information of currents).
This study is expected to contribute to improving the
criteria used in the parameterization of waiting times of
devices, as well as assisting in the specification of safe drift
values to the IEDs used in SAS projects.
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