CMOS Subcircuits

Allen and Holberg - CMOS Analog Circuit Design
Page V.0-1
V. CMOS SUBCIRCUITS
Contents
V.1
V.2
V.3
V.4
V.5
V.6
MOS Switch
MOS Diode
MOS Current Source/Sinks
Current Mirrors/Amplifiers
Reference Circuits
V.5-1 Power Supply Dependence
V.5-2 Temperature Dependence
Summary
Organization
Chapter 10
D/A and A/D
Converters
Chapter 11
Analog Systems
SYSTEMS
Chapter 7
CMOS
Comparators
Chapter 8
Simple CMOS
Opamps
Chapter 9
High Performance
Opamps
COMPLEX
CIRCUITS
Chapter 5
CMOS
Subcircuits
Chapter 6
CMOS
Amplifiers
SIMPLE
Chapter 2
CMOS
Technology
DEVICES
Chapter 3
CMOS Device
Modeling
Chapter 4
Device
Characterization
Page V.0-2
WHAT IS A SUBCIRCUIT?
A subcircuit is a circuit which consists of one or more transistors and
generally perfoms only one function.
A subcircuit is generally not used by itself but in conjunction with other
subcircuits.
Example
Design hierarchy of analog circuits illustrated by an op amp.
Operational
Amplifier
Complex Circuits
Simple Circuits
Biasing
Circuits
Current
Source
Current
Mirror
Input Differential Amplifier
Current
Sink
Diff.
Amp.
Mirror
Load
Second Gain
Stage
Inverter
Output
Stage
Current Source Current

Sink
Sink
Load Follower Load
Page V.1-1
V.1 - MOS SWITCH

SWITCH PROPERTIES
Ideal Switch
RAB(on) = 0
RAB(off) =
Nonideal Switch
CAB
IOFF
ROFF
VOFF
RON
B
CAC
C
+
RA
VControl
CBC
RB
Page V.1-2
MOS TRANSISTOR AS A SWITCH

Symbol
Bulk
A
(S/D)
(D/S)
C (G)
On Characteristics of A MOS Switch

Assume operation in active region (vDS < vGS - V T) and vDS small.
CoxW
v D S
CoxW
iD =
(v
- V T ) - 2 v DS
(vGS - VT) vDS
GS
L
L
Thus,
vDS
1
= CoxW
RON i
D
(v G S - V T )
L
OFF Characteristics of A MOS Switch
If vGS < VT, then iD = I OFF = 0 when vDS 0V.
If vDS > 0, then
1
1
ROFF i = I
DS
OFF
Page V.1-3
MOS SWITCH VOLTAGE RANGES

Assume the MOS switch connects to circuits and the analog signal can vary
from 0 to 5V. What are the voltages required at the terminals of the MOS switch
to make it work properly?
Bulk
(0 to 5V)
Circuit
1
(0 to 5V)
(S/D)
(D/S)
Circuit
2
The bulk voltage must be less than or equal to zero to insure that the
bulk-source and bulk-drain are reverse biased.
The gate voltage must be greater than 5 + VT in order to turn the switch
on.
Therefore,
VBulk 0V
V G 5 + VT
(Remember that the larger the value of VSB , the larger VT)
Page V.1-4
I-V CHARACTERISTICS OF THE MOS SWITCH

SPICE ON Characteristics of the MOS Switch
100A
V1 =10V
V1
V1=9V
Id
60A
V1 =8V
V1 =7V
V2
-5
20A
Id
V1=2V
-20A
V1=3V
V1=4V
-60A
V1 =5V
V1 =6V
-100A
-1V
-0.6V
-0.2V
0.2V
V2
SPICE Input File:

MOS Switch On Characteristics
M1 1 2 0 3 MNMOS W=3U L=3U
.MODEL MNMOS NMOS VTO=0.75, KP=25U,
+LAMBDA=0.01, GAMMA=0.8 PHI=0.6
V2 1 0 DC 0.0
V1 2 0 DC 0.0
V3 3 0 DC -5.0
.DC V2 -1 1 0.1 V1 2 10 1
.PRINT DC ID(M1)
.PROBE
.END
0.6V
1V
Page V.1-5
MOS SWITCH ON RESISTANCE AS A FUNCTION OF VGS

SPICE ON Resistance of the MOS Switch
100k
MOS Switch On Resistance
W/L = 3m/3m
10k
W/L = 15m/3m
W/L = 30m/3m
1k
W/L = 150m/3m
100
1.0V
1.5V
2.0V
2.5V
3.0V
3.5V
Gate-Source Voltage
4.0V
4.5V
5.0V
SPICE Input File:

MOS Switch On Resistance as a f(W/L)
M1 1 2 0 0 MNMOS W=3U L=3U
M2 1 2 0 0 MNMOS W=15U L=3U
M3 1 2 0 0 MNMOS W=30U L=3U
M4 1 2 0 0 MNMOS W=150U L=3U
.MODEL MNMOS NMOS VTO=0.75, KP=25U, LAMBDA=0.01, GAMMA=0.8
PHI=0.6
VDS 1 0 DC 0.001V
VGS 2 0 DC 0.0
.DC VGS 1 5 0.1
.PRINT DC ID(M1) ID(M2) ID(M3) ID(M4)
.PROBE
.END
Page V.1-6
INFLUENCE OF SWITCH IMPERFECTIONS ON

PERFORMANCE
Finite ON Resistance
Non-zero charging and discharging rate.
1
RON
+
VIN
-
VSS
C1
+
vC1
C1
VIN
-
vC1
Finite OFF Current

1
C2
+
vIN
-
VSS
CHold
+
vOUT
-
+
VSS
vOUT
-
Page V.1-7
EXAMPLES
1.
What is the on resistance of an enhancement MOS switch if VS = 0V, VG =

10V, W/L = 1, VTO = 1V, and K' = 25A/V2?
Assume that vDS 0V. Therefore,
vDS
L
L/W
RON
=
=
iD
CoxW(v GS-VT) K'(VG-V S -V T)
RON =
106
25(10-1) = 4444
VG
2.
If V G=10V at t=0, what is the W/L

value necessary to discharge C1 to
with 5% of its intial charge at
t=0.1S? Assume K'=25A/V2
and V TO = 1V.
C2=10pF
+
5V
+
- C1=20pF
v(t) = 5exp(-t/RC)
10-7
10-7
= 20 RC =
exp
RC
ln(20)
10
Therefore, R = 6 x 103
Thus,
10x103
L/W
L/W
=
=
6
K'(VG-V S-V T) (2.5x10-5)(9)
W
Gives L = 2.67
Page V.1-8
INFLUENCE OF PARASITIC CAPACITANCES

MOSFET Model for Charge Feedthrough Analysis
Distributed Model
G
CGDO
CGSO
S
CGC=Cox
RCH
Simplified Distributed Model

G
CGDO
D
Cox
2
Cox
2
CGSO
S
RCH
CGSO = Voltage independent (1st-order), gate-source, overlap cap.

CGDO = Voltage independent (1st order), drain-source overlap cap.
CGC = Gate-to-channel capacitance (C ox)
RCH = Distributed drain-to-source channel resistance
Page V.1-9
Charge Injection Sensitivity to Gate Signal Rate

Model:
vG
dvG
dt
vIN
CHold
-
Case 1 - Slow Fall Time:

Gate is inverted as vG goes negative .
Channel time constant small enough so that the charge on CHold is absorbed
by vIN.
When gate voltage reaches vIN+VT, the device turns off and feedthru occurs
via the overlap capacitance.
Case 2 - Fast Fall Time:
Gate is inverted as vG goes negative.
Fall rate is faster than the channel time constant so that feedthru occurs via
the channel capacitance onto CHold which is not absorbed by v IN.
Feedthru continues when vG reaches vIN+VT.
Total feedthru consists of that due to both the channel capacitance and the
overlap capacitances.
Other Considerations:
Source resistance effects the amount of charge shared between the drain and
the source.
The maximum gate voltage before negative transition effects the amount of
charge injected.
Page V.1-10
Intuition about Fast and Slow Regimes

To develop some intuition about the fast and slow cases, it is useful to model the
gave voltage as a piecewise constant waveform (a quantized waveform) and
consider the charge flow at each transition as illustrated below. In this figure, the
range of voltage at CL illustrated represent the period while the transistor is on.
In both cases, the quantized voltage step is the same, but the time between steps is
different. The voltage accross CL is observed to be an exponential whose time
constant is due to the channel resistance and channel capacitance and does not
change from fast case to slow case.
vCL
V
vGATE
Voltage
Time
(d)
Voltage
Time
(e)
Figure 4.1-10 (a) Illustration of slow ramp and (b) fast ramp using a quantized voltage
ramp to illustrate the effects due to the time constant of the channel resistance and capacitance.
Page V.1-11
Illustration of Parasitic Capacitances

1
CGS
+
CGD
VSS
VIN CBS
-
CBD
C1
vC1
CGS and CGD result in clock feedthrough

CBS and CBD cause loading on the desired capacitances
Clock Feedthrough
Assume slow fall and rise times
1
1
Switch ON
Switch OFF
1
CGS
+
VIN
-
Clock signal couples through CGD on the

rising part of signal when switch is off, but
VIN charges C1 to the right value regardless.
VSS
CBS
Clock signal couples through

CGD on the falling part of the
signal when the switch is off.
CGD
C1
vC1
CGD
CGD
CGD
vC1 = -C +C 1 - C 1 = - C (v in + VT)
1 GD
1
1
EXAMPLE regime)
Switched
Capacitor
Page V.1-12
Integrator
(slow
clock
edge
1
Switch ON
Switch OFF
vIN+VT
2
Switch ON
Switch OFF
VT
T
M1
M2
+
VIN
-
assuming:
C2
VSS
C1
VSS
vOUT
-
CGS1=CGS2=CGD1=CGD2 = CG
Net feedthrough on C1 at t2:

CG
(VIN + VT)
CG+C1
CG
CG
VC1 = VIN 1
V T
C1+CG
CG+C1
V C1 =
At t3, additional charge has been added due to CGS overlap of M2 as 2

goes positive. Note that M2 has not turned on yet.
CG
V C1 (t2-t3) = C +C VT
G 1
Page V.1-13
Giving at the end of t3 (before M2 turns on):
CG
VC1 = VIN 1C +C
1 G
+
Once M2 turns on (at t3 ), all of the charge on C1 is transferred to C2.
CG
C1
C1
VO = VC1 = V IN 1
C1+CG
C2
C2
+
Between times at t3 and t4 additional charge is transferred to C1 from the
channel capacitance of M2.
V O
Cch
(Vclk V T)
C2
(t3-t4)=
The final change in Vout is:

CG
C1
Cch
V O = V IN 1

(Vclk V T)
C2 C1+CG
C2
C1
so the error due to charge
C2
Ideally the output voltage change is VIN

feedthrough is:
C1 CG
Cch
V O (error) = VIN

(Vclk V T)
C2 C1+CG
C2
Page V.1-14
Rigorous Quantitative Analysis of Fast and Slow Regimes

1
Cch
CGS0
CL
VS
CGD0
Rch
+
vCL
-
VS
(a)
CL
+
vCL
-
(b)
1
Cch
Cch
CGS0
CGD0
Rch
VS
CL
+
vCL
-
(c)
Consider the gate voltage traversing from VH to VL (e.g., 5.0 volts to 0.0 volts,
respectively) described in the time domain as
v G = V H Ut
(3)
When operating in the slow regime defined by the relationship

2
V HT
2CL >> U
(4)
where VHT is defined as

V HT = V H V S V T
(5)
the error (the difference between the desired voltage V S and the actual voltage,
VCL) due to charge injection can be described as
W CGD0
V error =
CL
C c h
2
Page V.1-15
U CL W C G D 0
+
(V S + V T V L )
2
CL
(6)
In the fast swithing regime defined by the relationship

2
V HT
2CL << U
(7)
the error voltage is given in Eq. (8) below as
WCGD0 + C ch
2
V error =
V H T
CL
V HT WCGD0
6U C + C
(V S + V T V L )
L
L
3
(8)
The following example illustrates the application of the charge-feedthrough

model given by Eqs. (3) through (8).
Example 4.1-1 Calculation of charge feedthrough error
Calculate the effect of charge feedthrough on the circuit shown in Fig. 4.1-9 where Vs = 1.0 volts,
CL = 200 fF, W/L = 0.8m/0.8m, and VG is given for two cases illustrated below. Use model
parameters from Tables 3.1-2 and 3.2-1. Neglect L and W effects.
Case 2
vG
Case 1
0
0.2 ns
10 ns
Time
Case 1:
The first step is to determine the value of U in the expression
vG = VH - Ut
For a transition from 5 volts to 0 volts in 0.2 ns, U = 25 109
In order to determine operating regime, the following relationship must be tested.
Page V.1-16
2
2
VHT
VHT
2CL >> U for slow or 2CL << U for fast
Observin g that there is a backbias on the transistor switch effecting VT, VHT is
VHT = VH - VS - VT = 5 - 1 - 0.887 = 3.113
giving
2
VHT
11010-6 3.1132
= 2.66 109 << 25 109 thus fast regime.
2CL =
2 200f
Applying Eq. (8) for the fast regime yields
1.5810-15
17610-18 +
3.3210-3 17610-18
2
Verror =
(5 + 0.887 - 0)
3.113
+
20010-15
3010-3 20010-15
Verror = 19.7 mV
Case 2:
The first step is to determine the value of U in the expression
v G = VH - Ut
For a transition from 5 volts to 0 volts in 10 ns, U = 5 108 thus indicating the slow regime
according to the following test
2.66 109 >> 5 108
1.5810-15
17610-18 +
2
Verror =
20010-15
Verror = 10.95 mV
31410-6 17610-18
+
(5 + 0.887 - 0 )
22010-6 20010-15
Page V.1-17
POSSIBLE SOLUTIONS TO CLOCK FEEDTHROUGH

1.) Dummy transistor (MD)
W1
L1
WD = W1
LD 2L1
M1
MD
VSS
VSS
Complete cancellation is difficult.

Requires a complementary clock.
2.) Limit the clock swing when one terminal of the switch is at a defined
potential.
vG
0V
C
+
vin > 0
-
vout
VSS
vG
3VT
2VT
VT
t
ON
OFF
ON
Page V.1-18
CMOS SWITCHES
"Transmission Gate"
VSS
VDD
Advantages 1.) Larger dynamic range.

2.) Lower ON resistance.
3.) Feedthrough somewhat diminished.
Disadvantages 1.) Requires complementary clock.
2.) Requires more area.
Page V.1-19
DYNAMIC RANGE LIMITATIONS OF SWITCHES

Must have sufficient vGS to give a sufficiently low on resistance
Example:
VDD
50
2
B
VDD
+
VAB
1 A
50
2
Switch On Resistance
3k
2.5k
VDD = 4V
2k
VDD = 4.5V
VDD = 5V
1.5k
1k
0.5k
0k
0V
1V
2V
VAB
3V
4V
5V
SPICE File:
Simulation of the resistance of a CMOS transmission switch
M1 1 3 2 0 MNMOS L=2U W=50U
M2 1 0 2 3 MPMOS L=2U W=50U
.MODEL MNMOS NMOS VTO=0.75, KP=25U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5
.MODEL MPMOS PMOS VTO=-0.75, KP=10U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5
VDD 3 0
VAB 1 0
IA 2 0 DC 1U
.DC VAB 0 5 0.02 VDD 4 5 0.5
.PRINT DC V(1,2)
.END
Page V.1-20
Brooklyn Bridge Effect

If N-channel and P-channel devices are resistively scaled (i.e., sized to have the
same conductance at equivalent terminal conditions) the resistance versus voltage
(common mode) will appear as shown below.
Nch on; Pch on
Nch on
Pch off
Pch on
Nch off
280
270
5v
260
Id
250
5v
240
V
230
220
0.1
210
0
Page V.1-21
VOLTAGE DOUBLER USE TO PROVIDE GATE OVERDRIVE

Example
VDD
A
M1
CPump
M6
M4
M2
M7
M8
VDBL
CHold
M3
M5
VSS
A
B
Operation:
1. A low, B high - C Pump is charged to VDD-VSS.
2. A high, B low - CPump transfers negative charge to CHold
VDBL -0.5V DD - V S S
3. Eventually, VDBL approaches the voltage of -VDD + VSS. If
VDD = - VSS, then VDBL - 2VDD.
Page V.1-22
SUMMARY OF MOS SWITCHES

Symmetrical switching characteristics
High OFF resistance
Moderate ON resistance (OK for most applications)
Clock feedthrough is proportional to size of switch (W) and inversely
proportional to switching capacitors.
Complementary switches help increase dynamic range.
As power supply reduces, switches become more difficult to fully turn
on.
Switches contribute a kT/C noise which folds back into the baseband.
Page V.3-1
V.2 - DIODES AND ACTIVE RESISTORS

MOS ACTIVE RESISTORS
Realizations
+
When the drain is connected to the

gate, the transistor is always saturated.
vDS v GS - VT
v D - vS v G - vS - VT
vDG -V T where V T > 0

Large Signal
I-V Characteristics i
AC
DC
K'W
i = iD = (
) [ vGS - VT ]2
2L
= 2 ( vGS - VT ) 2 , ignore
or
v
v = vDS = vGS = VT +
Small signal
i
G
D
+
v
gm v
rds
v
If VBS = 0 , then ROUT = i
If V BS 0?
Note:
gmbs vbs
1
1
= g +g
g
M
DS
M
Generally, gm 10 gmbs 100 gds
(2iD ,)
Page V.3-2
VOLTAGE DIVISION USING ACTIVE RESISTORS

Objective : Derive a voltage Vout from VSS and VDD
VDD
M2
Vout
M1
VSS
Equating iD1 to iD2 results in :
vDS1 =
2
1 v DS2 - V T 2 + VT1
where
vGS1 = vDS1
and
v GS2 = vDS2
Example :
If VDD = -VSS = 5 volts, Vout = 1 volt, and ID1 = ID2 = 50 amps,
then use the model parameters of Table 3.1-2 to find W/L ratios.
iD1 = ( vGS - VT ) 2
2
1 = 4.0 A/V2
2 = 11.1 A/V2
K'n = 17 A/V2
K'p = 8 A/V2
1
then ( W/L )1 = 4.25
and ( W/L )2 = 1.34
Page V.3-3
EXTENDED DYNAMIC RANGE OF ACTIVE RESISTORS

Concept:
I
VC
+
I1
M1
+
vDS
I
I2
M2
+
VC
-
Consider :
Assume both devices are non-saturated
2
v DS
I1 = 1 (v DS + V C - V T )v DS 2
2
v DS
I2 = 2 (V C - V T )v DS - 2
2
2
v DS
v DS
I = I1 + I2 = v D S 2 + (V C - V T )v D S - 2 + (V C - V T )v D S - 2
I = 2(VC - VT)vDS
1
R = 2(V - V )
C
T
Page V.3-4
Implementation :
VDD
+
V
- C
M3A
M2A
M1
+
VGS
G- i
M3B
+
VGS
S
-
M2
vDS +
R
VSS
S
M2B
Page V.3-5
NMOS Parallel Transistor Realization :

+
i1
VC
+
G1
D1
+
D2
i2
i
G2 +
M1
VSS
S1
M2
r ac
VC
-
S2
_
Voltage-Current Characteristic :
2mA
Vc=7V
6V
5V
I(VSENSE)
1mA
4V
W=15u
L=3u
VBS=-5.0V
3V
0
-1mA
-2mA
-2
-1
VDS
NMOS parallel transistor realization

M1 2 1 0 5 MNMOS W=15U L=3U
M2 2 4 0 5 MNMOS W=15U L=3U
.MODEL MNMOS NMOS VTO=0.75, KP=25U, LAMBDA=0.01, GAMMA=0.8
PHI=0.6
VC 1 2
E1 4 0 1 2 1.0
VSENSE 10 2 DC 0
VDS 10 0
VSS 5 0 DC -5
.DC VDS -2.0 2.0 .2 VC 3 7 1
.PRINT DC I(VSENSE)
.PROBE
.END
Page V.3-6
P-Channel Extended Range Active Resistor Circuit

vAB
iAB
V DD
M2B
M2A
+
VC
-
M1A
+
VC
M1B
M3A
+ V
C
M3B
V SS
Voltage Current Characteristics
100uA
4V
5V
60uA
3V
20uA
Vc=2V
i AB
- 20uA
- 60uA
- 100uA
-4
-3
-2
-1
0
1
VAB
P-Channel Extended Range Active Resistor

M1A 3 4 5 10 MPMOS W=3U L=3U
M1B 3 6 5 10 MPMOS W=3U L=3U
M2A 10 3 4 4 MNMOS W=3U L=3U
M2B 10 5 6 6 MNMOS W=3U L=3U
M3A 4 7 0 0 MNMOS W=3U L=3U
M3B 6 7 0 0 MNMOS W=3U L=3U
VSENSE 1 3 DC 0V
VC 7 0
VAB 1 5
VDD 10 0 DC 5V
.MODEL MNMOS NMOS VTO=0.75, KP=25U
+ LAMBDA=0.01, GAMMA=0.8 PHI=0.6
.MODEL MPMOS PMOS VTO=-0.75 KP=8U
+LAMBDA=0.02 GAMMA=0.4 PHI=0.6
.DC VAB -4.0 4.0 0.2 VC 2 5 1
.PRINT DC I(VSENSE)
.PROBE
.END
Page V.3-7
THE SINGLE MOSFET DIFFERENTIAL RESISTOR

VC
i1
i1
v1
v2
v2
- v1
i2
v1
- v1
v2
v2
+
-
i2
VC
Assume the MOSFET's are in the active region

1
i1 = (V C - v 2 -V T )(v 1 - v 2 ) - 2 (v 1 - v 2 ) 2
i2 = (V C - v 2 -V T )(-v 1 - v 2 ) - (-v 1 - v 2 ) 2
2
Rewrite as
1
i1 = (V C - v 2 -V T )(v 1 - v 2 ) - (v 1 2 - 2v 1 v 2 + v 2 2 )
2
i2 = (V C - v 2 -V T )(-v 1 - v 2 ) - (v 1 2 + 2v 1 v 2 + v 2 2 )
2
i1 - i2 = (V C -v 2 -V T )(2v 1 ) - (v12-2v1v2+v22-v12-2v1v2-v22)
2
i1 - i 2 = 2 [ (VC - VT)v1 - 2v1v2 + 2v1v2 ]

2R =
v1-(-v1) 2v1
2v1
1
=
=
=
i1-i2 2(VC-VT)v1 (VC-VT)
i1-i2
or
R=
v1 V C - V T
1
W
2K L (VC-VT)
Page V.3-8
Single-MOSFET, Differential Resistor Realization

VC
r ac/2
i1
i1
v2
v1
v2
v1
VCC
r ac/2
- v1
v2
i2
- v1
v2
i2
VC
Voltage-Current Characteristics
1.0mA
VC= 7V
6V
0.6mA
5V
4V
0.2mA
ID(M1)
3V
- 0.2mA
- 0.6mA
- 1.0mA
-2
-1
V1
Single MOSFET Differential Resistor Realization
M1 1 2 3 4 MNMOS1 W=15U L=3U
M2 5 2 3 4 MNMOS1 W=15U L=3U
VC 2 0
VCC 4 0 DC -5V
V1 1 0
E1 5 0 1 0 -1
.MODEL MNMOS1 NMOS VTO=0.75 KP=25U
.DC V1 -2.0 2.0 0.2 VC 3 7 1
.PRINT DC ID(M1)
.PROBE
.END
Page V.3-9
The Double MOSFET Differential Resistor

VC1
i1
v1
iD2 iD1
i1
v1
v2
VC2
i2
v
iD3
iD4
v2
VC1
i2
iD1 = (V C1 -v-V T )(v1 -v) - 2(v1-v)2
iD2 = (V C2 -v-V T )(v1 -v) - (v1-v)2

2
iD3 = (V C1 -v-V T )(v2 -v) - (v2-v)2

2
iD4 = (V C2 -v-V T )(v2 -v) - (v2-v)2

2
1
1
i1=iD1+iD3=(VC1-v-VT)(v1-v)- (v1-v)2+(VC2-v-VT)(v2-v)- (v2-v)2

2
2
1
1
i2=iD2+iD4=(VC2-v-VT)(v1-v)- (v1-v)2+(VC1-v-VT)(v2-V)- (v2-v)2

2
2
i1 - i 2 = [(VC1-v-VT)(v 1-v) + (VC2-v-VT)(v 2-v)

- (V C2-v-VT)(v1- v) - (VC1-v-VT)(v2-v)]
= [v1(VC1-VC2) + v 2(VC2-VC1)] = (VC1-VC2)(v1-v2)
v1-v2
v1-v2
1
=
=
i1-i2
(VC1-VC2)(v1-v2)
KW
(VC1-VC2)
L
1
v1 ,v 2 min [(V C1-VT),(VC2-VT)]
R i n = KW
(VC1-VC2)
L
Rin =
or
Page V.3-10
Double-MOSFET, Differential Resistor Realization

VC1
iD1
i1
M1
v3
v1
i1
iD2
r ac/2
v1
VSS
v3
M2
r ac/2
v2
VC2
v4
i2
iD3
M3
iD4
VSS
v2
i2
M4
v4
VC1
Voltage-Current Characteristics
150uA
VC2 = 6V
5V
100uA
VBC =-5V
V3 =0V
VC1 =7V
50uA
I(VSENSE)
Double MOSFET Differential Resistor Realization

M1 1 2 3 4 MNMOS1 W=3U L=3U
M2 1 5 8 4 MNMOS1 W=3U L=3U
M3 6 5 3 4 MNMOS1 W=3U L=3U
M4 6 2 8 4 MNMOS1 W=3U L=3U
VSENSE 3 8 DC 0
VC1 2 0 DC 7V
VC2 5 0
VSS 4 0 DC -5V
V12 1 6
.DC V12 -3 3 0.2 VC2 2 6 1
.PRINT DC I(VSENSE))
.PROBE
.END
4V
3V
2V
- 50uA
- 100uA
- 150uA
-3
-2
-1
V1-V2
Page V.3-11
SUMMARY OF ACTIVE RESISTOR REALIZATIONS
AC Resistance
Realization
Linearity
How
Controlled
Restrictions
Single MOSFET
Poor
V GS or W/L
vBULK < Min (vS, v D)
Parallel MOSFET
Good
VC or W/L
v (VC - VT)
Single-MOSFET,
differential resistor
Good
VC or W/L
Double-MOSFET, Very Good VC1 - V C2 or

W/L
differential resistor
|v1| < VC - VT
vBULK < -v1
Differential around v1
v1, v2 < min(VC1-VT,
VC2-VT)
vBULK < min(v1,v2)
Transresistance only
Page V.3-1
V.3 - CURRENT SINKS & SOURCES

CHARACTERIZATION OF SOURCES & SINKS
1). Minimum voltage (vMIN) across sink or source for which the
current is no longer constant.
2). Output resistance which is a measure of the "flatness" of the
current sink or source.
CMOS Current Sinks & Sources
VDD
VG = V GG
iD
iD
VGG
+
v
vMIN
iD
VDD
VG = V GG
VGG
iD
+
v
1
rOUT = I
D
vMIN = vDS(SAT.) v
vMIN
VDD
0
where V = vGS - VT
Page V.3-2
NMOS1mA
Slope = 1/Ro
VGS = 3.73V
0.75mA
iO
+
vO
iO 0.5mA
+
0.25mA
VMIN
0mA
0V
2V
4V
vO
6V
vGS
-
8V
10V
Page V.3-3
SMALL SIGNAL MODEL FOR THE MOSFET
D
G
B
S
gm =
gmbs =
2K'WID
L
gm
2 2 F + |V BS |
1
1
r ds g = I
ds
D
G
+
B
+
vgs
vbs
gmvgs
gmbsvbs
rds
Page V.3-4
INCREASING THE ROUT OF A CURRENT SOURCE

MOS
Circuit
Small-Signal Model
i OUT
+
iout +
M2
r ds2
gm2 vgs2
vOUT
+
-
r
VGG
gmbs2 vbs2
+
v S2
-
Loop equation:
vout = [iout - (g m2vgs2 + gmbs2vbs2)]r ds2 + iout r
But, v gs2 = -vs2 and vbs2 = - vs2.
vout = [iout + gm2vs2 + gmbs2vs2]rds2 + iout r
Replace vs2 by i outrvout = iout [ rds2 + gm2 rds2r + gmbs2rds2r + r ]
Therefore,
rout = rds2 + r [1 + gm2 rds2 + gmbs2rds2]
MOS Small Signal Simplifications
Normally,
g m 10g mbs 100g d s
Continuing
rout rgm2 rds2
r out r x (voltage gain of M2 from source to drain)
vout
-
Page V.3-5
CASCODE CURRENT SINK

MOS
Small-Signal Model
Circuit
iOUT
IREF
iout
+
M2
M4
+
vOUT
gmbs2vbs2
M3 M1
r ds2
gm2vgs2
vout
+
vS2
-
r ds1
gm1vgs1
vout = [iout - (g m2vgs2 + g mbs2vbs2)]rds2 + ioutrds1

vout = iout[rds2 + gm2rds2r(1 + 2) + rds1]
rout = rds2 + r[1 + g m2rds2(1 + 2)] r ds1gm2rds2(1 + 2)
Note : v MIN = VT + 2VON 0.75 + 1.5 = 2.25 (assuming V ON VT)
NMOS Cascode1mA
Slope = 1/R o
iO
0.75mA
+
+
vGS2
-
iO 0.5mA
0.25mA
0mA
0V
VMIN
2V
4V
vO
6V
vO
+
vGS1
- 8V
10V
Page V.3-6
Gate-Source Matching Principle

iD2
+
iD1
iD2
+
M1
-
vGS1
vGS2
vGS2
M2
iD1
S = W/L
M2
vGS1
M1
-
Assume that M1 and M2 are matched but may not have the same W/L ratios.
1). If vGS1 = vGS2, then iD1 = (S1/S2)iD2
a). v GS1 may be physically connected together , or
b). v GS1 may be equal to vGS2 by some other means.
2). If i D1 = iD2, then
a). vGS1 = VT +
S2/S1(vGS2 - VT) , or
b). If S1 = S2 and VS1 V S2 then

vGS1 = vGS2
Page V.3-7
Reduction of VMIN or VOUT (sat)

High-Swing Cascode
Method 1 for Reducing the Value of vOUT(sat)
IREF
IOUT
IOUT
2V T+2V
M4
M3
+
VT+V
-
VOUT(sat)
M2
VOUT
M1
+
VT+V
+
VT+V
-
VOUT
VT + 2V
Standard Cascode Sink :
vGS = VON + VT =
Part of v G S
to achieve
drain current
Part of v G S to
enhance the channel
vDS(sat) = v GS - V T = (VON + VT) - VT = VON

iD
ID
VT
VT+VON
Above is based on the Gate-Source matching principle.
vGS
Page V.3-8
Circuit Which Reduces the Value of Vout(sat) of the Cascode Current Sink
iREF
iREF
M6
M4
1/4
+
-
+
1/1
VT + 2VON
iOUT
M2
2VT + 3VON
vOUT
VT + VON
+
1/1
1/1
VT + VON
M3
M5
iout
VT + 2VON
M1
+
VON
1/1
VT + VON
1/1
iD
vOUT(sat)
W=1
L 1
W =1
L 4
VT + VON
VT + 2VON
ID
2V ON
vOUT
K'W
K'W
iD = 2
(vGS - VT) 2 = 2
(VON) 2
L
L
vGS
VT
Page V.3-9
Method 2 for Reducing VMIN for MOS Cascode Sink/Source
iREF
iREF
iO
1
M5
M4
+
1/4
M1
VT + VON
M2
+
1
+
VON
VT + VON
Assume (W/L)1 = (W/L)2 = (W/L)4 = 4(W/L)5 values are identical and ignore
bulk effects.
Let I
= IO
REF
VGS1 =
2I REF
+ VT = VON + VT
W1
K L
1
and
V GS5 =
2I REF
+ VT
W5
K L
5
Since (W/L)1 = 4(W/L)5
V GS5 =
2I REF
+ VT = 2
W1
K 4L
1
2I REF
W1
K L
1
+ V T = 2 VON + VT
Page V.3-10
Since V GS3 = VGS4 = VON +VT

VDS1 = V DS2 = V ON
which gives a minimum output voltage while keeping all devices in saturation of
v M I N = 2 VO N
Output Plot:
1000A
ID(M4)
750A
500A
250A
0A
0V
1V
2V
3V
VOUT
4V
5V
Page V.3-11
Matching Improved by Adding M3

iREF
iREF
VT
+ M3 1
+
-
M4
+
V T + VON
1/4
M1
VON
M5
iO
V T + 2VON
VT + V ON
M2
V ON
+
1
V T + V ON
+
-
What is the purpose of M3?

The presence of M3 forces the VDS1 = VDS2 which is necessary to guarantee that
M1 and M2 act alike (e.g., both will have the same VT).
Page V.3-12
CMOS REGULATED CASCODE CURRENT SOURCE

Circuit Diagram
VDD
VDD
iOUT
I B2
R B2
M3
iD3
+
v GS3
IB1
M4
VBat
+ -
M1
v OUT
Iout
M2
-
VDS3(min) V DS3(sat)
v DS3
Principle of operation:
As v OUT decreases, M3 will enter the active region and iOUT will
begin to decrease. However, this causes a decrease in the gate-source
voltage of M4 which causes an increase in the gate voltage of M3. The
result is that even though M3 enters the active region, the series feedback
of M3 causes iOUT to remain constant.
Result:
The minimum value of vOUT is determined by the gate-source
voltage of M4.
vOUT(min) =
2IB2
K'(W/L) + VT4
Use a floating voltage, VBat, to reduce to VON
Page V.3-13
CMOS REGULATED CASCODE CURRENT SOURCE - CONT.

Small Signal Model
r ds3
iout
+ vgs3 +
RB2
r ds4
gm4vgs4
vgs4
gm3vgs3
r ds2
vout
-
(Ignore bulk effects)
iout = gm3vgs3 + g ds3(vout - v gs4)

vgs4 = ioutrds2
vgs3 = vg3 - vs3 = -gm4(rds4||RB2)v gs4 - vgs4
= -rds2[1 + gm4(r ds4||RB2)]iout
iout = -gm3rds2 [1 + gm4(rds4 ||RB2)]iout + g ds3 vout - gds3 rds2 iout
Solving for vout,

vout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(r ds4||RB2)]iout
vout
rout = i
= rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(r ds4||RB2)]
out
g m 2r3
r out = r ds3 g m3 r ds2 g m4 (r ds4 ||R B2 ) =
2
Example
K' N = 25A/V2, = 0.01, IB1 = IB2 = 100A, all transistors with
minimum geometry (W = 3m, L=3m), and RB2 = rds, we get
rds = 1M and gm = 70.7mho
rout (1M)(70.7mho)((1M)(70.7mho)(1M||1M)= 2.5G!!!
Page V.3-14
CMOS REGULATED CASCODE CURRENT SOURCE - CONT.

SPICE Simulation
160A
IB1=150A
140A
120A
IB1=125A
100A
IB1=100A
iOUT 80A
IB1=75A
60A
40A
IB1=50A
20A
0A
0
vOUT
SPICE Input File
CMOS Regulated Cascode Current Sink
VDD 6 0 DC 5.0
IB1 6 4 DC 25U
VOUT 1 0 DC 5.0
M1 4 4 0 0 MNMOS1 W=15U L=3U
M2 3 4 0 0 MNMOS1 W=15U L=3U
M3 1 2 3 0 MNMOS1 W=30U L=3U
M4 2 3 0 0 MNMOS1 W=15U L=3U
M5 5 4 0 0 MNMOS1 W=15U L=3U
M6 5 5 6 6 MPMOS1 W=15U L=3U
M7 2 5 6 6 MPMOS1 W=6U L=3U
.MODEL MPMOS1 PMOS VTO=-0.75 KP=8U
.DC VOUT 5 0 0.1 IB1 50U 150U 25U
.OP
.PRINT DC ID(M3)
.PROBE
.END
Page V.3-15
SUMMARY OF CURRENT SINKS/SOURCES
Current Sink/Source
Simple
Cascode
High-Swing Cascode
Regulated Cascode
rOUT
Minimum Voltage
rd s
VON
gm2 rds2rds1
gm2 rds2rds1
VT + 2 VON
gm 2rds3
VT + 2 VON
2 V ON
Page V.4-1
V.4 - CURRENT MIRRORS/AMPLIFIERS

What Is A Current Mirror/Amplifier ?
Rout
R in
CURRENT
iI
iO
MIRROR/
+
vI
Ideally,
iO = A I iI
Rin 0
+
vO
AMPLIFIER
Rout
Graphical Characterization
iI
iO
slope = 1/Rin
slope = 1/Rout
II
IO
vI
vMIN
INPUT
vO
vMIN
OUTPUT
iO
AI
1
iI
TRANSFER
Page V.4-2
CURRENT MIRROR AND CURRENT AMPLIFIERS

Sources of Errors
iI
CURRENT
iI
iO
MIRROR/
AMPLIFIER
+
vDS1 M1
-
In general,
iO
W2L1 v GS - V T 2 2
iI = W1L2v GS - V T 1
iO
1+vDS2 o2Cox2
1+vDS1 o1Cox1
If the devices are matched,

iO
W2L1 1+vDS2
=
iI
W1L2 1+vDS1
If vDS1 = vDS2,
W 2L 1
iO
iI = W1L2
Therefore the sources of error are:
1). v DS1 vDS2
2). M1 and M2 not matched ( and VT)
+
vGS
-
M2
vDS2
-
Page V.4-3
Simple Current Mirror With 0
DS1
M2
+
vGS
-
+
v DS2
-
( 1 + v
M1
v SS
Ratio Error
vDS1
-
10
= 0.02
8
1 + v DS2
iO
iI
+
- 1)x100%
Circuit -
= 0.015
6
4
= 0.01
2
0
0V
1V
2V
3V
VDS1-VDS2
4V
Ratio error (%) versus drain voltage difference Used to measure iO

1+ v D S 2 S1
=

iI
1+ v D S 1 S2
If S 1 = S 2, v DS2 = 10V, vDS1 = 1V, and i O/iI = 1.501, then
iO
1+10
=
1.501
=
iI
1+
0.5
---> = 8.5 = 0.059
5V
Page V.4-4
Matching Accuracy of MOS Current Mirrors

Neglect effects
iD1
iD2
+
M1
Define:
vGS1
vGS2
M2
(vDS2 > vGS2 - VT1)
= 2 - 1
iO = iD2 = 2(vGS2-VT2)2
iI iD1 1(vGS1-VT1)2
and
VT = V T2 - V T1 and
1 + 2
2
VT1+VT2
VT =
2
=
VT
+
,
V
=
V
2
T1
T
2
2
2
VT
and V T2 = V T + 2
1 = -
Thus,
V T2

+ v GS - vT
iO
2
2
V T 2
iI =
- v GS - v T +
2
T
1-2(vV-V
GS T)
VT

1 1+
2 2(vGS-VT)
1 +
2
VT
VT 2
iO
iI 1+ 2 1+ 2 1-2(vGS-VT)1-2(vGS-VT)
2VT
iO
iI 1 + - (v GS - V T ) ,
VT

5% , (v
= 10%
GS - V T )
iO
iI 1 0.05 - ( 0.2) = 1 0.15

= 1 0.025 if and VT are correlated
Page V.4-5
Matching Accuracy - Continued
RATIO ERROR (
iO - 1)100%
iI
Illustration
7
6
II = 1uA
5
4
3
II = 5uA
II = 10uA
1
II = 50uA
1
VT(mV)
10
Page V.4-6
Layout Techniques to Remove Layout Error

Layout without correction technique iI
iO
iI
M1
iO
M2
M2
V SS
VSS
Layou
t with correction technique iI
iO
iI
M1
M2
a
M2
b
M2
c
M2
d
M2
e
M1
iO
M2
a
M2
b
VSS
VSS
M2
c
M2
d
M2
e
Page V.4-7
Practical Current Mirrors/Amplifiers

Simple mirror
Cascode current mirror
Wilson current mirror
Simple Current Mirror iI = 60uA
60uA
Current mirrors and amplifiers

M1 1 1 0 0 MNMOS1 W=3U L=3U
M2 3 1 0 0 MNMOS1 W=3U L=3U
IIN 0 1
VOUT 3 0
.DC VOUT 0 5 0.1
+IIN 0 60U 10U
.PRINT DC ID(M2)
.PROBE
.END
iI = 50uA
iI = 40uA
40uA
iI = 30uA
iOUT
iI = 20uA
20uA
iI = 10uA
0
0
vOUT
iI
iO
3u
3u
3u
3u
M1
M2
vO
-
Page V.4-8
Cadcode Current Mirror

CIRCUIT
SPICE
iOUT
iI
M3
60uA
M4
40uA
iOUT
mproved current mirror

M1 1 1 0 0 MNMOS1 W=3U L=3U
M2 2 1 0 0 MNMOS1 W=3U L=3U
M3 3 3 1 0 MNMOS1 W=3U L=3U
M4 4 3 2 0 MNMOS1 W=3U L=3U
IIN 0 3
VOUT 4 0
.DC VOUT 0 5 0.1
+ IIN 10U 60U 10U
.PRINT DC ID(M4)
.PROBE
.END
iI = 60uA
iI = 50uA
iI = 40uA
iI = 30uA
iI = 20uA
20uA
M1
M2
iI = 10uA
VSS
vOUT
Example of Small Signal Output Resistance Calculation ii

io
+
v3
-
+
rds3
gm3 v3
v4
-
+
rds4
v1 =v3 =0
+
v1
-
1).
2).
3).
gm4 (v3 +v1 -v2 )

io
+
rds1
gm1 v1
v2
-
rds2
gm2 v1
gmbs v2
vo
vo = v4 + v2 = rds4 [i o - gm4(v 3 + v1 - v2) + gmbs4v2] + rds2(io - gm2v1)

v 2 = iords2
v o = io [rds4 + (gm4 rds2)rds4 + (rds2gmbs4)rds4 + rds2]
vo
4). rout =
io = rds4 + rds2 + rds2rds4(gm4 + gmbs4 )
Page V.4-9
Wilson Current Mirror

Circuit and PerformanceIin = 80uA
iI
M3
70uA
65.5uA
iO
60uA
50uA
45.0uA
M1
M2
VSS
40uA
iO
30uA
22.5uA
20uA
10uA
0
0
Wilson Current Source
M1 1 2 0 0 MNMOS W=15U L=3U
M2 2 2 0 0 MNMOS W=15U L=3U
M3 3 1 2 0 MNMOS W=15U L=3U
R 1 0 100MEG
.MODEL MNMOS NMOS VTO=0.75, KP=25U,
+LAMBDA=0.01, GAMMA=0.8 PHI=0.6
IIN 0 1
VOUT 3 0
.DC VOUT 0 5 0.1 IIN 10U 80U 10U
.PRINT DC V(2) V(1) ID(M3)
.PROBE
.END
vOUT
Principle of Operation:
Series negative feedback increase output resistance
1. Assume input current is constant and that there is high resistance to
ground from the gate of M3 or drain of M1.
2. A positive increase in output current causes an increase in vGS2 .
3. The increase in vGS2 causes an increase in vGS1 .
4. The increase in vGS1 causes an increase in iD1.
5. If the input current is constant, then the current through the resistance to
ground from the gate of M3 or the drain of M1 decreases resulting in a decrease
in vGS3.
6. A decrease in v GS3 causes a decrease in the output current opposing the
assumed increase in step 2.
Page V.4-10
Output Impedance of the Wilson Current Source

iout
+
iin=0
v3
+
rds3
gm3(v1-v2)
gm1v2
rds1
+
v1
-
rds2
gm2v2
+
v2
-
gmbs3v2
vout
-
vout = rds3[iout - gm3v1 + gm3v2 + gmbs3v2] + v2

vout = rds3iout - gm3rds3(-gm1rds1v2) + gm3rds3v2 + gmbs3rds3v2 + v2
rds2
v2 = iout 1 + g m2 r d s 2
vout = ioutrds3 + [gm3rds3 + gmbs3rds3 + gm1rds1gm3rds3]v 2 + v2

1 + g m3 r ds3 + g mbs3 r ds3 + g m1 r ds1 g m3 r ds3
1+gm2rds2
rout = rds3 + rds2
r ds2 g m1 r ds1 g m3 r ds3

r out
r ds1 x (g m 3 r ds3 ) if g m 1 = g m 2
gm2rds2
Page V.4-11
Improved Wilson Current Mirror
Iout
Iin
M1
M4
M3
Additional diode-connected
transistor equalizes the
drain-source voltage drops
of transistors M2 and M3
M2
SPICE simulation
improved Wilson current source

M1 1 2 3 0 MNMOS1 W=12U L=3U
M2 3 3 0 0 MNMOS1 W=12U L=3U
M3 5 3 0 0 MNMOS1 W=12U L=3U
M4 2 2 5 0 MNMOS1 W=12U L=3U
.DC VOUT 0 5 0.2 IIN 10U 80U 10U
R 2 0 100MEG
IIN 0 2
VOUT 1 0
.PROBE
.PRINT DC ID(M1)
.END
77.5uA
45.0uA
Iout
Iin = 80uA
70uA
60uA
50uA
40uA
30uA
20uA
22.5uA
10uA
0
Vout
Page V.4-12
Regulated Cascode Current Mirror

VDD
iOUT
IB
M4
IIN
M3
vOUT
+
vGS4
-
M1
M2
-
VSS
Small Signal Equivalent Model iout

+
rds4
gm4vgs4
v4
+
g m3 v3
rds3
rds2
vout
v3
-
vout = (iout - gm4vgs4)rds4 + ioutrds2

vgs4 = v 4 - v 3
v3 = ioutrds2
v4 = -gm3v3rds3
vout = ioutrds4 - gm4(-gm3ioutrds2rds3 - ioutrds2)r ds4 + ioutrds2
rout = rds4 + gm4 g m3 r ds2rds3rds4 + rds2 + gm4 rds2rds4
Minimum vOUT =
2IB
W + VT
K' L
Page V.4-13
SUMMARY OF CURRENT MIRRORS
Accuracy
Output
Resistance
Minimum
Voltage
Simple
Poor (Lambda)
r ds
VON
Cascode
Excellent
g m rds2
VT + 2V ON
Wilson
Excellent
g m rds2
2VON
Good
gm 2rds3
VT + 2VON
Current Mirror
Regulated
Cascode
Page V.5-1
V.5 - REFERENCE CIRCUITS

Introduction
What is a Reference Circuit?
A reference circuit is an independent voltage or current source which has a
high degree of precision and stability.
Requirements for a Reference Circuit
1.) Output voltage/current should be independent of power supply.

2.) Output voltage/current should be independent of temperature.
3.) Output voltage/current should be independent of processing variations.
V-I Characteristics of an Ideal Reference

i
Voltage Reference
Iref
Current Reference
Vref
Page V.5-2
Concept of Sensitivity
Definition
Sensitivity is a measure of dependence of Vref (Iref) upon a parameter or
variable x which influences Vref (Iref).
Vref
S
x
Vref
Vref
x Vref
=
=
x
Vref x
x
where
x = VDD or temperature
Application of Sensitivity
V
Vref ref x

Vref =
x
x
For example, if the sensitivity is 1, then a 10% change in x will cause a 10%
change in V ref.
Vref
Ideally,
S
x
V.5-1 - SIMPLE REFERENCES

Objective is to minimize,
Vref
S
V DD
Vref
Vref
VD D
VDD
Types of references include,

1. Voltage dividers - passive and active.
2. MOS diode reference.
3. PN junction diode reference.
4. Gate-source threshold referenced circuit.
5. Base-emitter referenced circuit.
Page V.5-3
Page V.5-4
Passive Divider
Accuracy is approximately equivalent to 6 bits (1/64).
VDD
RA
V1
I
RB
V2
RC
VSS
Active Dividers
I
V3
M3
VDD
VDD
V2
M2
V1
M1
M2
M2
+
M1 Vref
-
+
M1 Vref
-
Page V.5-5
PN Junction Voltage References

VCC
kT
I
I
VREF = VBE = q ln = Vt ln
Is
I s
V CC - V B E VCC
R
If I =
R
VREF
VCC
V REF V t ln
RI
Sensitivity:
VREF
V CC
1
VCC
ln RI
s
VREF
If VCC = 10V, R = 10 k, and Is = 10-15A, then
= 0.0362.
V CC
Modifying the Value of VREF
VCC
R
IR1
R1
If >> 1, then VREF IR1 (R 1+R2)
I
+
VREF
R2
VBE
replacing IR1by
R1 gives,
R 1 +R 2
VREF
V BE
R1
or
R1+R2
VCC
V REF
Vt ln
R1
RIs
Page V.5-6
Gate-Source Referenced Circuits

(MOS equivalent of the pn junction referenced circuit)
VDD
2(VDD-V REF)
R
VREF = VGS = VT +
I
1
V REF = VT
R
2(VDD-VT)
1
+ 2 2
R
R
VREF
Sensitivity:
V REF
S
VDD
VDD
1
= V
1 + KR(V
REF
REF - V T )
If V DD = 10V, W/L = 10, R = 100k and using the results of Table 3.1-2 gives
VREF
VREF = 1.97V.and
= 0.29.
VDD
Modifying the Value of VREF

V DD
R
IR1
R1
R 1 +R 2
V GS
R1
VREF
I
+
V REF
R2
-
Page V.5-7
Bootstrapped Current Source

VDD
M4
M5
M3
RB
ID1 = I1
iOUT
ID2 = I2
M6
M2
M8
M1
R
I2
Principle:
If M3 = M4, then
I 1 = I2
(1)
also,
VGS1 = VT1 +
2I1
KNS1 = I2R
therefore,
VT1 1
I2 =
R + R
2I1
KNS1
Desired
operating
point
Eq. (2)
Eq. (1)
(2)
Undesired operating point
Page V.5-8
Bootstrapped Current Sink/Source - Continued

An examination of the second-order effects of this circuitThe relationship between M1 and R can be expressed as,
I2R = VT1 +
2I1
1
Instead of assuming that I1 = I2 because of the current mirror, M3-M4, let us

consider the effects of the channel modulation which gives
1 + PV G S 4
I 2 = I1
1 + P (V D D - V DS1 )
Solving for I1 from the above two expressions gives
I1R(1 + PVGS4) = [1 + P(V DD-V DS1)]
2I1
1
Differentiating with respect to VDD and assuming the VDS1 and VGS4 are
constant gives (IOUT = I1),
20VDD PV T1 +
IOUT
S
VDD
IOUTR(1 + P V GS4 )
2I1
1
1 + P (V D D - V DS1 )
21I1
Page V.5-9
Bootstrapped Current Sink/Source - Continued

Assume that VDD =5V, K N ' = 23.6 A/V2, VTN=0.79V, N=0.53V0.5, P =
0.590V, N=0.02V-1, K P ' = 5.8A/V2, VTP=-0.52V, P=0.67V0.5, P = 0.6V,
N=0.012V-1. Therefore,
VGS4 = 1.50V, VT2 = 1.085V, VGS2 = 1.545V, and VDS1 = 2.795V which
gives
IOUT
S
VDD
IOUT/IOUT
= 0.08 = V /V
DD DD
V DD
= 3.2A
If VDD = 6V - 4V = 2V, then IOUT = 0.08 I OUT V
DD
SPICE Results:
120A
100A
IOUT 2.8A for VDD 4V 6V
80A
IOUT
60A
40A
20A
0A
0V
2V
4V
VDD
6V
8V
10V
Page V.5-10
Base-Emitter Voltage Referenced Circuit

VDD
M4
M5
M3
RB
ID1 = I1
ID2 = I2
M6
M1
M8
I2
VBE1
R = I5
V = I2R V BE1
Q1
M2
iOUT
Page V.5-11
V.5-2 - TEMPERATURE DEPENDENCE

Objective
Minimize the fractional temperature coefficient which is defined as
1 Vref
T CF = V T parts per million per C or ppm/C
ref
Temperature Variation of References
PN Junction:
v
i I s exp
Vt
-V GO
I s = KT 3 exp V
t
I
I1s Ts
(ln I s )
3 V GO V GO
= T + TV TV
T
t
t
dvBE V BE - V G O
= -2mV/C at room temperature
dT
T
(VGO = 1.205 V and is called the bandgap voltage)
Gate-Source Voltage with constant current (Strong Inversion):

dVGS dVT
dT = dT +
2L d
WCox dT
ID
o
o = KT-1.5 ; VT = VT0 - T or VT(T) = VT(To) - (T-To)

dV G S
3
=
+
dT
4
V GS - V T
Page V.5-12
PN Junction Voltage Reference

VDD
+
VREF = VBE = kT ln I = Vt ln I
q
Is
Is
-
V DD - v B E V DD
I=
R
R
TCF =
------->
VDD
V REF = V t ln RI
s
dV REF V REF - V G O
VREF dT =
TVREF
Vt dR
- V
REF RdT
Assume VREF = 0.6 volts and that R is a polysilicon resistor

dR
= +1500 ppm/ C gives a

RdT
0.6 - 1.205
0.026
TC F = (300K)(0.6) - 0.6 (0.0015)
= -0.003361 - 0.000065 = -3426 ppm/C
Page V.5-13
Gate - Source Referenced Circuits

MOS Equivalent of the PN Junction Referenced Circuit
VDD
I
+
VREF
-
1
V R E F = V T R +
1 dV REF
=
TCF = V
REF dT
2(VDDVT)
1
+ 2 2
R
R
1
VREF
V DD V REF 1.5
1 d R
2R
R dT
T
1
1 +
2R (V DD V REF )
Page V.5-14
Example
W = 2L, VDD = 5V, R = 100 K , K=110 , VT = 0.7, T = 300 K, = 2.3
mV/C
Solving for VREF gives
VREF = 1.281 V
dR
= +1500 ppm/C
RdT
2.3 10-3 +
1 dV REF
1
TCF = 1.281 dT = 1.281
TCF = - 928 ppm/C
1+
5 1.281
1.5 1500 10-6
300
2 211010-6 100K
1
2 211010-6 100K (5 - 1.281)
Page V.5-15
Bootstrapped Current Source/Sink

VDD
M4
M5
M3
RB
I D1 = I1
I D2 = I2
iOUT
M6
M2
M8
M1
R
2ID1 L
+ VT
VGS1
V ON + V T
K'W
ID2 = R =
=
= ID1 = IOUT
R
R
Assuming that VON is constant as a function of temperature because of the
bootstrapped current reference, then
TCF =
1 dVT
1 dR
- 1 dR
=
VT dT
R dT VT - R dT
If R is a polysilicon resistor, then

-2.3 x 10 -3
- 1.5x10 -3 = -3800 ppm/C
1
If R is an implanted resistor, then
TC F =
TC F =
-2.3 x 10 -3
- 0.4x10-3 = -2700 ppm/C
1
Page V.5-16
Base-Emitter Voltage - Referenced Circuit

VDD
M4
M5
M3
RB
ID1 = I1
ID2 = I2
iOUT
M6
M1
M8
Q1
vBE1
I2 R
M2
1 dv BE 1 dR
-----> TCF = v
- R dT
BE dT
Assuming VBE = 0.6 volts and a polysilicon resistor gives

1
TCF = 0.6 (-2x10-3) - (1.5x10-3) = -4833 ppm/C
Page V.6-1
V.6 - SUMMARY
The circuits in this chapter represent the first level of building blocks in
analog circuit design.
The MOS transistor makes a good switch and a variable resistor with
reasonable ranges of linearity in certain applications.
Primary switch imperfection is clock feedthrough. In order for switches to
be used with lower power supplies, VT must be decreased.
The primary characteristics defining a current sink or source are VMIN and
Rout. V MIN 0 and Rout . Typically the product of VMIN times Rout
is a constant in most designs.
Current mirrors are characterized by:
Gain accuracy
Gain linearity
VMIN on output
Rout
Rin
Reasonably good power supply independent and temperature independent
voltage and current references are possible. These references do not satisfy
very stable reference requirements.

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Allen and Holberg - CMOS Analog Circuit Design

Allen and Holberg - CMOS Analog Circuit Design

Input Differential Amplifier

Current Source Current

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V.1 - MOS SWITCH

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MOS TRANSISTOR AS A SWITCH

On Characteristics of A MOS Switch

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MOS SWITCH VOLTAGE RANGES

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I-V CHARACTERISTICS OF THE MOS SWITCH

SPICE Input File:

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MOS SWITCH ON RESISTANCE AS A FUNCTION OF VGS

MOS Switch On Resistance

SPICE Input File:

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INFLUENCE OF SWITCH IMPERFECTIONS ON

Finite OFF Current

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What is the on resistance of an enhancement MOS switch if VS = 0V, VG =

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INFLUENCE OF PARASITIC CAPACITANCES

Simplified Distributed Model

CGSO = Voltage independent (1st-order), gate-source, overlap cap.

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Charge Injection Sensitivity to Gate Signal Rate

Case 1 - Slow Fall Time:

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Intuition about Fast and Slow Regimes

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Illustration of Parasitic Capacitances

CGS and CGD result in clock feedthrough

Clock signal couples through CGD on the

Clock signal couples through

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Net feedthrough on C1 at t2:

At t3, additional charge has been added due to CGS overlap of M2 as 2

Allen and Holberg - CMOS Analog Circuit Design

Giving at the end of t3 (before M2 turns on):

The final change in Vout is:

Ideally the output voltage change is VIN

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Rigorous Quantitative Analysis of Fast and Slow Regimes

When operating in the slow regime defined by the relationship

where VHT is defined as

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In the fast swithing regime defined by the relationship

the error voltage is given in Eq. (8) below as

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POSSIBLE SOLUTIONS TO CLOCK FEEDTHROUGH

Complete cancellation is difficult.

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Advantages 1.) Larger dynamic range.

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DYNAMIC RANGE LIMITATIONS OF SWITCHES

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Brooklyn Bridge Effect