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IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 12, DECEMBER 2002

Low-Frequency Noise Characteristics

in p-Channel FinFETs
Jeong-Soo Lee, Yang-Kyu Choi, Daewon Ha, Tsu-Jae King, and Jeffrey Bokor, Fellow, IEEE

AbstractWe report on the characterization of low-frequency

noise in fully depleted (FD) double-gate p-channel FinFETs.
dependence, considerable
While the average noise follows a 1
device-to-device variations in noise level are observed due to the
statistical fluctuation of the number of oxide traps involved. We
found that the low-frequency noise in poly-Si-gated p-FinFETs is
mainly governed by the carrier number fluctuation with correlated mobility fluctuation. The low-frequency noise characteristics
indicate that the FinFET device can be a promising candidate for
analog and RF applications.
Index TermsDouble-gate, FinFET, low-frequency noise, metal
gate, Molybdenum, silicon-on-insulator (SOI), ultrathin body.

I. INTRODUCTION

OW-FREQUENCY noise is an important parameter for

analog and RF applications. For example, low-frequency
noise in MOS devices is up-converted to oscillator phase noise,
degrading system performance [1]. An increase in the fluctubehavior has
ation of the noise level and deviation from
been reported as MOSFET dimensions are scaled down [2]. Recently, fully depleted (FD) silicon-on-insulator (SOI) devices
have been widely demonstrated and show promise for highspeed [3], analog [4], and RF applications [5]. The FinFET,
which has a double-gate straddling a narrow silicon fin, is a
candidate structure for FD-SOI technology. High-performance
nanoscale FinFETs with excellent short-channel behavior have
recently been demonstrated [6], [7].
In this letter, we report the low-frequency noise characteristics of p-channel FinFETs. Due to the small device geometry, the
noise behavior shows considerable device-to-device variation in
noise amplitude. The noise behavior dependence on the gate material and bias conditions is also presented, and the sources of
noise are discussed.
II. DEVICE FABRICATION AND MEASUREMENT
Standard (100) SOI wafers (p-type, 15 cm) were used as
the starting material. The 100-nm silicon film was thinned to
Manuscript received August 13, 2002; revised October 1, 2002. The lowfrequency noise characterization system at the University of California at
Berkeley was supported by the AFOSR DURIP Grant F49620-01-1-0285.
This work was supported by SRC under Contract 2000-NJ-850 and MARCO
Contract 2001-MT-887.
J.-S. Lee was with the Department of Electrical Engineering and Computer
Science, the University of California, Berkeley, CA 94720 USA. He is now with
the Department of Electrical Engineering, The University of Texas at Dallas,
Richardson, TX 75080 USA (e-mail: ljs6951@utdallas.edu).
Y.-K. Choi, D. Ha, T.-J. King, and J. Bokor are with the Department of Electrical Engineering and Computer Science, University of California, Berkeley,
CA 94720 USA.
Digital Object Identifier 10.1109/LED.2002.805741

Fig. 1. Tilted SEM photographs of double-gate p-FinFETs with Mo-gate

(L = 400 nm and W = 50 nm). Subthreshold I V characteristics for
p-FinFETs with n poly-Si-gate and Mo-gate are shown in the inset.

50 nm, with a 50-nm thermal oxide remaining on top to serve

as a hard mask. Fins of extremely narrow and uniform width
(beyond the lithographic limit) were obtained with the spacer
lithography process [6], [7]. Following a sacrificial oxidation
of the fin sidewalls, a 2.1-nm gate oxide was grown. Then,
either Molybdenum (Mo) (40-nm-thick, deposited by a dc
magnetron sputtering at 200 C and 10 Torr) or n poly-Si
was deposited as the gate material. After patterning and etching
the gate stack, source/drain (S/D) implantation and 900 C
RTA for 60 s were performed. Further details of this device
fabrication process have been reported elsewhere [6]. Fig. 1
shows a top-view SEM picture of a p-FinFET comprised of six
fins, with effective channel width 0.6 m ( 2 sides 6 fins
0.05 m fin height). Subthreshold characteristics for p-FinFETs
are shown in the inset of Fig. 1. The threshold voltage (defined
nA/ m) is 0.85 V for the poly-Si-gated device
at
and 0.35 V for the Mo-gated device, respectively. Mo-gated
p-FinFET shows lower threshold voltage due to the higher
work function of Mo film ( 5 eV) [7].
Prior to noise analysis, the FinFET dc characteristics were
measured with an HP4155 Semiconductor Parameter Analyzer.
Low-frequency noise behavior was then measured over the frequency range of 1 Hz10 kHz with a BTA9812B Standard Noise
Analyzer. The output noise current was applied to an HP35670A
Dynamic Signal Analyzer after being amplified by the lownoise amplifier in the BTA9812B.

0741-3106/02$17.00 2002 IEEE

LEE et al.: LOW-FREQUENCY NOISE CHARACTERISTICS IN p-CHANNEL FinFETs

Fig. 2. Equivalent gate voltage noise versus frequency in four p-FinFETs with
Mo-gate biased at V = 50 mV and I = 0:1 A/m. The dashed line is
the average noise spectra using (1) with N = 10.

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Fig. 3. Equivalent gate voltage noise characteristics of p-FinFETs as a function

of gate voltage at f = 10 Hz and V = 50 mV. Symbols and the error bars
are calculated from (1) and (4), respectively.

III. RESULTS AND DISCUSSION

Fig. 2 shows the equivalent gate voltage noise spectra
versus frequency for Mo-gated p-FinFETs with channel area
0.24 m . The measured noise spectra from four devices at
the drain current level of 0.1 A/ m are shown. Large deviations in noise level among these devices are observed, which
are mainly due to the statistical fluctuation of the number of
oxide traps confined in the small device area [2]. Such variaof
tions in noise spectra are also observed in the measured
poly-Si-gated p-FinFETs. The average equivalent gate voltage
expressed in decibels, is calculated from
noise
devices by
(1)
denotes the equivalent gate voltage noise of the th
where
device. Although one or two noise humps are observed in each
can be characterized
individual noise curve, the calculated
dependence, with varying between 1 and 1.2 in the
by a
frequency range of 1 Hz10 kHz.
The expression for the carrier number fluctuation model including correlated mobility fluctuation was recently given in [8]
(2)
where
(3)

Fig. 4. Equivalent gate voltage noise characteristics of p-FinFETs

with poly-Si-gate as a function of drain voltage at f = 10 Hz and
V = 100 mV. The solid symbol and the error bars are calculated
V
from (1) and (4), respectively.

frequency;
frequency exponent;
device area;
oxide trap density (units: eV cm ).
To characterize the statistical fluctuation in noise spectra, the
is calculated in decibels as
standard deviation

where
Coulomb scattering coefficient;
low-field mobility;
area gate capacitance;
flat-band voltage noise density associated with interface charge fluctuation;
tunneling attenuation length ( 1 );
thermal energy;

(4)
values are expressed in decibels.
where the
characteristics of the
Fig. 3 shows the comparison of
p-FinFETs with n poly-Si-gates and Mo-gates, measured at
10 Hz as a function of gate voltage. The error bars indicate 2

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IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 12, DECEMBER 2002

values. For p-FinFETs with poly-Si-gate,

is almost constant in weak inversion and increases in a quadratic manner in
strong inversion, which clearly supports the validity of the carrier number fluctuation model with correlated mobility fluctuis
ation. On the other hand, for p-FinFETs with Mo-gate,
almost constant from weak inversion to strong inversion, which
suggests that the low-frequency noise is mainly dominated by
the carrier number fluctuation due to higher oxide trap density.
From Fig. 3, one can extract the average oxide trap density
using (1)(3) at
. The extracted trap density
of 1.5 10 eV cm for p-FinFETs with poly-Si-gate is
comparable to bulk-Si MOSFETs and FD MOSFETs [9], [10].
10 eV cm
The high average oxide trap density of 1
for p-FinFETs with Mo-gate is attributed to sputtering damage
during Mo film deposition and can be reduced by using the CVD
method [11] and adequate thermal annealing. Fig. 4 shows
characteristics of poly-Si-gated p-FinFETs, measured at 10 Hz
V. The
as a function of drain voltage at
noise is found to be independent of the drain voltage without
excess noise, which suggests that the p-FinFET is fully depleted
with no impact ionization [12].
IV. CONCLUSIONS
Low-frequency noise characteristics have been investigated
in FinFETs for the first time. Because of the small device
area, the measured noise exhibits device-to-device fluctuations
by more than one order of magnitude. Although one or two
noise humps are observed in each individual noise curve, the
variation. The low-freaverage noise is found to follow a
quency noise behavior in p-FinFETs with poly-Si-gate is well
described by the carrier number fluctuation with correlated
mobility fluctuation. Due to the noise characteristics which are
comparable to bulk-Si MOSFETs, the FinFETs are expected to
be very promising for analog and RF circuit applications.

ACKNOWLEDGMENT
The authors would like to thank the University of California
at Berkeley Microlab staff for their support in device fabrication.
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