Design & Implementation of Low Power 4-bit Flash ADC in

0.18m CMOS using Custom design approach

Abstract
The trend toward increased integration of analog and digital circuitry requires that data
converters be embedded in large digital ICs. For high resolution ADCs the sheer volume became
a limitation. By their nature, applications of Flash ADC rely heavily on DSP, which performs
best when implemented on the finest geometry CMOS process. On the other hand, ADCs, as
with analogue circuits in general, tend to function best when fabricated on more mature CMOS.
Comparators are the key analog building block of any flash ADC and strongly influence
performance. A high degree of comparator accuracy is essential for good ADC performance. The
linearity of the circuit depends on the comparator. However, integration of analog circuitry in
low voltage scale VLSI technologies results in degraded precision due to large device mismatch
and limited voltage swing. Reduced precision can be compensated for through the use of offset
correction schemes. Analog offset correction techniques are typically used, but these schemes are
increasingly difficult to implement in modern CMOS processes. For this reason, the issue of
comparator offset is becoming a bottleneck in the design of flash ADCs.
This work concerns the design of Flash type of Analog to Digital Converter (ADC) which
is more likely to be used for high quality audio and video signals. It uses resistor ladder logic,
comparator and encoder to convert the continuous input signal into binary form. Comparator,
encoder circuits are designed using CMOS technology and its output response is obtained to
meet the requirements. Comparators form the main element to design Flash ADC. Design of
these circuit use gpdk 180nm technology in cadence tool and simulated using SPECTRE.

Flash ADC Basics:

For high speed applications, flash ADC is often used. Flash ADC is very fast and used for low
resolution application due to its parallel architecture. It is best and less complex up to 8 bits. But
when the number of bits increased complexity increases since the number of comparator needed
is large. The flash ADC consists of three main components resistor string, comparator bank,
encoder logic. Sample and hold circuit is not used usually in this type. For N bit ADC, 2N
N
resistors and 2 1 comparators and

2N 1 to N bit encoder is needed. The block diagram

for typical flash ADC architecture is shown in the figure below.

For an "N" bit converter, the circuit employs

N
with 2

2N 1

comparators. A resistive divider

resistors provides the reference voltage. The reference voltage for each comparator is

one least significant bit (LSB) greater than the reference voltage for the comparator immediately
below it. Each comparator produces a "1" when its analog input voltage is higher than the
reference voltage applied to it. Otherwise, the comparator produces a "0", the flash ADC is
composed of three major components: resistors string, comparators and encoder.

The analog input voltage is concurrently compared to the reference voltage levels
generated from resistors string and the speed of A/D conversion is therefore maximized. The
outputs of comparators form a thermometer code (TC) which is a combination of a series of
zeros and a series of ones, e.g., 000000111111.
Because binary code is usually needed for digital signal processing, a thermometer code
is then transformed to a binary code through a 2k-1 to k, TC to BC encoder, where k is the
resolution (bits) of ADCs. The cost of such a traditional encoder increases exponentially with the
resolution. Optimizations on area cost, circuit latencies an power consumptions are greatly
expected. In this work we will make use of low power Comparator in the design throughout.

The Design/Implementation steps are as follows:

Understand the specifications of Flash ADC and its sub-modules.

Understand the Inputs/Outputs required.
Designing and Optimizing the Comparator circuit.
Simulate the Comparator circuit to get expected results.
Developing the 4-bit Thermometer Encoder circuit.
Obtaining the Proposed Flash ADC circuit and to simulate to get expected results.
Attach the 0.18m technology files.
Place and route the logic using Cadence Virtuoso Layout XL tool.
Check for DRC, LVS and RCXs.
Generate the post route netlist and simulate the post routed netlist in Cadence Spectre

simulator.
Generate GDSII.