Simulation of High Voltage DC Using PSPICE

SUBMITTED BY:
KUNTAL SATPATHI
INDRANIL DEBNATH
SUVRA KANTI PAL
SOURAV BISWAS
SUPRIYO MONDAL

(07/EE/02)
(07/EE/08)
(07/EE/18)
(07/EE/22)
(07/EE/35)

HALDIA INSTITUTE OF TECHNOLOGY

SUBMITTED FOR THE DEGREE OF
BACHELOR OF TECHNOLOGY IN THE DEPARTMENT OF
ELECTRICAL ENGINEERING

Page | 1

CONTENTS
Topic
CHAPTER 1
Abstract
1.1
Half Wave Rectifier Circuit
1.2
Full Wave Rectifier Circuit
1.3
Voltage Doubler Circuit
1.4
Cockcroft Walton Voltage Multiplier Circuit
1.5
Operation of two stage Cockcroft Walton Multiplier
1.5.1
Circuit
Operation of multiple stage Cockcroft Walton
1.5.2
multiplier circuit
CHAPTER 2
Variation Of Off-load Steady State Voltage Profile
2.1
with change in number of stages using schematics.
Variation
Of Offload Steady State Voltage Profile for
2.1.1
three stage voltage multiplier circuit.
Variation Of Offload Steady State Voltage Profile for
2.1.2
two stage voltage multiplier circuit.
Variation Of Offload Steady State Voltage Profile for
2.1.3
single stage circuit.
Miscellaneous Results
2.2
CHAPTER 3
PSPICE Simulation Of Cockcroft Walton Circuit (33.1
Stage)
Simulation results
3.2
Observations for Various types of Loads
3.3
CHAPTER 4
CASE STUDY: A 3-Stage Cockcroft Walton Circuit
4.1
for a practical load (C=20pF & R=10k)
4.2
4.2.1
4.2.2
4.3
4.5
4.6

Simulation results
Voltage waveform pattern in smoothing capacitor.
Voltage waveform pattern in oscillating capacitor
Analysis and discussion
Conclusions
References

Page No.
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4
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9
10
11
12

20
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27
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29
30
31
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35

Page | 2

ABSTRACT
One of the cheapest and popular ways of generating high voltages at relatively low
currents is the classic multistage diode/capacitor voltage multiplier, known as Cockcroft
Walton multiplier, named after the two men who used this circuit design to be the first to
succeed in performing the first nuclear disintegration in 1932. James Douglas Cockcroft and
Ernest Thomas Sinton Walton, in fact have used this voltage multiplier cascade for the
research which later made them winners of the 1951 Nobel Prize in physics for
"Transmutation of atomic nuclei by artificially accelerated atomic particles". Less known is
the fact that the circuit was first discovered much earlier, in 1919, by Heinrich Greinacher, a
Swiss physicist.

For this reason, this doubler cascade is sometimes also referred to as the Greinacher
multiplier.

Page | 3

CHAPTER: 1
HALF WAVE RECTIFIER CIRCUIT
Theory:
During the positive half cycle the diode is forward biased and the capacitor gets
charged with the application of the voltage. And during the negative half cycle the diode is
reverse biased and thus the capacitor discharges through the load resistance R. The output
voltage is shown in the figure given.
Circuit Diagram:

In this circuit,
D: diode
R: load resistance
C: smoothing (or reservoir) capacitance
Assumptions:
o The leakage reactance of the transformer is negligible
o The internal impedance of the diode is very small during conduction

Page | 4

Operation:
When the load is absent(R=)
During conduction of diode D, the capacitor is charged to the maximum voltage +Vmax
of the AC voltage Va(t) of the HT transformer and the D.C. voltage across the capacitor
remains constant at +Vmax, whereas Va(t) oscillates between +Vmax and V
Vmax.
The diode must be dimensional, therefore to withstand reverse voltage of 2Vmax. Also
if the H.T. transformer is grounded at the terminal B instead of A, and the output voltage is
taken across the diode the D.C. voltage oscillates betw
between
een 0 and +2Vmax. This circuit is
known as Voltage Doubler Circuit by Villard.
When the circuit is loaded:
The output voltage does not remain constant.

tc= T

During conduction period (T=1/f) of the AC voltage a charge Q is transferred to the load RL,
which is represented by,
  =
Q=
 

v(t)dt = IT =

(1)

I:: the mean value of the DC output iL(t),

v(t): the d.c. voltage which includes a ripple as shown.
This charge is supplied by the capacitor over the period T when the voltage v(t) changes
from Vmax to Vmin over approximately period T, neglecting the conduction period of the
diode (tc=T) show in Figure.
Page | 5

This charge is also supplied from the transformer within the short conduction period (tc=T).
Therefore
Q=
  =
 
(2)
As <<T, the transformer current i(t) is pulsed and is of much bigger amplitude than the
direct current iL.
Calculation of Ripple Voltage (V)
According to IEEE standards 4-1978, the value of a direct voltage is defined by its
arithmetic mean value V, expressed as


Vmean =
 


(3)

Where, T- time period of the voltage wave of frequency f =1/T

Test voltage as applied to test objects deviate periodically from the mean value and this
deviation is known as Ripple. The ripple voltage is defined as the half the difference
between the maximum and the minimum values


V= [Vmax-Vmin]


(4)

The ripple factor is defined as the ratio of amplitude to the arithmetic mean, i.e. V/Vmean.
Now for the rectifier circuit, the charge delivered by the capacitor for a decrease of voltage
of dV is
dQ= CdV
So the total charge transferred which can be obtained from equation(4)


Q =
  =
  =-C(Vmax-Vmin)

= -2CV
From (1) and (5) taking the magnitude of Q
IT =
V=

"

...(5)

= 2VC

!"
Page | 6

FULL WAVE RECTIFIER CIRCUIT

Theory :
A Full Wave Rectifier is a circuit, which converts an ac voltage into a pulsating dc voltage
using both half cycles of the applied ac voltage. It uses two diodes of which one conducts
during one half cycle while the other conducts during the other half cycle of the applied AC
voltage.
During the positive half cycle of the input voltage, diode D1 becomes forward biased and
D2 becomes reverse biased. Hence D1 conducts and D2 remains OFF. The load current
flows through D1 and the voltage drop across RL will be equal to the input voltage.
Circuit Diagram:

Operation:
During the negative half cycle of the input voltage, diode D1 becomes reverse biased and
D2 becomes forward biased. Hence D1 remains OFF and D2 conducts. The load current
flows through D2 and the voltage drop across RL will be equal to the input voltage.

Page | 7

Calculation of Ripple Factor:

& ' & */&
 #$%
()

()

Irms= ,

()

()

. / 0 1 12
-  
$

#$%

& ' & */&

#$%
()

4


=  $ = =1.11
5-

=61.11 1:

5
 =0.482

Page | 8

VOLTAGE DOUBLER CIRCUIT (Developed by Greinacher in 1990):

Both full wave and half wave rectifier circuits produced DC voltage less than AC maximum
voltage. For higher DC voltage, voltage doubler circuit is used.
Circuit Diagram:

During negative half cycle, the capacitor C1 is charge through diode D1 to voltage Vmax.
During the next half cycle the terminal Y of the capacitor C1 rises to Vmax and hence the
terminal X attains a potential 2Vmax. Thus, capacitor C2 is charged to 2Vmax through D2.

Normally, the voltage across the load is less than 2Vmax depending upon the time constant of
the circuit, capacitor C2 and the load RL which would be discussed in the following chapters.

Page | 9

COCKCROFT WALTON MULTIPLIER CIRCUITS

Introduction
One of the cheapest and popular ways of generating high voltages at relatively low
currents is the classic multistage diode/capacitor voltage multipler, known as Cockcroft
Walton multiplier, named after the two men who used this circuit design to be the first to
succeed in performing the first nuclear disintegration in 1932. James Douglas Cockcroft and
Ernest Thomas Sinton Walton, in fact have used this voltage multiplier cascade for the
research which later made them winners of the 1951 Nobel Prize in physics for
"Transmutation of atomic nuclei by artificially accelerated atomic particles". Less known is
the fact that the circuit was first discovered much earlier, in 1919, by Heinrich Greinacher, a
Swiss physicist.
For this reason, this doubler cascade is sometimes also referred to as the Greinacher
multiplier.
Advantages of Cockcroft Walton Circuit:
Unlike transformers this method eliminates the requirement for the heavy core and the
bulk of insulation required.
By using only capacitors and diodes, these voltage multipliers can step up relatively
low voltages to extremely high values, while at the same time being far lighter and
cheaper than transformers.
The biggest advantage of such circuit is that the voltage across each stage of this
cascade is only equal to twice the peak input voltage, so it has the advantage of
requiring relatively low cost components and being easy to insulate.
One can also tap the output from any stage, like a multi-tapped transformer. They
have various practical applications and find their way in laser systems, CRT tubes,
HV power supplies, LCD backlighting, power supplies, x-ray systems, travelling
wave tubes, ion pumps, electrostatic systems, air ionizers, particle accelerators, copy
machines, scientific instrumentation, oscilloscopes, and many other applications that
utilize high voltage DC.

Page | 10

Operation of 2-Stage Cockcroft Walton Circuit:

The Cockcroft Walton or Greinacher design is based on the Half-Wave Series
Multiplier, or voltage doubler. In fact, all multiplier circuits can be derived from its
operating principles. It mainly consists of a high voltage transformer TS, a column of
smoothing capacitors (C2, C4), a column of coupling capacitors (C1, C3), and a series
connection of rectifiers (D1, D2, D3, D4). The following description for the 2 stage CW
multiplier assumes no losses and represents sequential reversals of polarity of the source
transformer TS in the figure shown below. The number of stages is equal to the number of
smoothing capacitors between ground and OUT, which in this case capacitors are C2 and C4.

Operation:
1. Ts=Negative Peak: C1 charges through D1 to Epk at current ID1
2. Ts=Positive Peak: Epk of Ts adds arithmetically to existing potential C1, thus C2 charges to 2Epk
through D2 at current ID2
3. Ts=Negative Peak:C3 is charged to 2Epk through D3 at current ID3
4. Ts=Positive Peak: C4 is charged to 2Epk through D4 at current ID4.
Output is then 2n*Epk where N = number of stages.
In reality several cycles are required to
reach full voltage. The output voltage
closely follows the curve of an RC
network as shown above. R is the output
impedance of the ac source, whilst C is
the effective dynamic capacitance of the
CW multiplier. This charging occurs only
upon switching on the CW multiplier
from a discharged state, and does not
repeat itself unless the output is short
circuited. Most common input AC
waveforms are sine waves and square
waves.

CW: stands for Cockcroft-Walton

Page | 11

Operation of n stage Cockcroft Walton Circuit:

When the HV output terminal is open circuited (I=0):
When B is positive w.r.t A, C1 is charged to Vmax through D1 and when A is +ve, the M
point attains a voltage of 2Vmax and C1 is charged to 2Vmax through D1.

In the next half cycle , when B is again +ve w

w.r.tt A, potential of A falls and so, potential of
N falls and becomes less than potential of M. Hence C2 is charged through D2 . In the next
half cycle, A is +ve w.r.tt B and potential of M and N rise. Thu
Thuss charging C2 through D2.
Finally, all the capacitors C1, C2 Cn and C1, C2...Cn are charged.

Page | 12

Let us consider the operation of the 3-stage Cockcroft Walton Circuit (n=3):
Circuit Diagram:

Voltage profiles of the Oscillating capacitors C1, C2, C3 are v(C1), v(C2), v(C3):
For 3 cycles (0-60ms):
2.5KV

2.0KV

1.0KV

0V

-1.0KV

-1.5KV
0s
V(2)

V(3)

V(4)

10ms
V(1)

20ms

30ms

40ms

50ms

60ms

Time

Where:
v(1): input voltage
v(2), v(3), v(4) are voltage across smoothing capacitors C1, C2, C3 respectively.

Page | 13

For 100 cycles (steady state operation)

8.0KV

4.0KV

0V

-4.0KV
0s
V(2)

0.2s
V(3) V(4)

0.4s

0.6s

0.8s

1.0s

1.2s

1.4s

1.6s

1.8s

2.0s

Time

Where:
v(2), v(3), v(4) are voltage across smoothing capacitors C1, C2, C3 respectively.
Voltage profiles of the Smoothing capacitors C1, C2, C3 are v(C1), v(C2), v(C3):
For 3 Cycles:
2.5KV

2.0KV

1.0KV

0V

-1.0KV

-1.5KV
0s
V(1)

V(5)

V(6)

10ms
V(7)

20ms

30ms

40ms

50ms

60ms

Time

Where:
v(1): input voltage
v(5), v(6), v(7) are voltage across smoothing capacitors C1, C2, C3 respectively.

Page | 14

For 100 cycles:

8.0KV

4.0KV

0V

-4.0KV
0s

1.0s
V(5)

V(6)

2.0s

3.0s

4.0s

5.0s

6.0s

V(7)
Time

Where:
v(5), v(6), v(7) are voltage across smoothing capacitors C1, C2, C3 respectively.
It is seen that:

The potential across C1, C2Cn are oscillatory due to the supply voltage
oscillation, this column is known as oscillating column. Here in this case the
potential at node 2 varies from 0 to 2.2 kV, at node 3 from 2.2kV to 4.4kV and at node
4 from 4.4kV to 6.6kV.

The potential across C1, C2 ..Cn remain constant with reference to ground
potential; this column is known as smoothening column. Here in this case the
potential at node 5 is fixed at 6.6kV, at node 6 is fixed at 4.4kV and at node 7is fixed
at 2.2kV.

The voltage across all capacitors is of DC type, the magnitude of which is 2Vmax (in
this case 2.2kV) across each stage, except capacitor C1 where it is Vmax only.

Every diode D1, D2 Dn , D1, D2,Dn is stressed with 2Vmax or
twice of AC peak voltage.

The H.V output will reach a maximum voltage of 2nVmax (in this case 6.6kV across
node 5).

Page | 15

When the H.V output terminal is loaded (I>0):

If the generator supplies a load current I, the output voltage will never reach the value
2nVmax ; the output voltage will have ripples. Therefore, we have to calculate two quantities Ripple Voltage(V)
Voltage Drop(V0)

Calculation of Ripple Voltage (V):The output voltage on loaded condition is shown:

At time instant t1, when v(t) is at +Vmax ,the rectifiers D1,D2.,Dn just stopped to
transfer charge to the smoothing column, C1,C2..Cn. The charging of the
smoothing column takes place during the positive half-cycle.
During the negative half-cycle, the rectifiers D1, D2.. Dn conduct and the
oscillating column is charged.
Let,
q=charge transferred to the load per cycle, thus charge comes from smoothing column;
f=supply frequency;
T=time period;
Page | 16

I=load current;
q=I/f=IT
If no charge would be transferred during T from this stack via D1, D2,Dn to the
oscillating column, the peak to peak ripple will be
V=

q
2

(1 / C ' )
i =1

However, as the charge is transferred by D1, D2..Dn and the smoothing column is
discharged, the total ripple will be
I
1
2
n
( +
+..+ )
2 f Cn ' Cn 1'
C1'

V=

From this, we can see that lowest capacitors are responsible for most ripple and it would be
desirable to increase the capacitance in the lower stages.
However, this is very inconvenient, as a voltage breakdown at the load would completely
overstress the smaller capacitors within column.
So, equal capacitance values are used i.e. C1=C2==Cn-1=Cn=C; & the ripple is

V =
V=

I
2f

[ 1 + 2 ++ n ]
C

I n( n + 1)
2 fC
2

V= In(n + 1)
4 fC

Calculation of Voltage Drop (V0)

In order to find the voltage drop, we have to understand the charge transfer process. We
consider two cycles of operation:(a) Charging cycle:

charging of smoothing column through oscillating side.

(b) Transfer cycle:

charging of oscillating column through smoothing side.

Page | 17

(a) Charging cycle: During the positive half-cycle, the voltage at o is 2nVmax.This
discharges through RL and say the charge lost is q=IT over the cycle. This must be
regained during the charging cycle for stable operation. So, Cn must be supplied a
charge q from Cn-1. For this, Cn-1 must acquire a charge 2q from Cn-2 and in this way
C1 must have a charge of nq. In this cycle, diodes D1, D2,Dn conduct.
(b) Transfer cycle: During the negative half cycle, the diodes D1, D2Dn conduct.
Here Cn-1 transfer q charge to Cn, Cn-2 transfer 2q charges to Cn-1 and in this way, the
supply provides nq charges.
To calculate the voltage drop, we have to find the difference between the no-load
voltage 2nVmax and the on-load voltage.
Let C1=C2=..=Cn-1=Cn=C
Now capacitor C1 is charged upto
nI
nq
)= 2nVmaxC
fC
nI
nq
Vn= = = (2n-n )q/C
fC C

(2nVmax-

(i)

Capacitor C2 is charged up to (2nVmax-

nq
nq
)-(n-1)q/CC
C

I
q
[2n+ (n-1)] = [2n +(n-1)]
fC
C
q
Similarly, Vn-2= [2n+2(n-1) + 2(n-2)
C
q
V1= [2n+2(n-1)+2(n-2)+.+2.3+2.2+2.1]
C

Vn-1=

(ii)
](iii)
(iv)

By summation the voltage drop becomes,

V0= (Vn+Vn-1++V2+V1)
I

21
21
I 2 3+n
q 2 3+n
1
1
3
3
V0=
V0= C /3n
n 2 n =fC (2/3n
n2 n
n + /2-n/6)=
n + /2-n/6)

C 3

fC 3

Page | 18

Here also it is seen that most of the voltage drop is due to the lowest stage capacitors
C1, C2 etc. Hence, it is advantageous to increase their values proportional to the no. of
stages from the top.
n2
2n 3
n
& terms will become small compared to
and may
For large values of n>=5,
2
6
3

be neglected.
I 2n 3
V0=
fC 3

So, the maximum output voltage is given by,

Vomax=2nVmax-

I
fC

2n 3

From this it is seen that for a given n,f and C. The output voltage decreases
linearly with load current I.
However, for a given load, the output voltage rises initially with the no. of stages n,
reaches a maximum value and even decays if n is too large. This optimum no. of
stages can be found as
Vomax=2nVmax-

I 2 3
n
fC 3

For maximum Vomax,

2Vmax-

I
2
* * 3n 2 =0
fC 3

nopt=

V max fC
I

d
[ Vomax]=0
dn

So the maximum output voltage,

V max fC
(V
44/3 Vmax
(Vomax)max =
I

Page | 19

CHAPTER-2
VARIATION OF OFFLOAD STEADY STATE VOLTAGE PROFILE WITH
CHANGE IN NUMBER OF STAGES (Using SCHEMATICS)

300V

200V

100V

0V

-100V
0s

0.2s
V(10) V(1)

0.4s

0.6s

0.8s

1.0s

1.2s

1.4s

1.6s

1.8s

Time

1. Number Of Stages =3
v(1)= input voltage, v(10)= output voltage
Input voltage: 50V
Theoretical value of steady state output voltage: 300V
Practical Value of Steady state output voltage:
;'<=.>=

% Error=

;

296.761V

*100=1.08%

Time required to reach steady state= 1.748s

Time Constant= 241.74 ms
Page | 20

2. Number Of Stages=2

200V

100V

0V

-100V
0s

100ms

200ms

300ms

400ms

500ms

600ms

700ms

800ms

V(8) V(1)
Time

v(1)=input voltage , v(8)=output voltage

Input voltage: 50V
Theoretical value of steady state output voltage: 200V
Practical Value of Steady state output voltage: 197.85V
'<>.?@

% Error=



*100=1.072%

Time required to reach steady state= 1.0249s

Time Constant= 103.42 ms
Page | 21

3. Number Of Stages=1
100V

50V

0V

-50V
0s

20ms
V(6) V(1)

40ms

60ms

80ms

100ms

120ms

140ms

160ms

180ms

200ms

Time

v(1)= input voltage, v(6)= output voltage

Input voltage: 50V
Theoretical value of steady state output voltage: 100V
Practical Value of Steady state output voltage:
% Error=

'<?.<;


98.93V

*100=1.07%

Time required to reach steady state= 186.61ms

Time Constant= 23.83 ms

Page | 22

MISCELLANEOUS RESULTS:
1. Percentage Steady State error v/s Number of stages
Percentage Steady State Error
1.07
1.072
1.08

Number of Stages
1
2
3

Graph between Steady State Error and No.

of Stages
1.085
1.08
1.075
Steady State Error

1.07
1.065
1

2. Time Constant v/s Number of stages

Time Constant (ms)
23.83
103.42
241.74

Number of Stages
1
2
3

Graph Between Time Constant vs Number

of Stages
300
250
200
150
100
50
0

Time Constant (ms)

Page | 23

CHAPTER-3
PSPICE SIMULATION OF COCKCROFT WALTON CIRCUIT (3-Stage):
Circuit Diagram:

Program:
Cockcroft-Walton Circuit
V 2 0 sin(0 220 50 0 0)
R1 1 2 0.3
L1 1 0 20mH
L2 3 0 500mH
K L1 L2 0.98
R2 3 4 0.3
C1 4 5 500u
C2 5 6 500u
C3 6 7 500u
C4 8 9 500u
C5 9 10 500u
C6 10 0 500u
D1 0 5 DMOD
D2 5 10 DMOD
D3 10 6 DMOD
D4 6 9 DMOD
D5 9 7 DMOD
D6 7 8 DMOD
.MODEL DMOD D(Is=2.2e-15 BV=8000)
.tran 1s 50s uic
.probe V(1) V(3,0) V(8,0)
Page | 24

.end

Output:
8.0KV

6.0KV

4.0KV

2.0KV

0V
0s

5s

10s

15s

20s

25s

30s

35s

40s

45s

50s

V(8,0)
Time

Observations:
v(8,0)=output voltage
Input Voltage: 220V
Stepped up Voltage at Transformer secondary: 1.1kV
Theoretical Value of Steady State output Voltage: 6.6kV
Practical Value of Steady State output Voltage: 6.298kV
% Error=

=='=<?
==

*100=4.57%

Time Constant=185 ms
Time required reaching steady state: 1.414s
Page | 25

Observations for Various types of Loads:

Type of Load

1. Purely Resistive

2. Purely Capacitive
i) Line Insulators
ii) Bushings
iii) Power
Transformers
(<1MVA)
iv) Power
Transformers
(>1MVA)
v)Underground
Cables (per m)
a) Impregnated
Paper
Insulators
b)Gaseous
Insulators
3.Practical Load
a) Line Insulators

Value of
Capacitor

Value of
Resistor
()

Steady State
Output
Voltage (kV)

100k

20pF
300pF

1000pF

Remarks
(at steady
state )

6.28

Time
Required to
reach Steady
State (s)
1.48

6.353
6.3221

1.6
1.16

No Ripples
No Ripples

6.2779

1.13

No Ripples

6.2481

1.08

No Ripples

6.2425

1.183

No Ripples

6.2853

1.408

No Ripples

Heavy
Ripples
present

10000pF

250pF
75pF

20pF

b) Bushings
300pF

10k

5.7181

1.970

High Ripples

100k

6.2628

1.885

1000k

6.3473

1.780

10k

5.6990

1.302

Slightly Less
than Above
Fewer
Ripples
High Ripples

100k

6.2675

1.249

1000k

6.2968

1.181

Slightly Less
Ripples
Fewer
Ripples

Page | 26

CHAPTER-4
CASE STUDY: A 3-STAGE COCKCROFT WALTON CIRCUIT FOR A
PRACTICAL LOAD (C=20pF & R=10k)
Circuit Diagram:

PSPICE Program:
Cockcroft-Walton Circuit
V 2 0 sin(0 220 50 0 0)
R1 1 2 0.3
L1 1 0 20mH
L2 3 0 500mH
K L1 L2 0.98
R2 3 4 0.3
C1 4 5 500u
C2 5 6 500u
C3 6 7 500u
C4 8 9 500u
C5 9 10 500u
C6 10 0 500u
D1 0 5 DMOD
D2 5 10 DMOD
D3 10 6 DMOD
D4 6 9 DMOD
D5 9 7 DMOD
D6 7 8 DMOD
C7 8 0 20p
R3 8 0 10k
.MODEL DMOD D(Is=2.2e-15 BV=8000)
.tran 1s 5s uic
.probe V(1) V(3,0) V(8,0)
.end

Page | 27

OUTPUT:
Terminal Voltage Profile:
6.0KV

4.0KV

2.0KV

0V
0s

0.5s

1.0s

1.5s

2.0s

2.5s

3.0s

3.5s

4.0s

4.5s

5.0s

3.0s

3.5s

4.0s

4.5s

5.0s

V(8,0)
Time

v(8,0)= terminal voltage

Load Current Profile:
600mA

400mA

200mA

0A
0s

0.5s

1.0s

1.5s

2.0s

2.5s

I(R3)
Time

i(R3)=load current
Page | 28

Voltage waveform pattern in the smoothing capacitors

From the circuit diagram of the 3-stage Cockcroft Walton circuit we see that
C1, C2, C3 are oscillating capacitors &
C4, C5, C6 are smoothing capacitors.
The Voltage waveform of the Smoothing Capacitors C4, C5, C6 are v(C4), v(C5), v(C6) for 8input cycles (0-160ms) and input is v(3,0)

2.0KV

V(C6)

V(C5)
V(C4)
0V

Input Voltage

-2.0KV
0s
V(3,0)

20ms
V(C4) V(C5)

40ms

60ms

80ms

100ms

120ms

140ms

160ms

V(C6)
Time

The Voltage Waveform of the Smoothing Capacitors C4, C5, C6 is v(C4), v(C5), v(C6) at
steady state:
2.0KV

1.5KV

1.0KV

0.5KV

0V
0s
V(C4)

0.2s
V(C5) V(C6)

0.4s

0.6s

0.8s

1.0s

1.2s

1.4s

1.6s

1.8s

2.0s

Time

Page | 29

Voltage waveform pattern in the oscillating capacitors

The Voltage Waveform across the Oscillating Capacitors C1, C2, C3 are v(5,4), v(6,5), V
v(7,6) for 8-input cycles (0-160ms) and input is v(3,0)
2.0KV

1.0KV

0V

-1.0KV

-2.0KV
0s
V(3,0)

20ms
V(5,4) V(6,5)

40ms
V(7,6)

60ms

80ms

100ms

120ms

140ms

160ms

Time

The Voltage Waveform of the Oscillating Capacitors C1, C2, C3 is v(5,4), v(6,5), v(7,6) at
steady state :
2.0KV

1.5KV

1.0KV

0.5KV

0V
0s
V(5,4)

0.2s
V(6,5)

0.4s

0.6s

0.8s

1.0s

1.2s

1.4s

1.6s

1.8s

2.0s

V(7,6)
Time

Page | 30

Observations:
Ripples
Input Voltage
Stepped Up Voltage at Transformer secondary
Theoretical Value of Steady State output Voltage
Practical Value of Steady State output Voltage
% Error
Time Constant
Time required reaching steady state
Steady State Current

: Heavy Ripples Present

: 220V
: 1.1kV
: 6.6kV
: 5.7181kV
:

=='@>?.
==

*100=13.36%

: 1.970 ms
: 165.9 ms
: 570.4mA

Page | 31

Calculation of various factors:

1. Calculation of Output Voltage:
We know that the output voltage of the Cockcroft Walton circuit is given by:
Vout= 2nEp- Vdrop
Where,
o Ep is the input to the Cockcroft Walton Circuit (In this case the secondary of the
transformer),
o n is the number of stages,
o Vdrop is the Voltage drop under load.
Vdrop is given by,
Vdrop=

I load
4n 3 + 3n 2 n
6 fC

Here,
Practical Value of the output voltage is:
Vout(practical)=5.7181kV
Theoretical Calculations:
n=3,
Ep=1.1kV,
C=500uF
f=50Hz
Iload=570.4mA
So,
Vdrop= 882.22 V
Eout(theoretical)=6600-882.22=5717.78V or, 5.7178kV
%Error=

(from Vdrop Equation)

5.7178 5.7181
* 100 = 0.00525%
5.7178

2. Calculation of Ripple Voltage (V):

The expression of the ripple voltage is given by,
V=

In(n + 1)
4 fC

Page | 32

Here,
I=570.4mA
n=3
f=50Hz
C=500F
So, theoretical value of the ripple voltage is:
Vtheoretical =68.45V
Practical Value of the ripple voltage:
For this the output voltage waveform in the steady state is to be considered.
The output voltage waveform at steady state is given by:

5.875KV
(2.1071,5.7743K)

5.750KV

5.625KV

(2.1226,5.6422K)
5.536KV
2.008s
V(8,0)

2.050s

2.100s

2.150s

2.200s

2.250s

2.300s

Time

v(8,0)= steady state voltage profile

From the output waveform:

We see that,
Value of the voltage at crest Vcrest= 5.7743kV
Value of the voltage at trough Vtrough= 5.6422kV
The ripple voltage is given by:
Page | 33

V=

5.7743 5.6422
=0.06605kV=66.05V
2

So, Vpractical=66.05V
%Error=

68.45 66.05
*100=3.5%
68.45

CONCLUSIONS:
 The PSPICE schematic is limited for the output voltage of the range up to 300V only,
after that the output is not satisfactory due to the low breakdown voltage of the diodes
used.
 For getting the output voltage greater than the 300V rather in kVs the PSPICE
ORCAD is used where the breakdown voltage can be defined as per requirements.
 At no load condition the output does not match with the prescribed theoretical output
because of the voltage drops in the diodes.
 More is the output voltage the steady state error decreases due to negligible effect of
the diode voltage drops with respect to the output voltage.
 Ripples are present (at steady state) for the resistive load and the capacitive load (with
less load resistance) due to less time constant and so lesser time required for charging
and discharging of the capacitors.
 No load voltage is more than the terminal voltage on load due to voltage drop across
the load.
 The steady state error increases slightly with number of stages due to increase in
number of diodes and hence voltage drops across them.
 The time constant increases with the number of stages as the number of capacitor in
parallel increases and hence the ripples decreases.
 As the load capacitance value increases the ripples decrease and the time required to
reach the steady state also decrease.
 When load capacitance value is kept fixed with the resistance varied the ripples
increase with decrease in resistance value, the steady state voltage increase with the
increase in resistance and time required to reach steady state reduces with increase in
resistance.
 In the case study the steady state error in the output voltage profile is very low and
accounts mainly for the voltage drops across the diodes.
 In the case study the error in the ripple factor calculation is mainly due to the fact that
the transformer output voltage is not perfectly sinusoidal.
 From the voltage profile of the oscillating and the smoothing capacitors we see that
all the capacitors are charged to 2*Emax except C1 which is an oscillating capacitor.
Page | 34

REFERENCES
High Voltage Engineering by C.L. Wadhwa
High Voltage Engineering by M.S. Naidu, V. Kamaraju
www.wikipedia.com
www.blazelabs.com
www.google.com

Page | 35