Proceeding of the 2014 IEEE Students' Technology Symposium

FPGA Based Implementation & Power

Analysis of Parameterized Walsh Sequences
Gaurav Purohit1, V.K Chaubey2

Kota Solomon Raju3, Divya Vyas

Department of EEE
BITS- Pilani, Pilani Campus
Pilani, India
gp.bits@ gmail.com1, vkcster@gmail.com2
Abstract This paper presents FPGA based implementation of
the theory which replaces a general Sine and cosine function by
set of orthogonal functions i.e. Walsh function. The paper further
compares Parameterized Serial In Serial Out architectures
based on classical counter approach. The investigation consider
FPGA parameters like Area, Speed and Power and shows
that using Gray-increment based architecture instead of Binary
saves 6mW of power per symbol (64 Walsh chips per symbol)
with 30% reduction in area. The design is implemented in VHDL
code, simulated in MATLAB System Generator environment and
validated with MATLAB Simulink Model. The design targeted
Xilinx Virtex-5 XC5VLX50T-1ff1136 FPGA device for the
implementation and comparison. The design found their uses in
many popular applications like Software Define Radio (SDR)
including multiuser communications such as CDMA, WCDMA,
VLSI testing, pattern recognition as well as image and signal
processing.
Keywords-CDMA, Rademacher function, SDR,
Generator, WCDMA, Walsh sequences, Walsh function.

I.

System

Digital Systems Group

CSIR - CEERI Pilani
Pilani, India
solomon@ceeri.ernet.in3
Fourier transforms, audio and video signal processing,
filtering and multiplexing have been widely reported in
literature [3]-[4] specially for multimode radio SDR
(Software Defined Radio) and Reconfigurable Radio as in
CDMA standard, where the individual channels are
distinguished from each other by mutual orthogonality of
signals. It is therefore, necessary to create mutually
orthogonal sequences, through which information is
transmitted by various channels spread. The Table I
shows the application of Walsh code in the CDMA
Reverse channels [5].
This paper presents a customized, elegant, and concise
solution for building hazard free, noiseless 64orthogonal set using Rademacher function. Furthermore
presents the comparison is based on three main parameter
viz. power, speed and area for two prominent SISO
architecture i.e. using classical binary counter and Gray
counter.
Table I
Walsh functions for reverse CDMA channel

INTRODUCTION

WALSH functions are a complete set of periodic twovalued {+1,-1} orthogonal functions that can be used
in somewhat the same manner as Fourier functions. J.L
Walsh in his article A closed set of normal orthogonal
functions of 1923 defined orthogonal functions, which is
closed in a standard interval (0, 1) and every function
takes the values {+1,-1} except the final number of discrete
points, which is zero [1]. Walshs definition seems more
appealing to engineers because of the analogy with
trigonometric functions in terms of ordering the functions
according to the increasing average number of zero
crossings in a unit interval, called sequency. However,
they have aroused great interest in recent years in wireless
communication as they are used as channelization code in
many standards such as CDMA2000 (Code Division
Multiple Access), WCDMA (Wideband Code Division
Multiple Access) [2].
They are used for the elimination or the reduction of
interference within the users and within the channels and
furthermore for their identification. They have vast
applications in the field of communications, fast

The paper is structured as follows: Section 2 illustrates

about generation of the Walsh sequence and previous works
to provide appropriate background. In Section 3, describes
FPGA implementation of SISO architectures. In Section 4,
we investigate and evaluate our results by comparing the
two implemented architectures.

Sponsors: CSIR MHRD, DELHI SRF Fellowship

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Proceeding of the 2014 IEEE Students' Technology Symposium

II.

WALSH FUNCTION GENERATORS

There are two different kinds of Walsh function generators

are in use the first generates only one Walsh function at a
time out of a large possible number. Whereas the second
method generates a complete set of Walsh functions
simultaneously. Our implementations generate only one
Walsh function at a time and are shown with two different
architectures based on Rademacher function. The difference is
that first architecture uses classical binary counter and gray
index whereas other by gray counter and gray index. Let us
see how Rademacher functions are used for generating Walsh
sequence [6]. Rademacher functions of order N are set of
1+log2N orthogonal functions consisting of N=2^k
rectangular pulses where, k is integer. These pulses assume
alternately the values +1 and -1 in an interval of (0, T). The
Rademacher functions of order N are defined by the relation,
Rn (t) = sgn (sin 2 n t),

t (T, 0), n = 1, 2 ... K

(1)

Where R0 (t) = 1,
-1 for x < 0
Sgn(x) =

0 for x = 0
(2)

+1 for x > 0

is an iterative process. It is not suitable for generating Walsh

functions since errors in timing will accumulate for higher
order functions. Peterson has suggested a Walsh function
generator based on the symmetry properties [8]. Most other
generators use products of Rademacher functions. They
generate first the set of Rademacher functions by means of
binary counters. The first such generator was described by
Harmuth [9]. It uses half-adders to perform the
multiplication of the Rademacher functions. Lebert [10]
constructed another interesting type that uses the trailing
edges of selected Rademacher functions to set and reset a
flip-flop to generate a single Walsh function. A similar
generator that uses gates instead of differentiators was
described by Yuen [11]. Another one proposed by Nawrath
[12] uses multiplexers. Regarding implementation a
prototype Walsh Function Generator (WFG) for a NASA
satellite called the ESTAR (Electronically Scanned
Thinned Array Radiometer) has been designed and tested
by William A. Chren using a single Xilinx XC302OPC6850 FPGA, another by Yukihiro and Tsutomu but their
FPGA implementations show their feasibility up to n= 14
[13]. One parallel method is shown by G. Evans for CDMA
IS-95 but that method is having ASIC Flow [14][15]. Our
implementation uses conventional approach but shows
complete FPGA flow with comparative analysis of power,
area and speed which give an easiest approach to select
between two conventional available methods.

After generating Rademacher functions these are converted

to Rademacher sequences. This operation yields conversion
into binary logic (+10 & -11). The Walsh sequences
are generated as a modulo-2 sum of Rademacher functions.
This process is based on Walsh function index sequence
conversion into the Gray code. Index sequence of Walsh
function is simply Walsh function index in binary code
Xi = (xi1, xi2xiK) The Gray code Gi = (gi1, gi2 giK) is
created as follows:
gi1 = xi1
gik = xiJ-1 xiJ

J = 2,3...K

(3)
(4)

The Walsh sequences are exactly formed as the modulo-2

sum of R0 and the other Rademacher sequences {Rj} that are
not associated with zero values of Gi. This can be formulated
as follows:
Wi = R0(t) [ R1(t) if gi1 = 1 ] [R2(t) if gi2 = 1]
Wi = R0

RK +1 j

(5)
(6)

j:g ij =1

Walsh functions can be defined in terms of a difference

equation, by their symmetry properties or by products of
Rademacher functions [7]. The difference equation method

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Figure 1 SISO architecture based on classical counter approach

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Proceeding of the 2014 IEEE Students' Technology Symposium

III.

FPGA IMPLEMENTATION

For implementation of SISO architecture we choose black

box methodology based on Xilinx System generator in
MATLAB Simulink environment. Using such method we
need not bother about the test bench generation because
using MATLAB we can generate them directly. Secondly for
such we need our implementation in VHDL code and then
using black box bind the VHDL code in it. Use Gateway in
and out to convert MATLAB based signal to Xilinx based
precision. Then using Modelsim which is a tool given for
such environment from Mentor Graphics through which we
can check the timing closure and simulation results for both
pre and post synthesis. The fig.1 shows the first architecture
and in the second one we just modified the binary counter
to gray counter and gray index to binary index. With this

also we produced the same result as shown in Figs. 3-4.

MATLAB Simulink also provides copyright Walsh
generator. We used that for our validation. The unit Delay
in MATLAB model is needed because reset is needed for
VHDL design whereas no such is required for MATLAB
based Walsh Generator so for matching we required such. It
can be seen from Fig. 3 that all the models are perfectly
matched waveform. Fig.4 shows that the difference in
counter waveform, it shows binary linear rises whereas gray
is nonlinear. Further an important conclusion can be drawn
from Fig. 5 i.e. Walsh from binary shows glitches whereas
Walsh from gray is Noiseless, Hazard free and smooth. So
our next section will approach a Noisy Boy VS Gentleman
Comparison on three parameter i.e. Speed, Power and area.

Figure 2 Parameterized Walsh Generation using Xilinx System Generator

Figure 3 WALSH Generation validation using MATLAB Scope [Two arch. + MATLAB based BLOCK with index = 56 (as Data in)]

Figure 4 Counter Outputs (showing linear increment in Binary counter and Non Linear in Gray counter for N=6)

Figure 5 ModelSim based Functional Analysis (N=6) (showing Noisy boy and Gentleman outputs from two arch.)
Glitches

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Proceeding of the 2014 IEEE Students' Technology Symposium

IV.

V.

RESULTS

The implementation shows that Noisy boy i.e. first

architecture as shown in Fig.1 are having glitches at
many transition at output waveform shown in Fig. 5
whereas gentleman i.e. our second architecture with gray
counter is hazard free and noiseless because of its single
transition per clock. Further investigation related to area is
shown in table 2 shows that Architecture 2 has 30% less area
consumption compared to first. Results are cross verified
with system generator based resource estimator. [16 ]
Table II
Estimated device utilization for the Two Architecture

S.No.

Parameter

1
2
3
4

Slice utilization
Flip Flops
Look Up Table
IOS

5
12
14
14

5
7
10
14

Both the architecture runs with maximum frequency 600

MHz (synthesized) with corresponding minimum delay 1.667
ns. The power analysis has been done with minimum
frequency 100 MHz i.e. time 10 ns as well as for maximum
frequency i.e. 600 MHz and time 1.667 ns. The table 3 & 4
will report the power consumption of one symbol per 65
clocks or can say 64 bit output and one for reset at
beginning. The investigation shows Architecture first (noisy
boy) consumes 6mW more power for the same operation
then the architecture second (Gentleman).
Table III
Estimated power for the Two Architecture AT 100 MHz

S.No.

Parameter

1
2
3
4
5

Clock
Logic
Signal
IOS
Device leakage

Total

NOISY BOY
Architecture 1
(In watts)

0.003
0.00013
0.00020
0.018
0.448
0.470

GENTLEMAN
Architecture 2
(In watts)

0.003
0.00048
0.00069
0.012
0.448
0.464

Table IV
Estimated power for the Two Architecture AT 600 MHz

S.No.

Parameter

1
2
3

Clock
Logic
Signal

0.010
0.00025
0.00040

0.009
0.00078
0.00129

4
5

IOS
Device leakage

0.062
0.448
0.521

0.032
0.448
0.490

Total

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NOISY BOY
Architecture 1
(In watts)

The paper gives a finest look over FPGA based

implementation of Walsh Sequences i.e. 64-ary orthogonal
codes using Xilinx System Generator with MATLAB
environment. The simulation of VHDL code is validated
with MATLAB Simulink copyright block. Furthermore
power, area and speed analysis is represented which are
required for FPGA based development. The architecture
first i.e. noisy boy give glitches at output waveform w.r.t
gentleman i.e. second Architecture which give us a best
results without any tradeoff in frequency of operation.
VI.

NOISY BOY GENTLEMAN

Architecture 1 Architecture 2

GENTLEMAN
Architecture 2
(In watts)

CONCLUSIONS

ACKNOWLEDGMENT

This paper is produced with the CSIR-SRF, MHRD

Fellowship. The author would like to thank Mrs. Anu Gupta,
HOD Department of EEE, BITS-Pilani and CSIR- CEERI for
their support.
VII. REFERENCES
[1]
[2]
[3]

[4]
[5]

[6]
[7]
[8]

[9]

[10]

[11]
[12]

[13]

[14]
[15]

[16]

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