Third HW Assignment for ECEN 2104 (Digital Logic and Computer Organization)

1 Multiple Choice Questions

(i) Which logic gate has the highest speed?
(a) DTL (b)
RTL
(c) ECL
(d) TTL
(ii) A carry look ahead adder is frequently used because it is
(a) Is faster
(b) is more accurate
(c) uses fewer gates
(d) costs less
(iii) Micro instructions are kept in
(a) Main memory (b) Control Memory (c) Cache memory (d) Secondary memory
(iv)Two 4-bit 2s complements of binary numbers 1011 and 0110 are added. Then the result will
be
(a) 1111 (b) 0010
(c) 1101
(d)0001
(v)Principal of locality justifies the use of
(a) DMA (b) Paging
(c) Cache memory
(d) Polling
(vi)Hexadecimal equivalent of the binary no. 10111010001111 is
(a) 2E8F (b) 1E7A (c) 2F3B
(d)1E9D
(vii) If (24 + 17) = 40 then the base of the numbers is
(a) 5 (b) 6 (c) 9
(d) 11
(viii) Minimum no of NAND gates required to implement the X-OR gate for two variables is
(a) 5 (b) 7 (c)4
(d)3
(viii) In which addressing mode the effective address of the operand is generated by adding a
constant value to the contents of the register.
(a) Indexed (b) Indirect (c) Register (d) Absolute
(ix)The number of flip-flops required to design a MOD-6 counter is
(a) 3 (b) 5 (c) 4 (d) 6
(x) What is the hexadecimal equivalent of the Octal number (775737264.75)
(a) FBBF.F4 (b) 7F867FC.E3 (c) 7F7BEB4.F4
(d) 65DE7.74
(xi) What is Gray equivalent of the binary no 1101
(a) 1101 (b) 1011 (c) 0111 (d) 1986
(x) Which Flip Flop may act as a buffer
(a) D
(b) S R
(c) T (d) J K
(xi) The value of bases X for which (216)x=(52) 8 is
(a) 08 (b) 10 (c) 16 (d) 4
(xii) Normalized representation of 0.00101 x 22 in IEEE format is
(a) 0.00101 x 2-2 (b) 1.01 x 2-1 (c) 1.01 x 21
(d) 10.1 x 2-3
(xiii) A 3 bit MOD-8 ripple counter uses JK flip-flops. If the propagation delay of each flip-flop
is 50 nS then the minimum input clock frequency will be
(a) 5 MHz
(b) 6.6 MHz
(c) 8.67 MHz
(d) 250Mhz
(xiv) The equivalent decimal no. of BCD no. (100100111000.0111) is
(a)938.7
(b)125.6
(c) 256.9
(d) 923.7
(xv) The capacity of a memory unit is defined by the number of words multiplied by the number
of bits per word. How many separate address and data lines are needed for a memory 4K x 16?
(a) 10 addresses, 16 data lines, (b) 11 addresses, 8 data lines, (c) 12 addresses, 16 data lines
(d) 12 addresses, 12 data lines
(xvi) The number of transistor in a static CMOS RAM cell is
(a) 1
(b) 4
(c) 6
(d) 2
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(xvii) From The dual of the Boolean theorem A(B+C)=AB + AC one can deduce
(a) A + BC= (A+B)(A+C)
(b) ABC= (A+B)(A+C)
(c) AB+AC= (A+B)(A+C)
(d) none of these.
(xviii)The number of transistor in a dynamic CMOS RAM cell is
(a) 1
(b) 4
(c) 6
(d) 2
(xix) WINDOWS 8 can be classified under
(a) RTOS, (b) GPOS (c) CMOS (d) BDOS
(xx) Computer Organization is concerned with the ways ---------- components operate. Computer
Architecture is concerned with -------------- and ------------- of the computer as seen by the user.
(a) software, structure, behaviour (b) hardware, software, firmware (b) software, structure,
behaviour (d) hardware, structure, behaviour
2.
2a) Simplify using K-map in SOP form
f(A,B,C,D) = (1,2,4,5,9,10) + d(6,7,8,13) (d=dont care)
2b) Design a Full Adder and Subtractor module using two Half Adders and appropriate
gates
2c) Design a J K Master slave flip flop using two clocked R S Flip flop
3a) Simplify the following function using K-map and realize the simplified expression
using NAND gates only.
F(A,B,C,D)=(1,2,3,5,6,11,12) + d(7,8,10,14)
3b) Design a 3-to-8 decoder using logic gates.
3c) Implement a full adder and a full sub tractor circuit using a 3-to-8 decoder
4a) Design the following function using appropriate Multiplexer
F(A,B,C) = S(1,3 5,7)
4b) Design a four input (D3-D0) priority encoder having priority in order of sequence.
Input D0 having the lowest, and D3 the highest priority.
4c) Design a Full Adder with a Decoder and appropriate gates
5a) Draw a BCD adder circuit to add to BCD numbers maximum up to 9. The output of
this adder circuit should be in BCD.
5b) Design a 4 : 1 multiplexer using logic gates.
5c) Implement the following function using a 4:1 MUX.
F (A, B, C) = (1,3,5,6).
6a) What is Von Neumann architecture? What is Von Neumann bottleneck? What is
Harvard Architecture? Explain briefly using a block diagram.
6b) What is an instruction cycle?
6c) An instruction is stored at location 302 with its address field at location 303. The
address field has a value 405. A processor register R1 contains the number 206 at the
beginning. Evaluate the effective address if the addressing mode is i) direct, ii) relative,
iii) register indirect, iv) index with R1 as the index register

7a)For the function f(w,x,y,z)=(0,1,2,3,4,6,7,8,9,11,15) find out all prime implicants

and indicate which are essential.
7b) Design and explain a 16:1 multiplexer using only 4:1 multiplexer.
7c) Design a 2- bit binary magnitude comparator using a decoder of suitable size and
other gates.
8a) Evaluate the following expression in a zero address, and one address machine
Y = (A B) / (C + D*E)
8b) Show a Serial adder and compare its relative advantages and disadvantages with
respect to a Ripple carry adder.
8c) Show how a 4-bit Carry look ahead adder performs faster than an 4-bit ripple carry
adder?
9a)What is a ROM and RAM? What is the basic difference between EPROM and
EEROM?
ABC D
9b) A ROM is used to implement the Boolean function: F 1(A,B,C,D)=ABCD +
A B C
F2(A,B,C,D)=(A+B)( + + )
F3(A,B,C,D)= (13,15)
What is the minimum size of ROM required? Determine the data in each location of the
ROM.
10a)Distinguish between SRAM and DRAM. Explain their reading and writing operation
10b) What is cache mapping? Explain direct mapping for 256 x 8 Ram and 64 x8 Cache
memory. Briefly explain the functionality of an associative memory?
11a) Explain the circuit operation of master slave J-K flip-flop using all NAND gates.
11b) Convert a S-R flip-flop to J-K flip-flop.
12a) What is a virtual memory? Why is it called virtual? What are the advantages of a
virtual memory?
12b) What is a page? What is demand paging? What is a page fault?
12c) What are the various page replacement policies?
13a) Design a 4 bit Johnson counter using D flip-flop and explain its operation.
13b) Design a synchronous 3 bit up and down counter using J-K flip-flops. Consider a
conditional input x =0 for up counter and x=1 for down counter.
14a) Compare the pros and cons of RISC and CISC based architecture.
14b) What are the differences between a hardwired control unit and a microprogrammed control unit.
14c) The content of the top of a memory stack is 5320. The content of the stack pointer
SP is 3560. A two word call subroutine instruction is located in memory at address 1120
followed by the address field of 6720 at location 1121. What are the content of PC, SP,
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and the top of the stack?, A) Before the call instruction is fetched from memory?, B)
After the call instruction is executed?, C) After the return from subroutine?
15a) Draw a detailed diagram of a small DRAM which has 16 words 4 bits /word.
Show the configuration of dynamic cells used and the detailed layout of cells in rows and
columns.
15b) What are the difference between a static memory cell and a dynamic memory cell?
Which one of these cells can be non- destructively read out?
16(a) Why DMA based I/O is better than other I/O based technique
16(b) What is the difference between isolated I/O and memory mapped I/O?
16(c) Explain DMA data transfer between memory and terminal peripheral.
16(d) What is the difference between vectored and non vectored interrupt?
17Write short notes on:
a) Ring counter.
b) Serial input parallel output shift register