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IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 32, NO. 2, MAY 2009

Microcantilever Probe Cards With Silicon and

Nickel Composite Micromachining Technique
for Wafer-Level Burn-In Testing
Fei Wang, Member, IEEE, Xinxin Li, and Songlin Feng

AbstractA new type of probe card is designed and fabricated

for wafer-level integrated circuit (IC) testing. Using micromachining technology, roughly 18 000 cantilever-tip probes can be
integrated in one 4-in wafer, with a minimum pitch of 90 m for
adjacent probing tips. The probe card employs a silicon-and-metal
composite structure, in which the bulk-micromachined silicon cantilever arrays provide uniform probing height and good planarity
for the tips, as well as, the electroplated nickel probing tips feature
high hardness and satisfactory electric contact with the pads to
be tested. Electroplated nickel is used to simultaneously create
the probing tips and the through-wafer interconnects (TWIs),
which can transfer the testing signals from the dies-under-test
(at the wafer bottom side) to the input/output (I/O) interface (on
the front side). The probe card makes full use of the excellent
mechanical properties of single-crystal silicon and satisfactory
electrical properties of electroplated nickel, with the TWIs facilitating the following solder-bump flip-chip packaging. The
fabricated cantilever-tip is able to withstand a contact force of 50
mN, corresponding to a tip displacement of 33 m. The measured
contact resistances on metal thin-film specimens (Al, Cu, and Au)
are all below 1 , whereas the maximum current leakage across
two adjacent tips is 90 pA at 5 V voltage.

Index TermsMicromachining, Ni electroplating, probe card,

silicon cantilever, wafer-level integrated circuit (IC) testing.

I. INTRODUCTION

OR decades, integrated circuit (IC) researchers have

achieved the continuous increase in transistor density and
signal speed. In addition, along with the rapid development
of microelectronic packaging technologies such as multichip
module (MCM), system-on-chip (SOC), system-in-package
(SIP), and system-on-package (SOP), the electronic products
will eventually become convergent systems of computation,
communication, consumer, and biomedical functions [1]. Accordingly, the microelectronics testing technology is facing great
Manuscript received March 19, 2007; revised February 03, 2008; October 21,
2008. First published May 08, 2009; current version published May 28, 2009.
This work was supported in part by the NSFC Project under Contract 60725414
and in part by the Chinese 973 Program (2006CB300405). The work of X. Li
and S. Feng was supported by the NSFC Project under Contact 60721004. This
work was recommended for publication by Associate Editor Y. C. Lee upon
evaluation of the reviewers comments.
The authors are with the State Key Laboratory of Transducer Technology,
Shanghai Institute of Microsystem and Information Technology, Chinese
Academy of Sciences, Shanghai 200050, China, and also with the Graduate
University of Chinese Academy of Sciences, Shanghai 200050, China (e-mail:
xxli@mail.sim.ac.cn).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TADVP.2009.2013636

challenges, and wafer level burn-in test becomes particularly

important for low-cost mass production of known-good-die
(KGD). A wafer-level testing probe card is utilized, as the
principal interface for signal routing to the automatic test
equipment (ATE), to pass or fail the dies under test (DUT).
Industry is severely suffering from the conventional probe
card, in which tens to hundreds of cantilever needles are manually mounted onto an epoxy ring. Continually increasing paddensity and narrowing pad-pitch would break the limit of the
manual assembly ability in the near future. Cross-talk and parasite inductance also make the epoxy probe cards difficult for
high-speed testing. Additionally, the conventional metal needles tend to be deformed under many times touchdowns and
the calibration process is time consuming. To solve these problems, several attempts have been made to seek a substitute based
on advanced microelectromechanical systems (MEMS) technologies [2][9]. Compared with the conventional techniques,
MEMS technology is in favor of enhancing the tip uniformity
and fabricating high density probe arrays at a lower cost. Furthermore, MEMS probe cards are promising for high-speed ICs.
The membrane probe card and the thermally actuated microprobes were sequentially developed that represented the earliest stage of MEMS probe cards [2], [3]. Both of them gained
some advantages over manually assembled probe cards, such as
finer tip pitch by lithography and lower cost with batch fabrication. However, they also had some limitations. For the former,
an extra gas pressure system should be added, which increases
the complexity of the ATE. Besides, the probes at different positions were difficult to supply uniform probing forces since
the probe deflection was nonuniform across the membrane. The
latter microprobes were composed of thermally actuated microcantilevers which were hard to provide enough probing force
to break the natural oxide on the surface of the Al pads. In recent years, electroplated nickel was used as cantilever-tip probe
owing to its good electric conductive property [4], [5]. However, the residual stress in the electrodeposit tended to make the
micro-beams bend or buckle, which caused severe nonuniformity in the probing height. This nonuniformity would further
affect other performances such as probing force, contact resistance, and scrubbing depth. Some other researchers tried to use
single-crystal silicon for the whole probe structure to avoid the
stress problem [6], [7]. Unfortunately, the silicon probes suffered from the poor electric conductivity of silicon and were
difficult to form the through-wafer interconnects (TWIs).
In this paper, we present a new type of MEMS probe card,
in which highly dense and uniform nickel tips are simultaneously formed with the nickel TWIs. Both the back-to-front

1521-3323/$25.00 2009 IEEE

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and front-to-back electroplating techniques have been developed. The silicon and nickel composite structure combines the
advantages of both the silicon cantilever and the nickel TWIs
and probe tips. The silicon cantilever shows satisfactory elastic
properties before the material reaches the rupture limit. As a
complement, the nickel through-wafer interconnect (TWI) and
tip exhibit low probing resistance and uniform tip height. The
probe card is finally mounted on a printed circuit board (PCB)
by solder-bump flip-chip packaging for signal interface to ATE.
The detailed technique will be related in following sections.
II. DESIGN AND SIMULATION
During wafer-level burn-in test, the probe tips have to contact with the pads of DUT at the bottom side of the probe card,
while the testing signals have to be transferred from the bottom
side to the front side input/output (I/O) interface of the automatic test equipment (ATE). To meet this requirement, the authors previously developed a type of silicon cantilever probe
card with tip-to-pad electric feed-through by a double-sided
metal overlapping scheme and automatically isolated metal
coating technique [8], [9]. Low resistance of the feed-through
vias and high spring constant of the cantilevers were achieved.
However, the fabrication was quite complicated that did not facilitate high-yield low-cost production. In this paper, TWI of the
MEMS probe cards is introduced to achieve a probing resistance
lower than 1 . Nickel TWI and tip is used to lower the signal
routing resistance and to scratch the natural oxide on the pads
under test. In addition, silicon cantilevers are used to overcome
the plastic deformation problem of conventional metal needles.
High density and narrow pitch can be achieved by advanced silicon bulk micromachining techniques. Furthermore, the probing
tip at the free end of the cantilever will laterally slide when the
cantilever bends under a contact force. This slide can help the
probe tip to scratch the natural oxide on Al surface and make a
better contact with the tested pad.
The technology of TWI mainly comprises the feed-through
holes opening by deep reactive ion etching (DRIE) and the holes
filling by electrodeposition of metal. According to conventional
TWI fabrication techniques, however, neither of the two steps
could be easily implemented when the TWI holes occupied
the whole wafer thickness (several hundreds of microns). The
DRIE usually demanded an extraordinary high aspect ratio
(typically higher than 20:1) for high feed-through density [10],
while the TWI electrodeposition often required fussy control on
the plating parameters for void-free filling of the very deep and
narrow through-holes [11]. In present research, nickel TWIs are
formed on the relatively thinner cantilevers instead of the thick
wafer frame, as shown in Fig. 1. Therefore, the TWI structure
only demands a lower aspect ratio of DRIE (about 6:1) that can
be high-yield filled with regular electroplating technique. More
important, the electroplated nickel can be used as the TWIs and
the probing tips simultaneously when the silicon cantilevers
are finally released. Fig. 1(a) and (b) show the cross-sectional
scheme of the designed cantilever-tip probe card and the 3-D
configuration of the probe arrays, respectively. The Ti/Cu
thin-film signal lines connect the TWIs to the solder-bump for
further flip-chip packaging to a PCB for ATE I/O interface.
The novel cantilever-tip structure makes full use of both the

Fig. 1. (a) Cross-sectional scheme of the designed cantilever-tip probe card.

(b) Three-dimensional configuration of the probe arrays.

good electrical properties of the electroplated nickel and the

satisfactory mechanical properties of the single-crystal silicon.
The simultaneous formation of the TWIs and probe tips greatly
simplify the fabrication process and improve the probe uniformity, compared with the separate methods reported in [5].
Typically a contact pressure of 45 MPa is needed for the probe
tip to break the natural oxide film on the surface of the aluminum DUT pad [12]. Considering the apex area of the tip is
20 m 20 m in our design, the equivalent contact force is
about 17 mN. For practical application, an overdrive (i.e., tip
deflection) is also desired to tolerate the nonuniformity of the
tested pads within one wafer, which is with a typical value of
about 10 m. Finite element method (FEM) is used to simulate the mechanical properties of the probe card. Fig. 2 shows
the simulated stress distribution in the cantilever-tip probe using
ANSYS-9.0, with the maximum stress level as 427 MPa. The
Youngs module values of silicon cantilever and nickel tip used
for the simulation are 170 and 150 GPa, respectively. The cantilever is designed as 800 m in length, 80 m in width, and
60 m in thickness. Three types of tip-pitches, 90, 130, and
150 m, are separately designed for applications to different
DUT pad density. When a contact force of 25 mN is exerted
on the tip, the simulated tip displacement is 18.5 m, i.e., the
spring constant is designed as about 1350 N/m. The maximum
stress is located at the base of the cantilever with a simulated
value as 427 MPa, which is safely lower than the fracture limit
of single-crystal silicon [13]. The comparison among the simulation results, the theoretical calculation and the measured data
will be given in Section IV.
III. FABRICATION
The fabrication is started on a 450- m-thick (100)-oriented
n-type silicon wafer. The detailed process is sketched in Fig. 3
and described as follows.
1) Deep Cavity Etching: Firstly, 2- m-SiO is thermally
grown. After the SiO layer is patterned as etching mask,
anisotropic etching with aqueous KOH (40wt%, 60 C) is
carried out to form 300- m-deep cavities. The thermally grown

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Fig. 2. ANSYS simulated stress distribution in the cantilever-tip probe when a probing force of 25 mN is exerted at the tip.

SiO has a good selectivity of 1:250 over the (100) silicon

during the KOH etching process. The remnant 150 m of
silicon is left for the thickness of the further formed cantilevers
plus the probing height.
2) Nickel Electroplating for TWIs and Probe Tips: To simultaneously fabricate the TWIs and probe tips, two different
methods are developed in this study that are called the front-toback electroplating process and the back-to-front electroplating process, respectively. The front-to-back process approach is illustrated at the left-side column (i.e., the 2-a series) of Fig. 3, where nickel electroplating is performed from
the front side of the structure (i.e., the signal-line interconnection side) to the backside (i.e., the probe tip side). Using this
approach, chemical-mechanical polishing (CMP) can be used
to polish the probe tips to a flat plane. Herein the side-length
of the square-shaped cross section of the probe tip is normally
larger than 20 m to secure a high-yield of fabrication. In contrast, illustrated at the right-side column (i.e., the 2-b series) of
Fig. 3, the tip size can be less than 10 m for the back-to-front
process, since KOH etching can be used to form the electroplating molds for the tips. In this case, the nickel electroplating
from the backside to the front side is a little bit tricky since that
a dummy wafer is needed to provide the seed layer for electroplating.
Firstly, we describe the detailed steps of the front-to-back
process approach that are denoted as (2-a) in Fig. 3.
(2-a1): The SiO at the backside is patterned. Then,
the TWI holes for nickel electroplating are formed by

ICP-DRIE (inductively coupled plasma deep reactive ion

etching). The square-shaped cross section of the via hole
is with the side-length as 20 m. The holes are etched
through the 150- m-thick remnant silicon layer, by using
the time multiplexed etching cycles (SF ) and passivating
cycles (C F ) [14].
(2-a2): After the existing SiO removed, a new 2- m-thick
SiO layer is thermally grown for electric isolation between the silicon substrate and the nickel probes to be electroplated.
(2-a3): A 1- m-thick Ti/Cu layer is sputtered from the
front side. The Cu film serves as both the signal lines and
the seed layer for electroplating at the holes. The 500-thick Ti is predeposited beneath the Cu layer to improve
the adhesion between Cu and the substrate.
(2-a4): Thanks to the Cu sputtered at the vicinities of the
through-wafer holes, the feed-through holes can be firstly
sealed by nickel electroplating, with a patterned photoresist layer as mask. When the entire front side is covered
with the photoresist, the holes can be completely filled by
the front-to-back nickel electroplating. To achieve high
quality nickel plating, a sulphamate solution is used with
periodic reverse plating during the process [15]. The electroplating solution is mainly composed of nickel sulfamate (Ni(SO NH ) 4H O, 500 g/L), boric acid (H BO ,
40 g/L), nickel chloride (NiCl 6H O, 10 g/L), as well as
some addictives including butynediol and saccharin. The
pH value and the temperature of the solution are controlled

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Fig. 3. Fabrication processes of the MEMS probe cards. Two different nickel
electroplating methods have been developed. The left column shows the frontto-back plating process steps, and the right column shows the back-to-front
ones. An inset SEM image shows the Sn/Ag solder-bump after re-flowing.

as 4.0 C and 40 C, respectively. Fig. 4(a) shows the

cross-sectional SEM image of the electroplated TWI and
probe tip, while the topside view is shown in Fig. 4(b).
(2-a5): Chemical-mechanical polishing (CMP) is used to
polish the backside of the wafer, i.e., the probe tips are
tuned with the same probing height. After that, Sn/Ag
solder bumps for further flip-chip packaging are electroplated with a 30- m-thick photoresist layer (AZ-9260
from Clariant) from the front side.
Then, the Ti/Cu layer is patterned to form the signal lines
connecting the nickel TWIs and the Sn/Ag solder bumps. For
patterning the front side with deep cavities, a photoresist layer
spray coating technique is used with an EVG101 system (EV
Group, Austria). A normal contact aligner can be used for the
pattern exposure across the deep cavities, since the minimum
line width of 60 m for the Ti/Cu signal lines is not critical.
Due to the 300- m gap between the mask and the photoresist
layer at the bottom of the cavities, diffraction effect will cause
a loss of patterning resolution, which can be estimated by the
equation of
(1)
is the critical dimension that can be formed by
Herein,
a shadow printing. It can also be considered as the estimated
shrink in the signal-line width. is the wavelength of the exposure light and (300 m) is the gap between the mask and
the bottom of the cavity [16]. In our experiment, (365 nm) is
used in a Karlsuss MA6 double-side aligned exposer. Thus, the

Fig. 4. (a) Cross-sectional view of the electroplated TWI and probe tip by using
the front-to-back method. (b) Topside view of the nickel sealed electrically
connected to the Cu signal line.

width of the Ti/Cu signal line is expected to suffer a shrinkage

of 11 m, which has been taken into account when the pattern
dimensions of the mask are designed.
After the front-to-back approach described above, now we
turn to the back-to-front processes that are denoted as (2-b)
in Fig. 3 and detailed as follows.
(2-b1): After the remained SiO is removed with wet HF,
another layer of SiO is thermally grown and patterned
at the bottom of the cavity. KOH etching is performed to
shape the convex pyramids that will serve as the electroplating molds to fabricate the probe-tips.
(2-b2): The feed-through via holes for nickel electroplating are formed with the time multiplexed ICP-DRIE.
The flow rates of SF and C F are well balanced to keep
the pyramid-tip shape not changed during the etching
process [17]. Fig. 5 shows the profile of a hole formed
with the ICP-DRIE process. The shape of the concave
pyramid-tip is well preserved.
(2-b3): After the residual SiO is removed with wet
HF, a new layer of 2- m-thick SiO is thermally
grown. A dummy silicon wafer is sputtered with Cr/Cu
(500 /1500 ) seed layer and then attached at the back
side of the device wafer by AZ-4620 photoresist layer
(from Clariant). With the device wafer as hard mask,
the photoresist in the holes can be developed after light

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Fig. 5. Profile of a hole etched by the modified ICP-DRIE process, which can
keep the pyramid shape of the tip not changed.

Fig. 7. (a) Digital picture of the fabricated wafer containing 44 MEMS probe
cards. (b) Close-up view from the topside of the probe arrays.

Fig. 6. (a) Digital picture of the fabricated prototype probe card with the solderbump flip-chip packaged to a PCB. (b) Enlarged view of the probe card packaged
on the PCB.

exposing the wafers from the front side. This process step
is clearly shown in the close-up inset of Fig. 3 (2-b3).
(2-b4) The holes are filled back-to-front with electroplated
nickel. The nickel sulphamate bath and electroplating
conditions are the same as those in the above-mentioned
front-to-back processes (see the step of 2-a4).

(2-b5) After the nickel TWIs and tips are back-to-front

formed, Ti/Cu layer is sputtered and Sn/Ag solder bumps
are electroplated for further solder bump packaging. Then,
the Ti/Cu film is patterned by the above-mentioned photoresist direct spray-coating technique (see the step of
2-a5) to form the signal lines.
3) Silicon Cantilever Release: When all the exposed SiO
at the backside is stripped, ICP-DRIE is processed twice to
define and release the silicon cantilevers, respectively, leaving
the nickel probe tips protruding at the cantilever ends. With
2.3 m-thick photoresist patterned as etching mask, the silicon
cantilevers are defined and etched to the defined thickness of
60 m by using the ICP-DRIE process. Then, the whole silicon surface is maskless etched during the second ICP-DRIE
process step. When the remnant 150 m of silicon is etched
through, the silicon cantilevers are finally released. After reflowing the Sn/Ag solder bumps, the probe-card chips are diced
and flip-chip packaged to PCB boards, as is shown in Fig. 6.
The reflow process is performed with a five-zone reflow oven
(Falcon 8500). All the five reflow zones are in N atmosphere.
The temperature of different zones is sequentially set as 100 C,
150 C, 220 C, 260 C, and 80 C. An inset SEM image in
Fig. 3 shows the Sn/Ag solder-bump after relowing.
The photograph in Fig. 7(a) shows the fabricated 4-in silicon wafer comprising 44 probe-card chips, with the close-up
front side view of one probe card shown in the micrograph of
Fig. 7(b). Each MEMS probe card is composed of 392 cantilever-tip probes for wafer-level testing DUT, of which the pad
layout is provided by a customer. The SEM image in Fig. 8(a)
shows the backside view of the fabricated probe arrays, and

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Fig. 9. Ti/Cu signal lines from the TWIs at the bottom of the 300-m-deep
cavity to the topside of the chip frame. The interconnect interface between the
signal line and the TWI is shown in the inset image at the top-right corner.

A. Mechanical Properties

Fig. 8. (a) Backside view of the highly dense and uniform probe arrays.
(b) Cross-sectional view of the cantilever-tip probe, with a close-up inset for
the nickel tip at the top-right corner.

1) Spring Constant of the Silicon Cantilever Probe: The

mechanical performance of the silicon cantilever is measured
by a Nano-indenter XP system, which is a load-controlled
indentation instrument made by MTS Nano Instruments Inc.
The indenting method has been proved to be an effective way
to evaluate mechanical properties of MEMS structures [18].
The schematic of the indentation measurement setup is shown
in Fig. 10(a), and the detailed measurement techniques have
been described in [9]. Fig. 10(b) plots the relationship between
the measured tip deflection and the loading force. The silicon
cantilever can withstand a tip contact force of 50 mN with an
overdrive response of about 33 m. Based on the test results,
the spring constant of the cantilever can be obtained as about
1520 N/m. Theoretical calculation of the spring constant , is
base on the following equation:
(2)

the cross-sectional view of the cantilever-tip probe is shown in

Fig. 8(b). It can be seen that the tip height is quite uniform. The
uniform probe tips with high planarity can greatly facilitate the
probing operation. The length of the cantilever is 800 m and
the height of the probe tip is about 90 m. The pyramid-shaped
nickel tip apex is 12 m in diameter that can be close-up viewed
in the inset of Fig. 8(b). Fig. 9 shows the SEM image of the Ti/Cu
signal-lines from the TWIs at the bottom of the 300- m-deep
cavity to the topside of the chip frame. The signal-lines on the
inclined plane can be clearly seen and, perfect conjunction between the signal line and the TWI can be close-up viewed in the
inset of Fig. 9.
IV. CHARACTERIZATION
The developed probe cards are characterized by testing a series of mechanical and electrical parameters. The tested parameters include contact force, overdrive, tip planarity, contact resistance, signal path resistance, leakage current, and so on. The
detailed characterization is given in following sections.

where is the loading force at the probe tip, i.e., the probing
is Youngs modulus of silicon; and
, and are
force;
the width, thickness, and length of the cantilever, respectively
[19]. According to the designed dimensions listed in Table I,
the spring constant is calculated as about 1430 N/m. The spring
constant from the measurement results, theoretical calculation
and ANSYS simulation are compared together in Fig. 10(b), resulting in a satisfactory agreement.
2) Material Properties of the Electroplated Nickel: The material properties of the electroplated nickel is also characterized
by the Nano-indenter XP system. Herein, an Oliver and Pharr
method is used that has been accepted as the most common
method for extracting Youngs modulus and Vickers hardness
from an indentation curve [20]. Fig. 11(a) shows the analysis
schematic for the indentation measurement. When a normal
loading force is exerted, the indenter tip is driven into the
and
material surface, resulting in both elastic displacement
. Only the elastic displacement can
plastic displacement

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Fig. 11. (a) Analytical schematic of the indentation measurement [20].

(b) Measured curve of load versus indenting displacement.

Fig. 10. (a) Schematic of the bending test setup using a nano-indenter system.
(b) Measured loading-displacement relationship of the silicon cantilever, compared with the theoretical calculation and the ANSYS simulation results.

TABLE I
DESIGNED PARAMETERS AND THE TESTING RESULTS
OF THE FABRICATED MEMS PROBE CARD

electroplated nickel are measured as 116 GPa and 420, respectively. The measured Youngs modulus is slightly lower
than 125 GPa from the bending test reported in [21], while the
Vickers hardness is a little higher than the reported value of
400 [21]. The high hardness of the electroplated nickel can help
the probe tip to scratch the natural oxide on Al pad with little
abrasion, and promise the probes high life expectancy.
3) Tip Planarity and Scrub Mark: The tip planarity of the
probe card is evaluated by optically scanning the probe tips
using a WYKO NT-2000 optical metrology system (made by
Veeco Instruments Company), which provides noncontact highresolution 3-D surface measurement base on optical profiling.
The testing result of the nonuniformity in tip planarity is within
m, which is better than the previously reported results by
using nickel electroplating cantilever-tips [5].
Atomic force microscope (AFM) is used in this study to scan
the probing mark made by the cantilever-tips. When the probe
tip scrubs on the testing pad, it slides forward on the pad surface, making a tiny pit on the pad surface and leaving a stack
of pad material at the end of the scrub mark. Fig. 12 shows the
AFM image of a scrub mark on Al pad under an overdrive of
20 m, i.e., a contact force of about 30 mN. The maximum
depth of the probe mark is about 300 nm, and the scrub area
is about 6 m 12 m.
B. Electrical Characterizations

recover after the indenter force is fully withdrawn. A measured

curve of loading versus indenting displacement is demonstrated
in Fig. 11(b). Youngs modulus and Vickers hardness of the

1) Contact Resistance: The electrical properties of the

MEMS probe card are tested with a semiautomatic probe
station, which is connected to an Agilent-4156C semiconductor
parameter analyzer. The contact resistance is measured when
the probe card is forced to contact with a metal film on a

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Fig. 14. Measured contact resistance variation with the temperature change
from 25 C to 145 C.

Fig. 12. AFM images of a probe mark on Al pad made by the nickel probe tip
under a probing force of about 30 mN.

Fig. 13. (a) Measured I-V curves for probing to three different metal films (Al,
Cu, and Au). (b) Measured contact resistances at the probing tips at different
positions on the probe-card wafer.

silicon wafer, with a dc voltage of 200 mV applied between

two cantilever-tip probes. I-V curves for three different types of
metal films (Al, Cu, and Au) are given in Fig. 13(a). The total
resistance is measured as about 2.5 that comprises two-times
contact resistance and two-times signal path resistance. When
the signal path resistance is measured, the contact resistance
can be extracted. Fig. 13(b) records the contact resistances
of the different probes located at different positions of the
fabricated wafer. Five measured points are indicated in the inset
image to plot the positions on the device wafer where contact
resistances are tested. All the measured contact resistances for
the three kinds of metal films are generally below 1 , with a
maximum variation as about 0.5 .
2) Temperature Stability of the Contact Resistance: Temperature stability of the contact resistance is deserved to be
considered, since the probe card for IC burn-in testing might
work under high temperature circumstances
[22].
The temperature stability can be evaluated with a thermal
chuck of the semiautomatic probe station. Shown in Fig. 14, the
contact resistance rises linearly when the temperature increases
from 25 C to 145 C. A hysteresis effect, due to the heat
transport system, is observed. The rise in the contact resistance
is considered mainly due to the temperature coefficient of the
metals [23].
3) Leakage Current: Leakage performance of the probe card
is characterized by detecting the electric current passing between two open tips. When a dc voltage of 5 V is applied, a
leakage current of about 90 pA is detected between two adjacent tips while the measured leakage current between the second
nearest tips is about 50 pA. Fig. 15 demonstrates the detailed
testing results for the adjacent and the second nearest tips.
Based on the descriptions above, all the designed parameters
and tested results of the MEMS probe card are summarized in
Table I. The characterizations provided in this study include the
mechanical test results for the cantilever, the material properties for the electroplated nickel, the tip planarity and the scrub
mark, contact resistance for the probes, temperature stability for
the resistance and the leakage current data. Even so, in order to
improve the probe card for a real applicable product, more characterizations need to be further evaluated in future work, such
as high temperature fatigue and creep test, contact resistance

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Fig. 15. Leakage current between the adjacent tips and the secondly nearest
tips, respectively.

stability over time/cycling and spring constant stability over

time/cycling. Besides, the minimum tip pitch for the proposed
probe card holds the possibility to be further shrunk down to
about 50 m. If a projection-type exposure machine can be used
instead of the conventional contacting exposure one, the patterned line width at the deep silicon cavity could be much finer
and the pitch of the arrayed cantilevers could be even narrower.
V. CONCLUSION
In this paper, a novel probe card for wafer-level burn-in test
has been designed, fabricated with MEMS techniques and characterized. The composite structure is composed of a silicon cantilever and a nickel probe tip. The single-crystal silicon, which
is a satisfactory elastic material and free from internal stress,
can guarantee the uniformity of the probing height and the high
planarity of the probe tips. On the other hand, the nickel tip
with high hardness and sound electric conductivity ensures a
low contact resistance and a long life expectancy. Furthermore,
the nickel probe tips and the TWIs are electroplated simultaneously, which can greatly simplify the fabrication process and
improve the fabrication yield. The measured spring constant of
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Fei Wang (S06M09) was born in Anhui Province,

China, in 1983. He received the B.S. degree in
mechanical engineering from the University of
Science and Technology of China, Hefei, China,
in 2003, and the Ph.D. degree in microelectronics
from Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Science,
Shanghai, China in 2008.
He is currently a postdoctoral researcher in Department of Micro- and Nanotechnology, Technical
University of Denmark, working on micro four point
probes for IC testing. His research interests include MEMS fabrication and design, IC device testing, and contact phenomena in electronic measurement.

WANG et al.: MICROCANTILEVER PROBE CARDS WITH SILICON AND NICKEL COMPOSITE MICROMACHINING TECHNIQUE

Xinxin Li was born in Liaoning Province, China, in

1965. He received the B.S. degree in semiconductor
physics and devices from Tsinghua University,
Beijing, China, in 1987, and the M.S. and Ph.D.
degrees in microelectronics from Fudan University,
Shanghai, China, in 1995 and 1998, respectively.
After he worked in Shenyang Institute of Instrumentation Technology for five years as a Research
Engineer, he resumed his graduate study. Then, he
sequentially worked in Hong Kong University of
Science and Technology as a Research Associate, in
Nanyang Technological University, Singapore, as a Research Fellow and, then,
joined Tohoku University, Japan, as a nonpermanent Lecturer (COE Research
Fellowship). From 2001 to now, he has been a Professor and now serves as the
Director of the State Key Lab of Transducer Technology, Shanghai Institute of
Microsystem and Information Technology, Chinese Academy of Sciences. He
now also serves as Adjunct Professor in both Fudan University and Shanghai
Jiaotong University, Shanghai, China. For a long period of time, his research interest has been in the fields of micro/nano sensors and transducers, micro/nano
electromechanical systems (MEMS/NEMS) and micro/nano electromechanical
integration technologies. He has invented more than 30 patents. He has published about 200 papers in referred journals and academic conferences. He is an
editorial board member for Journal of Micromechanics and Microengineering.
Dr. Li served as a Technical Program Committee member for 2008 IEEE
International Conference on Micro Electro Mechanical Systems (IEEE
MEMS-08) and IEEE International Conference on Sensors (IEEE Sensors)
from 2002 to 2008. He has been appointed as a Program Committee Member
for Transducers09.

477

Songlin Feng received the B.S. degree in physics

from Wuhan University, Wuhan, China, in 1983,
and the Ph.D. degree in semiconductor physics from
Paris University, Paris, France, in 1998, where he
won the unique foreign students course of chancellor
of PARIS University in Science.
After graduation, he worked in Semiconductor
Institute, Chinese Academy of Sciences, Beijing,
China, working on the research of defect in super-lattices. In 2001, he transferred to Shanghai Institute of
Microsystem and Information Technology, Chinese
Academy of Sciences, where he had served as a Professor and the Director of
the Institute. His current research interests are in the fields of wireless sensor
network and microsystem technologies. He has published more then 120 papers
in international journals.
Dr. Feng won several national and ministerial natural science prices. He is an
expert member of several Chinese national scientific research and development
programs.