Basic Ideas and Definition Major Components of Software/Hardware Computer Revolution

What is "Computer Architecture"
ECE 4680
Computer Architecture and Organization
Co-ordination of
levels of abstraction
Application
Lecture 1: A Short Journey to

the World of Computer Architecture
Compiler
Operating
System
Instruction Set
Architecture
Instr. Set Proc. I/O system
Basic Ideas and Definition
Digital Design
Circuit Design
Major Components of Software/Hardware
Merits of Abstraction/Layers/Hierarchy
Computer Revolution
Under a set of rapidly changing Forces : technology,

applications, Programming Languages, operating systems, history
ece4680 Lect1 Intro.1
February 6, 2002
Technology Trend: Clock rate
February 6, 2002
Technology Trends: Transistor Count Growth

100,000,000
100
10
i8086
10,000,000
R10000
Pentium100

i80386
Transistors
Clock rate (MHz)
1,000
i80286
1,000,000
i8080
i8008
i4004
1,000
1970
1980
1985
1990
1995
2000
2005
1975
1980
1985
1990
1995
2000
2005
- 40% per year, order of magnitude more contribution in 2 decades

- More and more functions can be performed by a CPU
- Similar story for storage:
capacity increased by 1000x over ten years, speed only 2x
30% per year ---> todays PC is yesterdays Supercomputer

February 6, 2002
February 6, 2002
Performance Trends
Technology => dramatic change

Processor
logic capacity: about 30% per year
clock rate:
i8086
i4004
1975
10,000
i8080
i8008
0.1
1970
i80286
100,000

R10000
Pentium

i80386
R3000
R2000
1000
about 20% per year
Supercomputers
100
Memory
DRAM capacity: about 60% per year (4x every 3 years)
Memory speed: about 10% per year
Performance
Mainframes
Cost per bit: improves about 25% per year

Disk
capacity: about 60% per year
10
Minicomputers
Microprocessors
0.1
1965
1970
1975
1980
1985
1990
1995
2000
Year
February 6, 2002
February 6, 2002
CPU and LAN Performance
Processor Performance (SPEC)

performance now improves ~ 50% per year (2x every 1.5 years)
Relative
Performance
350
300
CPU
(spec)
P e rforma nce
250
RIS C
1000
200
LAN
RISC
introduction
150
Inte l x86
100
100
50
100 Mb FDDI
10 Mb
1995
1994
1993
1992
1991
1990
1989
1988
1987
1986
1985
1984
1983
1 Gb ATM
MIPS
M/120
10
35%/yr
1982
DEC
Alpha
Year
1980
Ye ar
1985
1990
1995
2000
Did RISC win the technology battle and lose the market war?
February 6, 2002
H Notations and Conventions for Numbers

P
Appendix1:
Notations
and ConventionsNumeric
for Numbers
Abbreviation
Meaning
Value
CPrefix
10 3
m
One thousandth
Amill
micro
10 6
One millionth
2
nano
n
10 9
One billionth
0
p
One trillionth
10 12
0 pico
1 femto
f
One quadrillionth 10 15
Moores Law
Moores Law (1965)

The number of transistors on a microchip doubles about

every 18-24 months,
The speed of a microprocessor doubles about every 18-24

months,
The price of a microchip drops about 48% every 18-24

months,
atta
kilo
K (or k)
mega
Official Definition of Moores Law :
giga
http://www.intel.com/intel/museum/25anniv/hof/moore.htm
tera
peta
exa
February 6, 2002
assuming the perform ance m etric (processor speed or memory

capacity) of the chip stays the same.
One quintillionth
Thousand
Million
10 18
10 3 or 210
Billion
Trillion
Quadrillion
Quintillion
10 9 or 2 30
10 6 or 2 20
10 12 or 2 40
10 15 or 250
10 18 or 2 60
61
Even the measure unit is changing !!!

February 6, 2002
How they predict the future
February 6, 2002
Computer Arch. = Instruction Set Arch. + Organization

Computer Design
Popular Science , 1949 "Computers in the future may

weight no more than 1.5 tons"
Thomas Watson, Chairman of IBM , 1943 "I think there
is a world market for maybe five computers"
Instruction Set Design

Machine Language
Compiler View
"Computer Architecture"
Ken Olsen, founder and president of Digital

Equipment Corp, 1957 "There is no reason anyone
would want a computer in their home"
"Instruction Set Processor"

"Building Architect"
Charles H. Duell, Commissioner, U.S. Office of

patents "Everything that can be invented has been
invented"
Computer Hardware Design

Machine
Implementation
Logic Designer's View

"Processor Architecture"
"Computer Organization"
"Construction Engineer"
Bill Gates, 1981 "640K ought to be enough for anybody"

February 6, 2002
February 6, 2002
Instruction Set Architecture
MIPS R3000 Instruction Set Architecture
. . . the attributes of a [computing] system as seen by the

programmer, i.e. the conceptual structure and functional
behavior, as distinct from the organization of the data
flows and controls the logic design, and the physical
implementation.
Instruction Categories
Load/Store
Computational
Jump and Branch
Floating Point
- coprocessor
Memory Management
Special
Amdahl, Blaw, and Brooks, 1964
SOFTWARE
-- Organization of Programmable
Storage
R0 - R31
PC
HI
LO
-- Data Types & Data Structures:

Encodings & Representations
Instruction Format
-- Instruction Formats
-- Instruction (or Operation Code) Set
-- Modes of Addressing and Accessing Data Items and Instructions
OP
rs
rt
OP
rs
rt
OP
-- Exceptional Conditions
February 6, 2002
Organization
rd
sa
funct
immediate
target
February 6, 2002
Example Organization
ISA Level
TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20
FUs & Interconnect

MBus Module
SuperSPARC
-- Capabilities & Performance Characteristics of Principal

Functional Units
Floating-point Unit
(e.g., Registers, ALU, Shifters, Logic Units, etc.
L2
$
Integer Unit
-- Ways in which these components are interconnected
CC
MBus
DRAM
Controller
-- nature of information flows between components

-- logic and means by which
Inst
Cache
such information flow is controlled.
Ref
MMU
Data
Cache
L64852 MBus control
Choreography of FUs to realize the ISA

Store
Buffer
Register Transfer Level Description

Bus Interface
February 6, 2002
Measurement and Evaluation

Design
M-S Adapter
SBus
SBus
DMA
SCSI
Ethernet
SBus
Cards
STDIO
serial
kbd
mouse
audio
RTC
Boot PROM
Floppy
February 6, 2002
Levels of Representation
Architecture is an iterative process

-- searching the space of possible designs
-- at all levels of computer systems
temp = v[k];
High Level Language
Program
Analysis
v[k] = v[k+1];
v[k+1] = temp;
Compiler
Assembly Language
Program
Creativity
Assembler
Cost /
Performance
Analysis
Machine Language
Program
lw $15,
0($2)
lw $16,
4($2)
sw $16,
0($2)
sw $15,
4($2)
Machine Interpretation
Good Ideas
Bad Ideas
Control Signal Spec
Mediocre Ideas
February 6, 2002
February 6, 2002
ECE468:So what's in it for me?
ECE468: Course Overview

Computer Design
Instruction Set Deign
Computer Hardware Design
Machine Language
Machine Implementation\
Compiler View
"Computer Architecture"
"Processor Architecture"
"Instruction Set Processor"
"Computer Organization"
"Building Architect"
Construction Engineer
In-depth understanding of the inner-workings of modern computers,

their evolution, and trade-offs present at the hardware/software
boundary.
Insight into fast/slow operations that are easy/hard to
implementation hardware
Experience with the design process in the context of a large complex
(hardware) design.
Functional Spec --> Control & Datapath
Learn how to completely design a correct single processor computer.
No magic required to design a computer
Foundation for students aspiring to work in computer architecture.
Few people design computers! Very few design instruction sets!
Others: solidifies an intuition about why hardware is as it is.
Many people design computer components.

Very many people are concerned with computer function, in detail.
February 6, 2002
The SPARCstation 20
February 6, 2002
Levels of Organization
SPARCstation 20
SPARCstation 20
Memory SIMMs
Memory
Controller
Memory Bus
MBus
MBu
s
MBu
s
Disk
Computer
Slot 1
Slot 0
SBus
Slot 1
SBus
Slot 3
SBus
Slot 0
SBus
Slot 2
SBus
MSBI
SEC
MACIO
Keyboard
Floppy
& Mouse
Disk
SPARC
Processor
Tape
Devices
Control
Input
Datapath
Output
SCSI
Bus
External Bus
February 6, 2002
The Underlying Network
February 6, 2002
Processor and Caches

SPARCstation 20
SPARCstation 20
MBus Module
Memory Bus
Memory
Controller
Memory
SuperSPARC Processor
MBus
Standard I/O Bus:

SCSI Bus
Processor Bus:
MBus
MBu
s
MBu
s
Suns High Speed I/O Bus:

SBus
MSBI
SEC
MACIO
Low Speed I/O Bus:

External Bus
Slot 1
Registers
Datapath
Internal
Cache
Control
Slot 0
External Cache
February 6, 2002
February 6, 2002
Memory
Input and Output (I/O) Devices
SIMM Slot 7
SIMM Slot 6
SIMM Slot 5
SIMM Slot 4
SIMM Slot 3
SIMM Slot 2
Memory
Controller
SIMM Slot 1
SIMM Slot 0
SPARCstation 20
SBus: High Speed I/O Devices
Memory Bus
External Bus: Low Speed I/O Device

Disk
DRAM SIMM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
SPARCstation 20
SCSI Bus: Standard I/O Devices
SBus
Slot 1
SBus
Slot 3
SBus
Slot 0
SBus
Slot 2
SBus
SEC
February 6, 2002
Standard I/O Devices
MACIO
Keyboard
Floppy
& Mouse
Disk
Tape
SCSI
Bus
External Bus
February 6, 2002
High Speed I/O Devices

SPARCstation 20
SPARCstation 20
SBus is SUNs own high speed I/O bus
SCSI = Small Computer Systems Interface
SS20 has four SBus slots where we can plug in I/O devices
A standard interface (IBM, Apple, HP, Sun ... etc.)
Disk
Computers and I/O devices communicate with each other

The hard disk is one I/O device resides on the SCSI Bus
Example: graphics accelerator, video adaptor, ... etc.

High speed and low speed are relative terms
Tape
SCSI
Bus
SBus
Slot 1
SBus
Slot 3
SBus
Slot 0
SBus
Slot 2
SBus
February 6, 2002
Slow Speed I/O Devices
February 6, 2002
Summary
ISA--Principle of abstraction
SPARCstation 20
Hiding details from the level above

Both software designers and hardware designers comply with
The are only four SBus slots in SS20--seats are expensive

All computers consist of five components
The speed of some I/O devices is limited by human reaction

time--very very slow by computer standard
Processor: (1) datapath and (2) control

(3) Memory
(4) Input devices and (5) Output devices
Examples: Keyboard and mouse

No reason to use up one of the expensive SBus slot
Not all memory are created equally

Cache: fast (expensive) memory are placed closer to the processor
Main memory: less expensive memory--we can have more
Input and output (I/O) devices has the messiest organization
Keyboard
Floppy
& Mouse
Disk
Wide range of speed: graphics vs. keyboard
External Bus
Wide range of requirements: speed, standard, cost ... etc.

Least amount of research (so far)
February 6, 2002
February 6, 2002

Basic Ideas and Definition Major Components of Software/Hardware Computer Revolution

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Basic Ideas and Definition Major Components of Software/Hardware Computer Revolution

Uploaded by

Copyright:

Available Formats

What is "Computer Architecture"

Lecture 1: A Short Journey to

Instr. Set Proc. I/O system

Basic Ideas and Definition

Major Components of Software/Hardware

Under a set of rapidly changing Forces : technology,

ece4680 Lect1 Intro.1

Technology Trend: Clock rate

ece4680 Lect1 Intro.2

Technology Trends: Transistor Count Growth

Clock rate (MHz)

ece4680 Lect1 Intro.3

- 40% per year, order of magnitude more contribution in 2 decades

30% per year ---> todays PC is yesterdays Supercomputer

ece4680 Lect1 Intro.4

Technology => dramatic change

about 20% per year

Cost per bit: improves about 25% per year

ece4680 Lect1 Intro.5

ece4680 Lect1 Intro.6

CPU and LAN Performance

Processor Performance (SPEC)

ece4680 Lect1 Intro.8

H Notations and Conventions for Numbers

Moores Law (1965)

The number of transistors on a microchip doubles about

The speed of a microprocessor doubles about every 18-24

The price of a microchip drops about 48% every 18-24

Official Definition of Moores Law :

assuming the perform ance m etric (processor speed or memory

Even the measure unit is changing !!!

How they predict the future

ece4680 Lect1 Intro.10

Computer Arch. = Instruction Set Arch. + Organization

Popular Science , 1949 "Computers in the future may

Instruction Set Design

Ken Olsen, founder and president of Digital

"Instruction Set Processor"

Charles H. Duell, Commissioner, U.S. Office of

Computer Hardware Design

Logic Designer's View

Bill Gates, 1981 "640K ought to be enough for anybody"

ece4680 Lect1 Intro.12

Instruction Set Architecture

MIPS R3000 Instruction Set Architecture

. . . the attributes of a [computing] system as seen by the

Amdahl, Blaw, and Brooks, 1964

-- Data Types & Data Structures:

ece4680 Lect1 Intro.14

TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20

FUs & Interconnect

-- Capabilities & Performance Characteristics of Principal

(e.g., Registers, ALU, Shifters, Logic Units, etc.

-- Ways in which these components are interconnected

-- nature of information flows between components

such information flow is controlled.

L64852 MBus control

Choreography of FUs to realize the ISA

Register Transfer Level Description

ece4680 Lect1 Intro.15

Measurement and Evaluation

ece4680 Lect1 Intro.16

Architecture is an iterative process