SystemC-to-Layout ASIC Flow Walkthrough

20.6.2015

Running the Demo

Youcanexecutetheflowautomaticallybyexecutingthecshshellscript:

cshrun_ASIC_demo.csh

Thescriptrunsalltoolsinasequence.Somethingsyoushouldbeawareare:
Sometoolsmaybeunresponsivewhentheyexecutecommands,sobepatient.
Afterthescriptsfinish,theyopenreportfilesgeneratedbythetoolinatexteditor.When
youhavefinishedexaminingthereports,closethetexteditor.
Thedesignremainsloadedintheprogram,soyoucaninspectitusingtheuserinterface
commands.
Whenyouarereadytocontinue,exitthetoolfromtheFilemenu.Sometimesyoumay
havetotype
exit
or
quit
.

Executing the Flow Step by Step

Youcanexecutetheflowonetoolatatimebyfollowingtheinstructionshownbelow.

SystemC Model Simulation

The"goldenmodel"hasbeenwritteninSystemC.Themodelcanbesimulatedbycompilingthe
sourcecodefilesintoanexecutableprogram,orbyusingtheQuestaSimsimulator.ASystemC
testbenchisavailableforthat.Laterthemodelcanbeinstantiatedasareferencemodelinthe
SystemVerilogtestbenchthatisusedtoverifytheRTLmodel.

Tocompilethefileswiththeg++compiler,enterthecommand

makefscripts/Makefile.sc

Tosimulatethedesign,type

makefscripts/Makefile.scsim

Simulationresultsaredumpedtotheterminalintextformat.

TosimulatethemodelwithQuestaSim,usethecommand

vsimdoscripts/1_vsim_systemc_simulation.tcl


YoucanviewthesimulationresultsintheWavewindow.

QuestaSimWavewindowshowingSystemCsimulationresults.SystemCmodelstructureis
shownontheleft.

SystemC Synthesis
TheSystemCmodelcanbesynthesizedintoRTLVerilogusingCadenceCtoSiliconhighlevel
synthesistoolwiththecommand:

ctosguiscripts/2_ctos_hls.tcl

ThescripthasbeensetuptoscheduletheFIRfilteralgorithmonsixclockcycles.


CadenceCtoSiliconCompilersynthesisresultsviews:SynthesizedRTLschematicontheleft,
andacontroldataflowgraphontheright,showingonwhichclockcyclesthehighlighted
multiplierisactive.

Notice!Theremainderofthisdemousesthe"handcrafted"RTLmodelofthecircuit.Youcan
setthevariable
HLS_RTL
to1in
input/0_setup_design.tcl
ifyouwanttousetheRTLmodel
synthesizedfromSystemC,butmostofSystemverilogassertionswillthenbeexcludedfrom
formalverification.

RTL Model Simulation

TheRTLSystemVerilogmodelcanbesimulatedwithQuestaSimusingthecommand:

vsimdoscripts/3_vsim_rtl_simulation.tcl

ThesimulationusesanUVMtestbenchwiththeSystemCmodelinstantiatedasareference
model.SimulationresultscanbeviewedintheWave,Assertions,andCoveragewindows.The
simulatorsaveaSAIFformatactivityfilethatisusedbythelogicsynthesistoolforpower
estimation.


QuestaSimWaveviewershowingsignalandassertionevaluationwaveforms.

Formal Verification
SystemVerilogassertionswrittenforthedesigncanbeformallyverifiedusingtheQuesta
Formaltoolasfollows:

qformaldoscripts/3_qformal_rtl_verification.tcl

Thetoolprovesassertionstobetrueorfalsebytryingtofindcounterexamplesthatcause
assertionstofail.Acounterexampleisastateofthecircuit,thatcanbereachedfromaninitial
state,andthatcausesanassertiontofail.Thisverificationmethoddoesnotdependoninput
stimulicreatedbythedesigner.


QuestaFormalanalysisresultsviewshowingseveralfiredassertions,onevacuouslyproven
andthreeprovenassertions.Thewaveformwindowpresentsacounterexamplethatprovesthe
assertionctr8_init_atobefalse.

RTL Code Check

TheRTLcodecanbecheckedformanycommoncodingerrorsorbadcodingstylewithQuesta
AutoCheckusingthecommand:

qautocheckdoscripts/3_qautocheck_rtl_verification.tcl


QuestaAutoCheckanalysisresultsshowingthreepotentialproblems.Theselectedcaseshow
apotentialarithmeticoverflowsituation.

Clock Domain Crossings Verification

PropersynchronizationofclockdomaincrossingsignalscanbeverifiedwithQuestaCDCby
usingthecommand:

qcdcdoscripts/3_qcdc_static_cdc_analysis.tcl

Ifthetooldetectscrossingsthatcannotbeproventobecorrect,itlabelstheseas"evaluations".
Thesecrossingsmustbeverifiedbysimulation.Thetoolcreatesasimulationmodelthat
containsassertionsthatchecktheoperationofthesynchronizersduringsimulation.Youcanrun
thesimulationandanalyzetheresultsusingthecommand:

qcdcdoscripts/3_qcdc_dynamic_cdc_analysis.tcl

SimulationresultsareontheSimulationtab.


QuestaCDCstaticanalysisresultsviewshowingoneclockdomaincrossingsignalwitha
violation,four"evaluations"thathavetobesimulated,andfourcrossingsproventobecorrect.
Theschematicshowsthecrossingthatcausedtheviolation(atwoflipflopsynchronizerdriven
bycombinationallogic)
.

RTL Synthesis with Clock Gate and Scan Chain Insertion

TheRTLSystemVerilogmodelcanbesynthesizedintogatesusingSynopsysDesignCompiler
withthefollowingcommand:

design_visionxgui_startfscripts/4_dc_rtl_synthesis.tcl

ThiscommandtranslatestheSystemVerilogcodeintogenericflipflopsandBooleanlogic
functions,andmapsthesetocomponentsavailableinthetargettechnologylibrarysothatit
meetsthetimingconstraintsdefinedinthesettingsfilesample_design.sdc.Thescriptalso

insertsclockgatingcellstoreducedynamicpowerconsumption,andcreatesscanchainsthat
improvetestability.

SynopsysDesignCompilerRTLsynthesisresultsviews:Logicalstructure,pathslack(timing
margin)histogram,andagatelevelschematic.

Formal Equivalence Check of RTL and Gate-Level Models

ThelogicalequivalenceoftheRTLSystemVerilogmodelandthesynthesizedgatelevelVerilog
netlist(output/sample_design_gatelevel.v)canbeverifiedusingtheSynopsysFormality
programwiththecommand:

formalityfilescripts/5_formality_gatelevel_verification.tcl


SynopsysFormalityresultsviewshowing"logiccones"foronecomparepoint.Topschematic
showsthelogicdrivingacomparepoint(flipflopinput)inRTLSystemVerilogcode.Bottom
schematicshowsthelogicconeforthesamecomparepointinthesynthesizedgatelevel
model.

Gate-Level Simulation
YoucansimulatethesynthesizedgatelevelmodelwiththeRTLmodelasareferencemodel
usingthiscommand:

vsimdoscripts/5_vsim_gatelevel_simulation.tcl

Becausethelogicsynthesisprogramdoesnotfixholdviolations,timingchecksaredisabledin
gatelevelsimulation.Holdviolationsarefixedinthelayoutphase,afterclocktreeinsertion.

Standard Cell Place and Route with Clock Tree Synthesis

YoucancreatealayoutforthedesignusingCadenceEncounterstandardcellplaceandroute
toolwiththecommand:


encounterreplayscripts/6_encounter_layout_synthesis.tcl

CadenceEncounterlayoutview.Theareaoccupiedbythethreearchitecturalunitsis
highlightedwithdifferentcolors:orangeforthedaq_unit,blueforthecdc_unit,andyellowfor
thespi_slave.Thewhilelinesshowclocktreeroutings.

Formal Equivalence Check of Pre- and Post-Layout Models

LogicalequivalenceofthesynthesizedgatelevelVerilognetlist
(output/sample_design_gatelevel.v)andthefinalpostlayoutnetlist
(output/sample_design_postlayout.v)canbeverifiedusingFormalitywiththecommand:

formalityfilescripts/7_formality_postlayout_verification.tcl

Post-Layout Timing Simulation

YoucansimulatethepostlayoutgatelevelmodelwiththeRTLmodelasareferencemodel
usingthiscommand:

vsimdoscripts/7_vsim_postlayout_simulation.tcl

Timingchecksaredisabledforfirstlevelsynchronizerflipflopsinthissimulation.

Inpostlayoutsimulationthespuriousvaluesseeninthe"analog"representationofthe16bit
data_outsignalarecausedbyoutputbitschangingatslightlydifferenttimesbecauseof
differentflipfloptooutputdelays.

Post-Layout Static Timing Analysis

YoucanrunstatictiminganalysisofthepostlayoutnetlistwithparasiticdatausingSynopsys
PrimeTimewiththecommand:


primetimexgui_startguifilescripts/7_primetime_postlayout_sta.tcl

PrimeTime'spathanalyzerwindow:Theleftpartshowstheworst100timingpathsinthe
registertoregisterpathgroup,organizedaccordingtotheirstartingpointandworstnegative
slack(WNS).Therightpartshowsacolorcodedmapwheretheareasrepresentthenumberof
pathsinthedifferentslackcategories.Inthiscaseallslacksarepositive,sothenumberof
violatingpaths(NVP)iszero.

Post-Layout Simulation for Dynamic Power Consumption Analysis

Dynamicpoweranalysisneedsinformationabouttheswitchingactivityofthesignalsinthe
design.Youcancapturethisactivitydatafromsimulationbyexecutingthefollowingcommand:

vsimdoscripts/8_vsim_postlayout_power_simulation.tcl

Thiscommandrunspostlayoutsimulationwithtimingchecksdisabled,andsavesactivity
informationinavaluechangedump(VCD)filethatcanbeusedinapoweranalysistool.

Post-Layout Dynamic Power Consumption Analysis

YoucananalyzethepowerconsumptionofthecircuitbyrunningSynopsysPrimeTimePX
usingthecommand:


primetimexgui_startguifilescripts/8_primetime_power_analysis.tcl

Thiscommandreadsinthepostlayoutnetlistandparasiticcapacitancedatafilecreatedby
Encounter,andtheVCDfilecreatedbysimulation,andcalculatesapowerconsumption
estimate.

PrimeTimePXpowermapviewshowsthecontributionofarchitecturalblocksandindividual
componentstothetotalpowerconsumptionwithareaandcolorcoding.

ThePrimeTimePXscriptopensawaveformviewerthatshowsthevariationofpower
consumptionofthedesignovertime.


PrimeTimePX'spowerwaveformviewshowsdynamicpowerconsumptionovertime.Inthe
figureshownabovethedata_fifoisseenconsumingalotofpowerwhenthefilterisbeing
programmedandthefifo_clrsignalisactive(synchronousreset).This"opens"allclockgates
atthesametime,whichcausespowerconsumptiontorise.

Automatic Test Pattern Generation

YoucangeneratetestpatternsformanufacturingtestwithSynopsysTetraMaxbyusingthe
command:

tmaxscripts/9_tmax_atpg.tcl

ThescriptreadsinthepostlayoutnetlistsandaSTILfilethatdescribestheteststructures
insertedbythelogicsynthesistool,andgeneratespatternsbasedonthestuckatfaultmodel.


SynopsysTetraMaxfaultanalysisview.Astuckatfaultattheinputofthehighlightedgate
couldnotbetestedbecauseitsstatecouldnotbeobservedfromthescanpathflipflopinthe
rightendoftheschematic.