Comparative Analysis of 8 X 8 Bit

Vedic and Booth Multiplier

Sasha Garg, Swati Garg, Vidhi Sachdeva
Electronics and Communication
ITM University
Gurgaon, INDIA
sasha4garg@yahoo.co.in, swatigarg_1992@yahoo.co.in,vidhisach@gmail.com

II.
BOOTH MULTIPLIER
In Booth multiplication the compilation speed it
increased due to the decrease in the number of partial
products required to compute the result[1]. The algorithm
makes use of simple operations like twos complement,
arithmetic right shift etc.; instead of more complicated ones
like addition. The architecture takes two 8 bit numbers as
input and generates a 16 bit product as the output. Since, we
are performing signed multiplication the MSB of the
operands is always the signed bit and will not be used as
part of the magnitude. To decide on the multiplier and the
multiplicand, we take the 2s complement of the two
numbers. The numerically smaller number is designated to
be the multiplicand and the other to be the multiplier. Now
the beginning product is obtained by concatenating 8 0-bits
with the multiplier. The previous LSB is initialized as 0.The
current LSB and the previous LSB together decide the
course of the arithmetic action to be taken according to the
following:

Abstract - Speed and power consumption are one of the most

important parameters to judge the performance of a
computational method. In this paper, we compare two
algorithms for 8 Bit multiplication namely Vedic
Multiplication Algorithm and Booth algorithm. This paper
aims in bringing to the fore the differences in compilation
speeds and the chip area consumption of the two
methodologies. The programming language used is Verilog and
the synthesis has been done on Xilinx 14.5.
Keywords: Vedic Multiplication, Booth Multiplication, Xilinx,
Verilog

I.
INTRODUCTION
Multiplication forms one of the basic arithmetic
operations that find itself in wide use, especially in Digital
Signal
Processing.
A
variety
of
computer
arithmetic techniques are available which can be used in
implementation of a digital multiplier. Most of these
techniques employ the concept of a set of partial products
and their simultaneous addition. The above process is
similar to the method that is taught to schoolchildren for
conducting long multiplication on decimals, but has been
modified here for application to binary digits. Various
multiplication techniques are available in the field of
mathematics like, repetitive addition, Vedic Multiplication,
Booth Multiplication, Ancient Egyptian Method etc. The
comparison is based on 3 parameters: delay, area, power.
These form the basis for judging the efficiency of the VLSI
design of the multiplier in concern. The ancient technique of
Vedic multiplication involves the use of Urdhava
Tiryagbhyam Sutra[2]. Booth Multiplication algorithm[6,7]
uses recorded multipliers. Vedic mathematics is mainly
based on sixteen principles or word-formulae which are
termed as sutras one of which is Urdhava Tiryagbhyam
Sutra. Booth's multiplication algorithm is a multiplication
algorithm that multiplies two signed binary numbers
in twos complements notation. In this paper, we focus on 8
X 8 Bit multiplier using the above two mentioned
techniques implemented and simulated on Xilinx Version
14.5.

c
978-1-4799-3080-7/14/$31.00 2014
IEEE

00: no arithmetic operation

01: add multiplicand to left half of the product

10: subtract multiplicand from left half of the

product

11: no arithmetic operation

Next, an arithmetic right shift (ASR) is performed on the

entire product. The above process is repeated 8 times (size
of operands).At the end of the 8th pass, the final product is
obtained.
For hardware implementation of multiplication, same steps
are replicated as is done by hand, i.e., partial products are
computed, shifted accordingly, and summed. This algorithm
thus, becomes very slow if there are many partial products
(i.e. many bits) as the output needs to wait until each sum is
performed. Booths algorithm decreases the number of
required partial products and hence is faster owing to the
fact that the number of sums of partial products was
reduced.

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result obtained is a number which is more than 4 bits. Hence

it is taken to be R7R6R5R4R3R2R1R0. The result is obtained
to be[1]:

Start

i)
ii)
iii)
iv)
v)
vi)
vii)
viii)

Product(p)<-0,
prev carry(cy_p)<-0
M<-MULTIPLICAND
Q<-MULTIPLIER
C<-COUNT

10

01
Q0,Q-1

p<-p-M

p<-p+M

00

11

R0= a0b0
R1= a0b1 + a1b0
R2 = a0b2 + a1b1 + a2b0+ R1
R3 = a0b3 + a1b2 + a2b1 + a3b0+ R2
R4 = a1b3 + a2b2 + a3b1 + R3
R5 = a1b2 + a2b1 + R4
R6 = a3b3 + R5
R7 = carry of R6

An 8 bit multiplier is generated using four 4 bit

multipliers (which are formed with the help of AND gates,
half adders and full adders) and 3 ripple carry adders. The
ripple carry adders are formed by the combinations of XOR
gates, full adders and half adders. The ADDER 1 consists of
7 full adders and a half adder. ADDER 2 comprises of four
half adders, three full adders and a XOR gate. ADDER 3
has three half adders, four full adders and a XOR gate[4,5].
START

ARITHMETIC SHIFT
RIGHTp,Q,cy_p
COUNT<-COUNT-1
Initialize 8 bit Multiplicand x and 8 bit Multiplier y
and 16 bit Product Prod1
count=0?

no

End
yes

Generate Partial Products

Fig. 1. BOOTH MULITPLIER ALGORITHM

III.
VEDIC MULTIPLIER
The Vedic Multiplier[2,3] uses the Urdhva Tiryagbyham
Sutra. It is also known as Vertical and Cross Wise method.
In this the partial products are obtained with the subsequent
addition of all the partial products.
For example, take two numbers and place them one
below the other.

Four 4- bit partial products

Vedic 8- bit Adder

Vedic 8- bit Adder

Vedic 8- bit
Adder

The following steps are then performed:

Multiply the digits at ones place with each other

and write it as the right most part of the answer.
Multiply the digits at tens place with each other.
This is the left most part of the answer.
Then multiply the numbers crosswise and add the
products to get the middle part.
If any carry is generated, it is added to the number
to its left.

Hence the answer is obtained.

Result Obtained

STOP
Fig. 2. VEDIC MULTIPLIER ALGORITHM

In the case of Binary numbers, the multiplication is

replaced by AND logic. For a 4 bit multiplier consider two
numbers a3a2a1a0 and b3b2b1b0. By using Vedic methods the

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2014 International Conference on Advances in Computing,Communications and Informatics (ICACCI)

Fig. 3. OUTPUT FOR BOOTH MULTIPLIER

Fig. 4. OUTPUT FOR VEDIC MULTIPLIER

IV.
COMPARISION
Based on our experimental findings of the comparison
conducted on the Nexys3, Spartan 6, the differences
between 8X8 Vedic Multiplier and Booth Multiplier can be
summarized as follows:
The area in terms of utilization of slices is comparatively
less in Vedic Multiplier. The Vedic Multiplier uses 161
slices whereas the Booth Multiplier uses 287 slices. The
number of fully used LUT-FF pairs is 0 in case of Vedic
Multiplier and 1 in case of Booth Multiplier.

TABLE 1. DELAY SUMMARY (BOOTH)

DELAY SUMMARY (BOOTH)

Delay

73.962 ns (Levels of Logic = 186)

Source

u_7 (LATCH)

Destination

u_7 (LATCH)

Source Clock

x[7]_x[6]_Mux_o falling

Destination Clock

x[7]_x[6]_Mux_o falling

The delay generated in Vedic Multiplier is approximately

1/10th of the delay generated in Booth Multiplier.

TABLE 2. DELAY SUMMARY (VEDIC)

DELAY SUMMARY (VEDIC)

Delay

7.929 ns (Levels of Logic = 13)

Source

x<2> (PAD)

Destination

Prod<10> (PAD)

2014 International Conference on Advances in Computing,Communications and Informatics (ICACCI)

2609

VII. REFERENCES

Delay (in ns)

80

[1]

60

[2]

Vedic Mul.

40

[3]

Booth Mul.

20
[4]

0
Fig. 9. COMPARISON (Delay)

[5]

Number of LUT Slices

used

400
[6]

300
200

Vedic Mul
[7]

Booth Mul2

100

Premananda B.S.,Samarth S. Pai, Shashank B, Shashank S.

Bhat, Design and Implementation of 8-Bit Vedic Multiplier,
IJAREEIE, Volume. 2, Issue 12, December 2013
Swami Bharati Krishna Tirthaji Maharaja, Vedic
Mathematics, MotilalBanarsidass Publishers, 1965.
Ch. Harish Kumar "Implementation and Analysis of Power,
Area and Delay of Array Urdhava, Nikhilam Vedic Multipliers,
" Internatinal Journal of Scientific and Research Publications,
Volume 3, Issue 1 January 2013, ISSN 2250 3153.
Anju and V.K. Agrawal, FPGA Implementation of Low Power
and High Speed Vedic Multiplier using Vedic Mathematics,
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)
Volume 2, Issue 5 Jun. 2013, ISSN: 2319 4200, pp. 51-57.
Aniruddha Kanhe, Shishir Kumar Dasand Ankit Kumar Singh,
Design and Implementation of Low Power Multiplier using
Vedic Multiplication Technique, International Journal of
Computer Science and Communication, Volume 3, No. 1, June
2012, pp. 131-132.
Dr. Ravi Shankar Mishra, Prof. Puran Gour and Braj Bihari
Soni, 'Design and Implements of Booth and Robertsons
multipliers algorithm on FPGA', International Journal of
Engineering Research and Applications (IJERA) Vol 1(Issue 3),
pp. 905-910.
Neha Goyal, Khushboo Gupta and Renu Singla (2014), 'Study
of Combinational and Booth Multiplier', International Journal
of Scientific and Research Publications Volume 4(Issue 5).

0
Fig. 10. COMPARISON (Area)

V. CONCLUSION
The Urdhva Tiryagbyham Sutra provides us with a
highly efficient method over Booth Algorithm for
multiplication in terms of speed, delay and area utilization.
Therefore, it can be concluded that the 8X8 bit Vedic
Multiplier is better than Booth Multiplier based on the
parameters discussed above. The specified architectures for
Vedic Multiplication and Booth Multiplication can be
extended for 16- bit, 64-bit etc. multiplication.

VI. ACKNOWLEGMENT
This research paper is made possible through the help
and support from our Department of EECE, ITM University
who provided us with the necessary software and hardware
including Xilinx and FPGA Kit.
We would like to acknowledge the efforts and guidance
offered by our faculty.

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2014 International Conference on Advances in Computing,Communications and Informatics (ICACCI)