MLX83100

Automotive 2-Phase DC Pre-Driver

Features and Benefits

2-phase DC gate driver for H-bridge control

- Level shifting between microcontroller
PWM outputs and 2 external half-bridges
- Compatible with 3.3V-5V microcontrollers

Integrated current sense amplifier

- Low offset and low offset drift
- Fast settling time < 1s
- Programmable gain: 8x-48x

Supported supply voltage range

- Absolute maximum rating: 45V
- Operating range: 4.5V-28V
- Automotive qualified for 12V boardnet
- Suitable for 12V-28V battery systems
- Sleep mode with quiescent current <30A

Extensive diagnostics
- Under/over voltage detection
- Over temperature warning
- Programmable VDS monitoring
- VGS monitoring

Two charge pump configuration modes for

- Low voltage operation
- Reverse polarity N-FET protection

Serial, PWM diagnostics interface

- Configurable diagnostics
- Full diagnostic feedback

Customer configurable EEPROM

- Driver configuration
- Diagnostics configuration

Small package, high temperature qualification

- 28-pin TSSOP-EP
- AEC-Q100 grade 0 qualification (TJ=175C)

Industrial DC motor drivers up to 28V

- Pumps
- Fans
- Blowers
- Compressors

High side N-FET drivers with bootstrap circuits

- Integrated 12V voltage regulator
- Supports 4x 500nC N-FETs at 20kHz PWM
- Supports 100% PWM operation

Application Examples

Automotive 12V boardnet DC applications

- Water pump / Oil pump / Fuel pump
- Cooling fan
- HVAC blower / compressor
- Wiper
- Sunroof
- EPS

Ordering Information
Product Code
MLX83100
Legend:
Temperature Code:
Package Code:
Option Code:
Packing Form:
Ordering example:

3901083100
Rev 4.1

Temperature Code
L

Package Code
GO

Option Code
DBA-000

Packing Form
RE

L(-40C to 150C)
GO=TSSOP
DBA-000
RE = Reel
MLX83100LGO-DBA-000-RE

Page 1 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Functional Diagram
VBAT

VSUP

3.3V-5V
Supply

CP

VBOOST
VREG

Charge Pump
12V Regulator
Driver Supply

CP1
CP2
CP3

Internal Supply

VDD

VBATF

MLX83100
DC Pre-Driver

VDD Supply
MCU

Shoot
Through
Protection

FETB2-3

GATET2

Driver Logic

FETT2-3

PWM

GATET1

HS
Gate Drivers

PHASE1

Dead
Time

PHASE2

EN

I/O

GATEB1
MISO

ICOM

I/O

Custom Interface

EEPROM

Error Output

Diagnostics

LS
Gate Drivers

VREF

ADC

GATEB2

IBP

Current Sense Amplifier

ISENSE

IBM

AGND

DGND

Figure 1-1. Typical Application Diagram

VBAT

VSUP

3.3V-5V
Supply

CP

VBOOST
VREG

Charge Pump
12V Regulator
Driver Supply

CP1
CP2
CP3

Internal Supply

VDD

VBATF

MLX83100
DC Pre-Driver

VDD Supply
MCU
FETT2-3

PWM

FETB2-3

GATET1

HS
Gate Drivers

GATET2

Driver Logic

Shoot
Through
Protection

PHASE1

Dead
Time

PHASE2

EN

I/O

GATEB1
MISO

ICOM

I/O

Custom Interface

EEPROM

Error Output

Diagnostics

LS
Gate Drivers

GATEB2

VDD

VREF

ADC

IBP

Current Sense Amplifier

ISENSE

IBM

AGND

DGND

Figure 1-2. Alternative Application Diagram

Note:
Both grounds, AGND-DGND, should be shorted together as close as possible to the pre-driver IC.

3901083100
Rev 4.1

Page 2 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

General Description

The MLX83100 is a two phase pre-driver (also called bridge or gate driver) IC with integrated current
sense amplifier. This device is used to drive brushed DC motors in combination with a microcontroller and
four discrete power N-FETs.
The device is able to control four external N-FETs for full H-bridge control in the supply range from 4.5V to
28V, by means of the integrated charge pump. The high side gate drivers are supplied via bootstrap circuits.
The trickle charge pump allows 100% PWM operation despite the use of bootstrap capacitors. The
bootstrap voltage regulator is optimized for gate charges up to 500nC per FET at 20 kHz PWM.
The device comprises various monitoring and protection functions, including under voltage and over
voltage detection at multiple internal voltage nodes, over temperature detection, drain-source and gatesource voltage monitoring of the external N-FETs. In case of fault detection, the ICOM diagnostics interface
will inform the microcontroller with a PWM signal, where the duty cycle indicates the nature of the error.
An integrated fast, high-bandwidth, low offset current sense amplifier allows for precise torque control,
with programmable gain selection.
The MLX83100 provides an EEPROM for configurability, avoiding the need for a high pin-count package.
The configuration allows the customer to optimize the pre-drivers operation for different applications.

3901083100
Rev 4.1

Page 3 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Table of Contents

Functional Diagram ..................................................................................................................................................... 2

General Description .................................................................................................................................................... 3

Table of Contents ........................................................................................................................................................ 4

Pin Configuration ........................................................................................................................................................ 5

Pin Definitions and Functions ..................................................................................................................................... 6

Absolute Maximum Ratings ........................................................................................................................................ 7

Operating Range ......................................................................................................................................................... 7

Electrical Specifications............................................................................................................................................... 8
8.1

MLX83100 Typical Performance Graphs ........................................................................................................... 14

Block Diagram ........................................................................................................................................................... 15

10 Functional Description .............................................................................................................................................. 16

10.1

Supply System ................................................................................................................................................... 16

10.2

Gate Drivers ...................................................................................................................................................... 20

10.3

Integrated Current Sense Amplifier and Over Current Comparator ................................................................. 21

10.4

Protection and Diagnostic Functions ................................................................................................................ 22

10.5

EEPROM Configuration ..................................................................................................................................... 27

11 ESD Protection .......................................................................................................................................................... 33

12 Package Information ................................................................................................................................................. 34
12.1

Package Marking ............................................................................................................................................... 34

12.2

Package Data TSSOP28-EP (4.4x9.7mm, 28 Leads) ........................................................................................ 35

13 Standard information regarding manufacturability of Melexis products with different soldering processes ......... 36
14 ESD Precautions ........................................................................................................................................................ 36
15 Disclaimer ................................................................................................................................................................. 37
16 Contact Information.................................................................................................................................................. 37
17 History of Changes .................................................................................................................................................... 38

3901083100
Rev 4.1

Page 4 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Pin Configuration

FETT2

28

AGND

FETT3

27

n.c.

VDD

26

VBATF

VREF

25

VSUP

IBM

24

CP

IBP

23

DGND

ISENSE

22

GATEB3

MISO

21

GATEB2

FETB2

20

VREG

FETB3

10

19

VBOOST

ICOM

11

18

CP3

EN

12

17

GATET3

PHASE2

13

16

PHASE3

GATET2

14

15

CP2

Figure 4-1. MLX83100 Pin Configuration TSSOP28-EP Package

3901083100
Rev 4.1

Page 5 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Pin Definitions and Functions

MLX83100
TSSOP28-EP
Pin
1
2

Name

Type

FETT2
FETT3

DI
DI

VDD

PWR

4
5
6
7
8

VREF
IBM
IBP
ISENSE
MISO

AI
AI
AI
AO
DI

FETB2

DI

10

FETB3

DI

11

ICOM

IO

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

EN
PHASE2
GATET2
CP2
PHASE3
GATET3
CP3
VBOOST
VREG
GATEB2
GATEB3
DGND
CP
VSUP
VBATF
n.c
AGND

DI
AO
AO
AI
AO
AO
AI
PWR
PWR
AO
AO
GND
AO
PWR
AI
GND

Function
High-side FET2 PWM control input (active high)
High-side FET3 PWM control input (active high)
Digital supply for IOs, current sense amplifier
and over current comparator
Current sense amplifier reference input
Current sense amplifier negative input
Current sense amplifier positive input
Current sense amplifier output
MISO output for SPI
Low-side FET2 PWM control input (active low)
CLK input for SPI
Low-side FET3 PWM control input (active low)
MOSI input for SPI
Bidirectional, serial diagnostics interface
CSB input for SPI
Enable input for gate driver outputs (active high)
Motor phase 2
High-side FET2 gate driver output
High-side FET2 bootstrap capacitor
Motor phase 3
High-side FET3 gate driver output
High-side FET3 bootstrap capacitor
Charge pump boosted supply output
Driver supply output for bootstrap capacitors
Low-side FET2 gate driver output
Low-side FET3 gate driver output
Driver ground
Charge pump floating capacitor
Power supply input (Battery input)
Battery voltage connection for VDS-monitoring
Not connected
Analog ground

Table 5-1. Pin Definitions and Functions

3901083100
Rev 4.1

Page 6 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Absolute Maximum Ratings

Parameter

Symbol

Power supply voltage

VVSUP, VBATF

Negative input current

Negative input current
Digital supply voltage
Analog input voltage
Analog output voltage
Digital input voltage
Digital input current
Digital output voltage
Output voltage
Output voltage
Input voltage on CPx pins
Input voltage on PHASEx pins
Maximum latch-up free
currentat any pin
ESD capability
Storage temperature
Junction temperature

Condition
t < 500ms (during load
dump)
Permanent (functional)

IVSUP
IVBATF
VVDD
VVREF, VIBM,
VIBP
VISENSE
VFETBx, VFETTx,
VEN
VICOM
VGATEBx, VREG
VGATETx
VCPx
VPHASEx
ILATCH
ESD
Tstg
TJ
Rth-JA

Thermal resistance package

Rth-JC

According to JEDEC JESD78,

AEC-Q100-004
Human Body Model

Min.

Max.

Unit

-0.3

45

-0.3
-15
-10
-0.3

28

5.5

V
mA
mA
V

-0.3

VDD+0.3

-0.3
-0.3
-10
-0.3
-0.3
-0.3
-0.3
-0.7

VDD+0.3
VDD+0.3
10
VDD+0.3
17
VREG+35
VREG+35
45

V
V
mA
V
V
V
V
V

-100

100

mA

-2
-55
-40

+2
150
175

kV
C
C

In free air on multilayer PCB

(JEDEC 1s2p)
Referring to center of
exposed pad

Typ.

37

K/W

10

K/W

Table 6-1. Absolute Maximum Ratings

Exceeding the absolute maximum ratings may cause permanent damage. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.

Operating Range

The electrical specifications are valid for the operating range below, unless otherwise specified.
Parameter
Power supply voltage range
Digital supply voltage range
Ambient temperature
Junction temperature

Symbol

Condition

VVSUP
VVDD
TA
TJ

Min.
4.5
3
-40
-40

Typ.

Max.

Unit

28
5.5
150
175

V
V
C
C

Table 7-1. Operating Range

3901083100
Rev 4.1

Page 7 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Electrical Specifications

The electrical specifications are valid for the operating range above, unless otherwise specified.
Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

18

4.5

18

28

30

mA

35

Power Supply VSUP

P.1

VSUP

P.4

Supply voltage range

Supply voltage
extended range low
Supply voltage
extended range high
Quiescent current from VSUP

P.5

Operating current from VSUP

ISUP_INT

P.2
P.3

P.6
P.7
P.8
P.9
P.10
P.11
P.12
P.13
P.14

Supply over voltage

threshold high
Supply over voltage
threshold low
Supply over voltage
hysteresis
Supply over voltage
debounce time
Supply under voltage
threshold high
Supply under voltage
threshold low
Supply under voltage
hysteresis
Supply under voltage
debounce time
Power on reset level

VSUP_ERL
VSUP_ERH
ISUP_SLEEP

Functional with decreased

gate drive voltage
Functional with decreased
gate drive voltage
VDD = Low
Pre-driver operation without
charge pump operation and
without switching

VSUP_OVH

Warning on ICOM

VSUP_OVL

ICOM released

VSUP_OVHY

30
0.4

V
1

VSUP_OV_DEB
VSUP_UVH

ICOM released

VSUP_UVL

Warning on ICOM

VSUP_UVHY

RVBATF_LEAK

Pre-driver is not in sleep

mode

V
V

0.5

VSUP_UV_DEB
Reset released on rising edge
of VSUP when VDD = high

5
0.2

VPOR

2.6

V
10

4.5

20

VVBATF
P.15

Internal leakage from

VBATF to GND
Temperature Warning

P.16
P.17

Over temperature
threshold high
Over temperature
threshold low

OVTH

Warning on ICOM

185

OVTL

ICOM released

168

On-Chip Oscillator
P.18

Oscillator frequency

3901083100
Rev 4.1

fOSC

Internal Oscillator

Page 8 of 38

6.8

9.2

Data Sheet
Nov/14

MHz

MLX83100
Automotive 2-Phase DC Pre-Driver

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

170

100
200

230

V/s
kHz

12

13

Charge Pump CP & VBOOST

P.19
P.20

Output slew rate

Charge pump frequency

VCP
fCP

P.21

Reverse polarity N-FET gatesource voltage (VBOOST-VSUP)

VGS_RPFET

P.22

Resistive load from VBOOST to

GND

RBOOST_LEAK

P.23

VBOOST under voltage

threshold high

VBOOST_UVH

P.24

VBOOST under voltage

threshold low

VBOOST_UVL

P.25

VBOOST over voltage

VBOOST_DIS

CP Mode 1
VSUP > 7V
IREG < 20mA
RTyp at room temperature
RMin at 150C TJ
(excl. RVREG_LEAK)
ICOM released
CP Mode 0 (VBOOST)

CP Mode 1 (VBOOST-VSUP)
Warning on ICOM
CP Mode 0 (VBOOST)
CP Mode 1 (VBOOST-VSUP)
Disable and discharge charge
pump at VSUP_OV

MOhm

6.1

7.2

5.6

6.7

40

mA

20

mA

13

13

13

Driver Supply VREG

IREG_CPMODE0
P.26

Load current on VREG

IREG_CPMODE1

P.27

P.28
P.29
P.30
P.31
P.32
P.33

Output voltage VREG

Internal resistive load from VREG

to GND
VREG over voltage
threshold high
VREG over voltage
threshold low
VREG over voltage
hysteresis
VREG under voltage
threshold high
VREG under voltage
threshold low

3901083100
Rev 4.1

VREG

RVREG_LEAK

VREG > 11V

EN_CP = 1
CP Mode 0
VREG > 11V
EN_CP = 1
CP Mode 1
CP Mode 0
VSUP > 8V
IREG < 40mA
CP Mode 0
7V< VSUP < 8V
IREG < 40mA
CP Mode 1
IREG < 20mA
RTyp at room temperature
RMin at 150C TJ

11

12

10
11

12

0.3

0.4

MOhm

VREG_OVH

Warning on ICOM

14.2

16.5

VREG_OVL

ICOM released

13.5

15.8

0.65

1.5

VREG_OVHY
VREG_UVH

ICOM released

7.2

8.1

VREG_UVL

Warning on ICOM

6.9

7.8

Page 9 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

IDD
VDD_RPD
VDD

Incl. ICOM current sourcing

300

VDD = 3.3V or 5V

200
3

20
370
5.5

mA
kOhm
V

VDD_UVH

ICOM released

2.55

2.95

VDD_UVL

Warning on ICOM

2.45

2.85

0.14

Digital Supply VDD

P.34
P.35
P.36
P.37
P.38
P.39
P.40
P.41
P.42

VDD operating current

VDD pull down resistance
VDD input voltage
VDD under voltage
threshold high
VDD under voltage
threshold low
VDD under voltage
hysteresis
VDD sleep voltage
threshold high
VDD sleep voltage
threshold low
VDD sleep voltage
hysteresis

3901083100
Rev 4.1

VDD_UVHY

0.08

0.10

VDD_SLEEPH

Out of sleep

2.1

2.7

VDD_SLEEPL

Go to sleep

1.6

2.1

0.80

VDD_SLEEPHY

0.45

Page 10 of 38

0.58

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

tr
tf

CLOAD = 1nF, 20% to 80%

CLOAD = 1nF, 80% to 20%

18
12

21
21

45
45

ns
ns

VSUP > 7V
-10mA, TJ = -40C
-10mA, TJ = 150C

7.2

12.0

21.0

Ohm

2.0

12.0

27.6

Ohm

VSUP > 7V
10mA, TJ = -40C
10mA, TJ = 150C

4.5

12.0

17.1

Ohm

6.0

15.0

27.6

Ohm

-0.33

-0.45

0.33

0.45

20

120

ns

-20

20

ns

+25%

15

Gate Drivers
P.43
P.44
P.45

P.46

P.47

Rise time
Fall time
Pull-up ON resistance
low-side pre-driver
Pull-up ON resistance
high-side pre-driver
Pull-down ON resistance
low-side pre-driver
Pull-down ON resistance
high-side pre-driver
Turn-on gate drive
peak current (sourcing)

RON_UP

RON_DN

IGON

P.48

Turn-off gate drive

peak current (sinking)

IGOFF

P.49

Propagation delay

tPDDRV

P.50

Propagation delay matching

tPDDRVM

P.51

Programmable dead time :

asynchronous internal delay
between high-side and low-side
pre-driver of one half bridge

tDEAD

P.52

Dead time matching between

different channels

tDEAD_TOL

VGS = 0V
VSUP > 7V
VGS = 12V
VSUP > 7V
From logic input threshold to
2V VGS drive output at no load
Transitions at the different
phases at no load condition
DEAD_TIME [ 2:0] =
000
001
010
011
100
101
110
111

-25%

-15
VDSMON[2:0] =

P.53

Programmable drain-source
voltage for monitoring of
external N-FETs

VVDS_MON

P.54

Programmable drain-source
monitor blanking time: Delay
between gate high and enabling
corresponding VDS monitor

tVDS_BL

P.55

Sleep gate discharge resistor

Rsgd

3901083100
Rev 4.1

0.00
0.51
0.80
1.10
1.67
2.30
3.40
6.90

000
001
010
011
100
101
110
111
VDS_BLANK_TIME[1:0] = 00
01
10
11
Internal resistance between
FET gate-source pins to
switch-off FET.
VDD = 0V (sleep mode)
VGS = 0.5V

Page 11 of 38

0.40
0.60
0.85
1.05
1.25
1.50
1.70
0.60
1.28
2.55
5.10

Disabled
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0.80
1.70
3.40
6.80

0.60
0.90
1.15
1.45
1.75
2.00
2.30
1.00
2.13
4.25
8.50

Data Sheet
Nov/14

kOhm

MLX83100
Automotive 2-Phase DC Pre-Driver

Parameter

Symbol

P.56

Trickle charge pump current

capability

ITCP

P.57
P.58
P.59

VGS under voltage threshold high

VGS under voltage threshold low
PWM frequency

VGS_UVH
VGS_UVL
fDR_PWM

P.60

Leakage from CPx - PHASEx

RCP_LEAK

Condition

VSUP > 12V

PHASEx = VSUP
CPx = PHASEx + 6.5V
ITCP,max @175C TJ
ITCP,min @-40C TJ
ICOM released
Warning on ICOM

RTyp at room temperature

RMin at 150C TJ

Min.

Typ.

Max.

Unit

-160

-25

42
36
5

20

70
63
100

%VREG
%VREG
kHz

0.75

Logic IOs - FET inputs

P.61

Digital input high voltage

VIN_DIG_H

P.62

Digital input low voltage

VIN_DIG_L

P.63
P.64

Input pull-up resistance

Input pull-down resistance

RIN_DIG_PU
RIN_DIG_PD

Minimum input voltage to be

treated as logical high
Maximum input voltage to be
treated as logical low
FETBx
FETTx

80

%VDD
20

%VDD

90
90

410
410

kOhm
kOhm

90

410

kOhm

-5.0
2.6
115
14.4
4096 /
fOSC

mA
mA
kHz
kHz

Logic IOs - EN input

P.65
P.66

Input pull-down resistance

Bridge disable propagation
delay

R_EN_PD
ENPR_DEL

EN
From bridge disable EN<0.2VDD
to VGS < 0.5V, CLOAD = 1nF

Logic IOs - ICOM

P.67
P.68
P.69
P.70
P.71

Pull-up current
Pull-down current
ICOM PWM frequency fast
ICOM PWM frequency slow
SPI start-up pulse duration on
ICOM to enter SPI mode

ICOMPU
ICOMPD
fICOMF
fICOMS
tSPI_SU

VICOM = 0V
VICOM = VDD

EN = Low
FETTx = Low, FETBx = High

-2.2
5.0
85
10.6
2048 /
fOSC

100
12.5

SPI Timing
P.72
P.73
P.74
P.75
P.76
P.77
P.78
P.79
P.80
P.81
P.82
P.83
P.84
P.85

SPI initial setup time

SPI clock frequency
Rise/fall times
CSB setup time
CSB high time
Clock high time
Clock low time
Data in setup time
Data in hold time
Data out ready delay
EEPROM read delay
EEPROM write delay
Operational temperature range
for EEPROM read
Operational temperature range
for EEPROM write

3901083100
Rev 4.1

tSPI_ISU
fSPI
tSPI_RF
tCSB_SU
tCSB_H
tCLK_H
tCLK_L
tDI_SU
tDI_H
tDO_R
tEE_RD
tEE_WR

2
500
200

CLK, CSB, MISO, MOSI

1
2
1
1
1
500
CLOAD at FETB1 < 50pF
EE_RD = 1
EE_WR = 1

6
12

TJ_EE_RD

Junction temperature

-40

175

T J_EE_WR

Junction temperature

-40

150

Page 12 of 38

500

s
kHz
ns
s
s
s
s
s
s
s
s
ms

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Current Sense Amplifier

P.86
P.87
P.88
P.89
P.90
P.91

Input offset voltage

Input offset voltage
thermal drift
Input common mode rejection
ratio DC
Input common mode rejection
ratio 1MHz
Input power supply rejection
ratio DC for VDD supply
Input power supply rejection
ratio 1MHz for VDD supply

VIS_IO

-7.6

7.6

mV

VIS_IO_TDRIFT

-10

10

V/C

ISCMRR_DC

60

dB

40

dB

ISPSRR_DC

60

dB

ISPSRR_AC

40

dB

ISCMRR_AC

Input differential voltage

within 100mV
Common mode [-0.5, 1.0] V

Current sense gain =

P.92

Closed loop gain

ISGAIN

P.93

Output settling time

ISSET

P.94
P.95

Output voltage range high

Output voltage range low
Output short circuit current to
P.96
ground
P.97 Gain bandwith (GBW)
P.98 Output slew rate
P.99 CM spike recovery
P.100 VREF voltage input

VISENSE_MAX
VISENSE_MIN
IISENSE_SC
ISGBW
ISSR
ISCM_REC
VREF

000
001
010
011
-3%
100
101
110
111
Amplified output to 99% of
final value after input change
ISENSE output max level
VDD -0.02
ISENSE output min level
GND
Output current saturation
level
6

8.0
10.3
13.3
17.2
22.2
28.7
37.0
47.8

+3%

1.0

VDD
GND+0.02

V
V

1.4

mA

8
CM spike = 1.5V, t=250ns
0

730
50

Table 8-1. Electrical Specifications

3901083100
Rev 4.1

Page 13 of 38

Data Sheet
Nov/14

MHz
V/s
ns
%VDD

MLX83100
Automotive 2-Phase DC Pre-Driver

MLX83100 Typical Performance Graphs

Temp -40C ; VREG unloaded

Temp -40C ; VREG loaded 1kOhm

Temp -40C ; VREG unloaded

Temp -40C ; VREG loaded 1kOhm

Temp 27C ; VREG unloaded

Temp 27C ; VREG loaded 1kOhm

Temp 27C ; VREG unloaded

Temp 27C ; VREG loaded 1kOhm

Temp 150C ; VREG unloaded

Temp 150C ; VREG loaded 1kOhm

Temp 150C ; VREG unloaded

Temp 150C ; VREG loaded 1kOhm

14

14

12

12

VREG [V]

VREG [V]

8.1

10

10

10

15

20

25

30

VSUP [V]

Figure 8-1. MLX83100 : Regulated Output Voltage vs. Supply

Voltage
Temp 25C

Temp -40C

Tenp 175C

30

30

25

25

20

20

15

10

Temp 25C

Temp 175C

15

10

0
0

10

15

20

25

30

10

Figure 8-3. MLX83100 : High-Side Driver FET RON Resistance vs.

Supply Voltage
Temp -40C

15

20

25

30

VSUP [V]

VSUP [V]

Temp 25C

Figure 8-4. MLX83100 : High-Side Driver FET ROFF Resistance vs.

Supply Voltage

Temp 175C

Temp -40C

30

30

25

25

20

20

LS FET Roff[Ohm]

LS FET Ron[Ohm]

12

Figure 8-2. MLX83100 : Regulated Output Voltage vs. Supply

Voltage

HS FET Roff[Ohm]

HS FET Ron[Ohm]

Temp -40C

10

VSUP [V]

15

10

Temp 25C

Temp 175C

15

10

0
0

10

15

20

25

30

VSUP [V]

10

15

20

25

30

VSUP[V]

Figure 8-5. MLX83100 : Low-Side Driver FET RON Resistance vs.

Supply Voltage

3901083100
Rev 4.1

Figure 8-6. MLX83100 : Low-Side Driver FET ROFF Resistance vs.

Supply Voltage

Page 14 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Block Diagram

Figure 9-1. Block Diagram

3901083100
Rev 4.1

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Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

10 Functional Description
10.1 Supply System
The MLX83100 is supplied via pins VSUP and VDD. The power supply VSUP supplies the internal operation of
the pre-driver, the charge pump and the voltage regulator used for the bootstrap based architecture. The
digital supply VDD supplies the IOs and the current sense amplifier.
Inputs
Outputs
Internal

EEPROM

VSUP

3.3V

VBG

RCO

Diagnostics

POR

VBOOST

CP

VREG

VDD

IOs

CSA

Drivers

Figure 10-1. Principle Organization of the Supply System

1.1.1

Power Supply - VSUP

The internal operation of the pre-driver is supplied from the power supply input pin VSUP. It supplies the
bandgap reference, power-on-reset system and internal 3.3V regulator. This 3.3V regulator in turn supplies
the EEPROM, RC-oscillator and diagnostics. For safety reasons the pre-driver provides integrated under
voltage and over voltage detection on VSUP
1.1.2

Charge Pump - VBOOST

The IC comprises a charge pump, supplied from VSUP, which allows full device operation down to 4.5V. The
charge pump boosted output voltage is available on VBOOST. This boosted voltage powers the voltage
regulator VREG used to supply the low-side drivers directly, and high-side drivers via the bootstrap
architecture. See Figure 1-1Figure 10-2 for the standard charge pump configuration where VBOOST is
regulated relative to ground. The charge pump will not be switching when VSUP > VREG + 2xVf, diode.
An alternative mode of operation for the charge pump supports the use of an external low drop N-FET for
reverse polarity protection. In this mode the charge pump boosts the output voltage relative to the supply
voltage instead of relative to ground, see application diagram in Figure 1-2. The disadvantage is an
additional amount of dissipation inside the driver to regulate VREG.
The charge pump architecture is a supply voltage doubler with feedback loop for stable output voltage
generation, as shown in Figure 10-2. It can be configured in EEPROM to either regulate the boosted output
voltage VBOOST relative to ground or relative to the supply voltage, see Figure 10-3 for the typical output
voltage. Furthermore the EEPROM configuration allows disabling the charge pump for applications not
requiring the low voltage operation, in order to reduce the overall power consumption.
For safety reasons the pre-driver provides integrated under voltage detection on VBOOST. In addition the
charge pump comprises a discharge switch in order to keep VBOOST output voltage in a safe operating area
in case of over voltage on the supply input pin. The discharge switch is activated as soon as the supply
voltage VSUP exceeds the VSUP_OVH threshold level and is deactivated when it drops below the VSUP_OVL
threshold. At the same time the charge pump is deactivated.

3901083100
Rev 4.1

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Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

EN_CP
0

CPMODE
x

Charge pump operation

Charge pump disabled
Charge pump configured to regulate VBOOST relative to ground,
to support low voltage operation.
Charge pump configured to regulate VBOOST relative to the
supply, to support the use of a reverse polarity N-FET.

Table 10-1. Pre-Driver Charge Pump Configuration Options

CPMODE

VSUP
EN_CP
fCP

Control
CP_FB

CP

VBOOST

Level shift
with
dead time
&
slope

VSUP

CPMODE

CP_DSCHG
VSUP

COMP
OPA

VBOOST_UV
COMP

Figure 10-2. Charge Pump Principle Schematic

Charge Pump and Voltage Regulator Output vs Power Supply Input

24
22
CP Mode 0 - VBOOST

20

Voltage [V]

18
CP Mode 1 - VBOOST

16
14
12

VREG

10
8
CPx-GATETx

4
4.0 V

5.0 V

6.0 V

7.0 V

8.0 V

9.0 V

10.0 V

11.0 V

12.0 V

V(VSUP) [V]
Figure 10-3. Charge Pump Output and Driver Supply

3901083100
Rev 4.1

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Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

1.1.3

Voltage Regulator - VREG

The voltage regulator regulates the power supply down to 12V, in order to supply the low-side gate drivers
and switch the external low-side N-FETs without gate-source over voltage at high battery voltages. The
regulated output voltage VREG further provides the bootstrap voltage for driving the high-side N-FETs.
For safety reasons the pre-driver provides integrated under voltage and over voltage detection on VREG.

12V
regulator

VREG

VBATF
Trickle
TopDRV
Charge
Pump

CPx

Top Driver
TopDRV

GATETx

PHASEx

GATEBx

Bottom
BotDRV
Driver

Ccpx

Rshunt

Figure 10-4. Voltage Regulator for Driver Supply VREG

1.1.4

Digital Supply - VDD

The MLX83100 comprises a current sense amplifier. The current sense amplifier and IOs are supplied from
the digital supply VDD.
For safety reasons the pre-driver provides integrated under voltage detection on VDD.
Note:
When supplying VDD with a limited output impedance (e.g. from a microcontroller IO) the performance of
the amplifier may be affected.

3901083100
Rev 4.1

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Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

1.1.5

Sleep Mode

Sleep mode is activated when the digital supply input VDD is pulled below VVDD sleep voltage
threshold low. In sleep mode the charge pump is disabled, all gate drivers are switched off and the current
consumption on VSUP is reduced. The pre-driver will wake-up as soon as the voltage level on VDD rises
above VVDD sleep voltage threshold high.
Pin Name
CP
VBOOST
GATEBx
GATETx
PHASEx
VREG
CPx
ISENSE
FETBx
FETTx
EN
ICOM

State in Sleep Mode

The charge pump is disabled.
Since the charge pump is disabled VBOOST is pulled to the supply voltage via the external
charge pump diodes.
In sleep mode, gate-discharge resistors (RSGD) between GATEBx and DGND are activated,
ensuring all low-side gate drivers are switched off
In sleep mode, gate-discharge resistors (RSGD) between GATETx and PHASEx are activated,
ensuring all high-side gate drivers are switched off
Phases are kept low with GATETx through the internal body diode of the pre-driver
Voltage regulator is disabled
Any charge that remains after VREG is disabled will leak to ground
Current sense amplifier is supplied from VDD, and thus not active
All IOs are supplied from VDD, and thus not active
Table 10-2. Drivers in Sleep Mode

Notes:
1. In case any of the digital input pins are externally pulled high while VDD is low, current will flow into
VDD via internal ESD protection diodes. This condition is not allowed.
2. When VDD is pulled low, also ICOM will go low. This should not be interpreted as a diagnostic
interrupt.
CPx

GATETx
RSGD
PHASEx
VREG

GATEBx
RSGD

Figure 13-1-5. Drivers in Sleep Mode

3901083100
Rev 4.1

Page 19 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

10.2 Gate Drivers

1.1.6

PWM Input Control Logic FETBx & FETTx

Each of the 4 external N-FETs can be controlled independently via the 4 digital PWM input pins: FETBx and
FETTx. However, the digital logic provides the option to control the 2 external half bridges with only 2
control signals, by shorting high-side and low-side PWM input pins for each half bridge.
The IC provides internal shoot through protection through the digital logic preventing the simultaneous
activation of both high-side and low-side gate driver of the same half bridge. An additional dead time can be
programmed to ensure high-side (low-side) N-FET is fully switched off, before switching on the
complementary low-side (high-side) N-FET.
For safety reasons the pre-driver provides integrated drain-source and gate-source monitoring blocks for
each of the 4 external N-FETs.

FETTx

Dead Time

GATETx

PHASEx
EN

FETBx

Dead Time

GATEBx

Figure 10-5. Input Control Logic of the Driver Stage

1.1.7

Enable Input EN

The enable input pin EN enables the gate driver outputs when set high. When reset, all gate driver outputs
are pulled to ground, switching off all external N-FETs. This enable pin can be used by the microcontroller to
disable all drivers in case of any fault detection.
While EN is low, the programming of the EEPROM via SPI can be initiated by pulling ICOM low for the SPI
start-up time specified by tSPI_SU.
1.1.8

Gate Driver Supply and Bootstrap Architecture VREG & CPx

The voltage regulator regulates the power supply voltage down to 12V. The regulated voltage is used to
directly supply the low-side drivers.
To provide sufficient supply voltage for the high-side drivers a bootstrap architecture is used. When the lowside N-FET is switched on, the phase voltage will be pulled low and the bootstrap capacitor is charged from
the VREG buffer capacitor through the bootstrap diode. Afterwards, if the low-side N-FET is switched off
and the high-side N-FET is switched on, the charge of the bootstrap capacitor is used to supply sufficient
gate drive voltage to the high-side N-FET. The integrated trickle charge pump assures the bootstrap
capacitor will not be discharged, and allows 100% PWM operation.

3901083100
Rev 4.1

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Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

10.3 Integrated Current Sense Amplifier and Over Current Comparator

The IC comprises an integrated fast, high-bandwidth, low offset current sense amplifier.
The current sense amplifier is supplied from the digital supply. It senses the voltage over the low-side shunt,
amplifies it with the gain programmed in EEPROM and adds the offset provided on VREF. The output of the
amplifier is available on ISENSE.

VDD

VREF

IBP
ISENSE

OPA

OPA

IBM

Figure 10-6. Current Sense Amplifier

3901083100
Rev 4.1

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Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

10.4 Protection and Diagnostic Functions

1.1.9

Power Supply Over Voltage Shutdown (VSUP_OV)

The pre-driver has an integrated VSUP over voltage shut down to prevent destruction of the IC at high
supply voltages.
1.1.10

Power Supply Under Voltage Warning (VSUP_UV)

The pre-driver has an integrated VSUP under voltage detection. The diagnostics interface will give a warning
to the microcontroller. It is the responsibility of the microcontroller to take action in order to ensure reliable
operation.
1.1.11 Digital Supply Under Voltage Warning (VDD_UV)

The pre-driver has an integrated VDD under voltage detection. The diagnostics interface will give a warning
to the microcontroller. It is the responsibility of the microcontroller to take action in order to ensure reliable
communication between microcontroller and pre-driver.
1.1.12 VBOOST Under Voltage Warning (VBOOST_UV)

The integrated charge pump boosts the supply voltage in low voltage operation on the VBOOST output.
There is an under voltage detection on VBOOST to warn the microcontroller the charge pump is not ready.
It is the responsibility of the microcontroller to take action in order to ensure reliable motor operation.
1.1.13 Gate Driver Supply Over Voltage Warning/Shutdown (VREG_OV)

The MLX83100 comprises an integrated VREG over voltage detection. The reaction of the pre-driver on this
VREG_OV event depends on the status of the Bridge Feedback bit in EEPROM. If this VREG_OV_BF_EN bit is
set the pre-driver will disable all gate drivers, switching off all external N-FETs. If the bit is reset it will just
give a warning to the microcontroller.
VREG_OV_BF_EN
0
1

Pre-driver reaction on VREG_OV event

VREG_OV is reported on ICOM, but the drivers remain active
VREG_OV is reported on ICOM and the drivers are disabled

Table 10-3. Pre-Driver EEPROM Configuration for VREG Over Voltage Detection

3901083100
Rev 4.1

Page 22 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

1.1.14 Gate Driver Supply Under Voltage Warning (VREG_UV)

The pre-driver detects when the regulated voltage drops below the under voltage threshold. The
diagnostics interface will give a warning to the microcontroller. It is the responsibility of the microcontroller
to take action in order to ensure reliable switching of the external N-FETs, since the VREG voltage directly
supplies the low-side gate drivers.
1.1.15 Gate Source Voltage Monitoring Warning (VGS_UV)

In order to ensure reliable switching of the high-side N-FETs, the MLX83100 comprises gate-source monitors
for each of the high-side N-FETs. In case of an under voltage, the diagnostics interface will give a warning to
the microcontroller, if the gate-source comparators are enabled in EEPROM. It is the responsibility of the
microcontroller to take action in order to ensure reliable switching of the high-side gate drivers.
1.1.16 Over Temperature Warning (OVT)

If the junction temperature exceeds the specified threshold, a warning will be communicated to the
microcontroller. The pre-driver will continue in normal operation. It is the responsibility of the
microcontroller to protect the IC against over temperature destruction.
1.1.17 Shoot Through Protection and Dead Time

The pre-drivers internal implementation guarantees that low-side and high-side N-FET of the same external
half bridge cannot be conducting at the same time, preventing a short between the supply and ground. In
addition the pre-driver provides a programmable dead time in EEPROM. The dead time sets the delay
between the moment when the high-side (low-side) N-FET is switched off, and the moment when the
complementary low-side (high-side) N-FET can be switched on.
1.1.18 Drain-Source Voltage Monitoring Warning/Shutdown (VDS_ERR)

The MLX83100 provides a drain-source voltage monitoring feature for each external N-FET to protect
against short circuits to ground or supply. The drain-source voltage comparator can be enabled or disabled
in EEPROM.
The drain-source voltage monitor for a certain external N-FET is activated when the corresponding input is
switched on and the dead time has passed. An additional blanking time can be programmed in EEPROM. If
the drain-source voltage remains higher than the VDS monitor threshold voltage, the VDS error is raised.
The threshold voltage is configurable in EEPROM.
The reaction of the pre-driver on a VDS error can be configured in EEPROM with the Bridge Feedback bit. If
this bit is set the pre-driver automatically disables the drivers when a VDS error is detected. If the bit is
reset, the drivers remain active. In both cases the VDS error will be reported to the microcontroller.
VDS_COMP_EN
0
1
1

VDS_BF_EN
x
0
1

Pre-driver reaction on VDS-Error event

Any VDS error is ignored and no error is reported on ICOM
VDS_ERR is reported on ICOM, but the drivers remain active
VDS_ERR is reported on ICOM and the drivers are disabled

Table 10-4. Pre-Driver EEPROM Configuration for Drain-Source Error Detection

3901083100
Rev 4.1

Page 23 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

1.1.19 EEPROM Error Warning (EEP_ERR)

To ensure reliable communication with EEPROM the pre-driver provides an automatic single bit error
correction and double error detection. If two bits in the addressed word are bad the EEPROM gives the
EEP_ERR warning, indicating a double error was detected.
1.1.20 Diagnostics Interface ICOM

All diagnostic events described above are reported to the microcontroller via a single pin, ICOM. In normal
operation, when no error is detected, ICOM is default high.
The ICOM interface acts as a serial interface that feeds back detailed diagnostics information. If an error is
detected, ICOM goes from default high to communicating a PWM-signal. The speed of this PWM signal
depends on the EEPROM configuration of bit PWM_SPEED. Each error corresponds to a duty cycle with a 5bit resolution. Thus the microcontroller can distinguish different errors by reading the duty cycle, see Table
10-7.
PWM_SPEED
0
1

Pre-driver
Slow mode: for slow microcontrollers
Fast mode : for fastest response of microcontroller

Table 10-5. Pre-Driver EEPROM Configuration for Diagnostics Communication

3901083100
Rev 4.1

Page 24 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

The duty cycle is transmitted until the microcontroller sends the acknowledgement. This is done by pulling
ICOM low for more than a PWM-period, tAck > tICOM. At each ICOM falling edge the pre-driver checks the
actual voltage on ICOM in order to detect an acknowledgement. After acknowledgement the duty cycle of
the next error is transmitted, if multiple errors were detected. All errors have been reported when the endof-frame duty cycle is send. When all errors are physically removed, and the end-of-frame message is
acknowledged by the microcontroller, ICOM returns to its default high state.

Physical
Error

ICOM

Default high

Error Information

End-of-Frame

Default high

MCU
Acknowledge

Figure 10-7. ICOM Diagnostics Communication

Notes:
1. When VDD is pulled low to put the pre-driver in sleep mode, ICOM will go low as well. This should
not be interpreted as a diagnostic interrupt. As soon as VDD goes high, the pre-driver wakes-up and
ICOM will return to its default high state.
2. At POR it is possible that the voltages on VSUP and VREG were not above the under voltage
thresholds (e.g. due to charging of external capacitors).
It is possible that ICOM reports these under voltage errors after POR. This implies that the
microcontroller has to acknowledge these errors before ICOM will be in its default high state and
the pre-driver is ready for normal operation.
The drivers are disabled when
The drivers are enabled again as soon as
An error condition is detected for which the
hardware protection is activated
VSUP_OV
The microcontroller acknowledges the error
VREG_OV
VDS_ERR
VDD = Low (sleep mode)
VDD = High (wake-up)
EN = Low
EN = High
Table 10-6. Pre-Driver Output State Summary

3901083100
Rev 4.1

Page 25 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

VDD

VDD

Microcontroller

Pre-Driver
<5mA

ICOM_OUT

Interrupt / Read duty cycle

ICOM

Acknowledge

Cload
<100pF

<5mA

ICOM_IN

Figure 10-8. ICOM Diagnostics Interface

In case multiple errors occur at the same time, the priority is as defined in Table 10-7. The highest priority is
0 and 16 is the lowest priority.
Priority Error Event
11
ICOM_EOF

10

VDS_ERR

% Duty Cycle
93.5

82.5

Debounce Time
n/a

2 s

9
8
7
6
5
4

EEP_ERR
VDD_UV
VSUP_OV
VSUP_UV
OVT
VREG_UV

55.0
49.5
44.0
38.5
33.0
27.5

n/a
8 s
2 s
8 s
2 s
16 s

VGS_UV

22.0

2 s

VBOOST_UV

16.5

16 s

VREG_OV

11.0

2 s

Description
End of frame
VDS Error = VDS_T2 | VDS_T3 | VDS_B2 |
VDS_B3
This event can be
VDS_COMP_EN = 0

masked

by

setting

To avoid erroneous triggering due to switching

there is a programmable blanking time on top
of the debounce time: VDS_BLANK_TIME[1:0].
EEPROM dual error detected
VDD under voltage
VSUP over voltage
VSUP under voltage
OVT over temperature
VREG under voltage
VGS under voltage
This event can be
VGS_UV_COMP_EN = 0
VBOOST under voltage
VREG over voltage

masked

by

setting

This event can be

VGS_UV_COMP_EN = 0

masked

by

setting

Table 10-7. Overview Diagnostics over ICOM with Priority Definitions

3901083100
Rev 4.1

Page 26 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

10.5 EEPROM Configuration

The MLX83100 provides an EEPROM for configuration of the IC, the current sense amplifier and over
current comparator, protection and diagnostic functions. This allows to optimize the pre-drivers operation
for the application requirements. The configuration can be done at customer production testing by using
the PTC-04, or by the microcontroller via a custom program interface.
The EEPROM features single error correction and double error detection.
1.1.21 Memory Map

The MLX83100 comprises 6 bytes of EEPROM for user configurability. The first two bytes are not used for
the internal configuration of the pre-driver, and can thus be used by the customer for traceability purposes.
The other 4 bytes are used for configuration of the current sense amplifier and configuration of the
diagnostics.
The pre-driver is programmed with default settings per table below.
SPI
Addr.

ED7

ED6

ED5

ED4

ED3

ED2

ED1

ED0

Res.

0x00

Res.

0x00

DEAD_TIME[2:0]

VDSMON[2:0]

CPMODE

Res.

0x7C

011

111

VDS_BLANK_TIME[1:0]

0xA6

10

PWM_
SPEED
1

CUR_GAIN[2:0]

Res.

011

0xFC

VREG_OV_
BF_EN
1

VDS_
BF_EN
1

VDS_
COMP_EN
1

VGS_UV_C
OMP_EN
1

5 (-6-7)

SPI_EN

Res.

0xC0

EN_TCP

EN_CP

Res.

Res.

Table 10-8. EEPROM Memory Map and Default Configuration

3901083100
Rev 4.1

Page 27 of 38

Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

Bit Name
Description
Configuration of the IC
Defines the mode of operation of the internal charge pump
1: VBOOST voltage is regulated relative to VSUP
CPMODE
for reverse polarity N-FET protection
0: VBOOST voltage is regulated relative to GND
for low voltage operation with minimal power consumption
Defines the status of the pre-drivers internal charge pump
EN_CP
1: Charge pump active
0: Charge pump not active
Defines the status of the pre-drivers trickle charge pump
EN_TCP
1: Trickle charge pump active
0: Trickle charge pump not active
Defines the accessibility of EEPROM through the custom SPI interface
SPI_EN
1: EEPROM accessible via the custom SPI interface
0: EEPROM not accessible via the custom SPI interface
Configuration of the Current Sense Amplifier and Over Current Comparator
CUR_GAIN[2:0]
Defines the gain of the current sense amplifier
Configuration of the Protection and Diagnostic Functions
Defines the diagnostics communication speed on ICOM
PWM_SPEED
1: Fast mode for fastest response of microcontroller
0: Slow mode for low-end microcontrollers
Defines the pre-drivers reaction on a regulated supply over voltage:
VREG_OV_BF_EN
1: Report VREG_OV on ICOM and disable gate drivers
0: Report VREG_OV on ICOM without effect on gate drivers
Defines the dead time between switching off high-side (low-side) N-FET
DEAD_TIME[2:0]
and switching on complementary low-side (high-side) N-FET
VDSMON[2:0]
Defines the threshold level for the VDS monitoring of the external N-FETs
Defines the duration of the VDS blanking time after switching on the NVDS_BLANK_TIME[1:0]
FET
Defines the status of the pre-drivers drain-source monitoring
VDS_COMP_EN
1: Drain-source comparators active
0: Drain-source comparators not active
Defines the pre-drivers reaction on a drain-source fault:
VDS_BF_EN
1: Report VDS_ERR on ICOM and disable gate drivers
0: Report VDS_ERR on ICOM without effect on gate drivers
Defines the status of the pre-drivers gate-source monitoring
VGS_UV_COMP_EN
1: Drain-source comparators active
0: Drain-source comparators not active

Default

011

1
011
111
10
1

Table 10-9. EEPROM Bit Description

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Rev 4.1

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Data Sheet
Nov/14

MLX83100
Automotive 2-Phase DC Pre-Driver

1.1.22 SPI Program Mode

The EEPROM memory can be accessed through a custom SPI interface. It allows the user to read/program
the EEPROM by the microcontroller in the application. This custom interface re-uses the low-side driver pins
for SPI communication.
Since the same pins are used for both reading/writing the EEPROM and for controlling the motor, the
EEPROM is only accessible when the motor is not running. Furthermore it is necessary to apply a certain
sequence of conditions before the pre-driver will enter the SPI Program Mode. Once in this mode, the
EEPROM can be accessed for reading and writing, until the IC enters Normal Mode again and motor
operation is possible.
EN
FETTx

Driver Logic

FETBx
MISO
ICOM

Custom
SPI

EEPROM

Diagnostics
Figure 10-9. Custom SPI Read/Program Interface

Pin Name
ICOM

SPI Signal
CSB

FETB3

MOSI

FETB2

CLK

MISO

MISO

Description
SPI-frames are defined by CSB low
The MOSI (Master Out Slave In) shift register is reading in data on
the rising edge of CLK
Clock input, each SPI-frame has to consist of 16 clock periods
The MISO (Master In Slave Out) output is guaranteed to be stable
while the CLK is low
Table 10-10. SPI Signals

1.1.22.1 Entering SPI Program Mode

The MLX83100 will enter from Normal Mode into SPI Program Mode when all below conditions are
satisfied:

EN = 0
FETTx = Low (High-side FET inputs off)
FETBx,MISO = High (Low-side FET inputs off)
ICOM
o Any pending errors have been removed and acknowledged, so ICOM is in default high state
o A low level pulse is applied on ICOM for a time tSPI_SU.

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Automotive 2-Phase DC Pre-Driver

1.1.22.2 Exiting SPI Program Mode

The MLX83100 will exit the SPI Program Mode when the enable input EN is pulled high. Similar to when
the MLX83100 comes out of POR, after leaving the SPI Program Mode the pre-driver will be blocked until
the data have been copied to the registers. This means that before entering Normal Mode any ongoing
EEPROM write will be completed and the EEPROM state machine will copy all EEPROM contents into
registers. During this time ICOM will be kept low. ICOM returning to its default high state signals when predriver is ready for normal operation.
1.1.22.3 Protocol

Once the IC is in SPI Program Mode the microcontroller can read/write the EEPROM, following the
protocol depicted below.

EE_READY=1
Data in
DATA latch

READ INSTRUCTION
WRITE INSTRUCTION

If COMM_ERR = 0
Start EE_RD
Latch data into
MOSI register on
CLK Rising edge

EE_READY=1
Data in
DATA LATCH register

Copy latched DATA into

MISO [10:4]

If comm_err = 0
Start EE_WR

>tEE_RD

Copy latched DATA

(not read from EEPROM!)
into MISO [10:4]

> tEE_WR

CSB
CLK
MOSI
MISO

n[0]

n[1]

n[0]

n[2]

n[15]

n[1]

n[15]

n[1]

Data on MISO stable

(valid) while CLK is
LOW

n+1[0]

n+1[1]

n+1[0]

n+1[2]

n[1]

n+1[15]

n+1[1]

n+1[15]

MISO[10:4] contains DATA

requested in previous Read
instruction

n+2[0]

n+2[1]

n+2[0]

n+2[1]

MISO[10:4] contains previous

MOSI[10:4] DATA

Figure 10-10. SPI Protocol (LSB first)

1.1.22.4 Registers Description

MOSI [15:0]
Bit [15]
MOSI_PAR
Bit [7]
MISO[15:0]
Bit [15]
MISO_PAR
Bit [7]

Bit [14]
Bit [13]
x
x
Bit [6]
Bit [5]
MOSI_DATA [4:1]
Bit [14]
Bit [13]
COMM_ERR EE_READY
Bit [6]
Bit [5]
MISO_DATA [4:1]

Bit [12]
Bit [11]
CMD [1:0]
Bit [4]
Bit [3]
x
Bit [12]
Bit [11]
CMD [1:0]
Bit [4]
Bit [3]
x

Bit [10]

Bit [9]
Bit [8]
MOSI_DATA [7:5]
Bit [2]
Bit [1]
Bit [0]
ADDRESS [2:0]
Bit [10]

Bit [9]
Bit [8]
MISO_DATA [7:5]
Bit [2]
Bit [1]
Bit [0]
ADDRESS [2:0]

Table 10-11. MOSI/MISO Registers: Frame Description

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Automotive 2-Phase DC Pre-Driver

Bit
ADDRESS

Description
Address of the byte in EEPROM that needs to be read/written to.
In case of write command, the data that needs to be written. Dont care for any read
command.
In case previous command was write instruction, it returns the data that was written. In
case of a read instruction, it returns the data read from EEPROM.
Read/Write command
00: EE_RD: Read command
01: EE_WR: Write command
10: EE_RDAW1
11: EE_RDAW2
Reading/writing the EEPROM takes a certain time, specified by tEE_RD and tEE_WR
respectively. These times define the minimum time CSB (ICOM) has to remain high
between two SPI-frames in order to finish the read/ write action.

MOSI_DATA[7:1]
MISO_DATA[7:1]

CMD [1:0]

As soon as the read/write action starts, the EE_READY bit is reset. After completion of
the read/write action the bit is set.

EE_READY

If the read/write delay between SPI-frames was long enough to execute the read/write
action, the EE_READY bit will thus be set, signaling the read/write action was finished. If
the time was too short, the bit will still be 0.
This bit indicates if the previous MOSI-frame was received correctly. If no
communication error occurred the bit will be reset, and the read/write action was
started as soon as CSB was pulled high.
COMM_ERR

If a communication error occurred in the previous MOSI-frame the read/write command

was not executed. Possible communication errors are:
Odd parity bit was set incorrect
Number of clock periods was not equal to 16

MOSI_PAR,
MISO_PAR

Odd parity bit of the current MOSI/MISO frame.

Table 10-12. MOSI/MISO Registers: Bit Description

MOSI

15

14

13

[11:12]

[10:4]

[2:0]

MOSI_
PAR

CMD[1:0]

MOSI_DATA[6:0]

ADDRESS[2:0]

CLK COUNTER=16

COMM
_ERR

EEPROM

Latches

MISO

MISO_ COMM
PAR
_ERR

EE_
READY

EE_
READY

DATA[6:0]

CMD[1:0]

MISO_DATA[6:0]

ADDRESS[2:0]

Figure 10-11. MOSI/MISO Registers and Relation to Internal Data Latches

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Automotive 2-Phase DC Pre-Driver

1.1.22.5 Read Instruction

In order to read one of the EEPROM bytes, the microcontroller should compose the MOSI(N) frame
according to Table 10-11 with the address it wants to read, the read command and set the odd parity bit in
a correct way.
After transmission of this MOSI(N)-frame and when the CSB signal is pulled high, the pre-driver will start to
read the data at the specific address. If CSB is kept high long enough for the pre-driver to execute the read
action, it will transmit the read data on the next MISO(N+1)-frame.
The data in this MISO(N+1)-frame is valid only if
COMM_ERR = 0 :
no communication error was detected on the previous MOSI(N)-frame
EE_READY = 1 :
the read delay was long enough to finish the read
MISO_PAR = correct : the MISO(N+1)-frame has a correct odd parity bit
1.1.22.6 Write Instruction

The MLX83100 provides different configuration options through the EEPROM programming. In order to
program one of the EEPROM bytes, the microcontroller should compose the MOSI(N) frame according to
Table 10-11 with the address and data it wants to write, the write command and set the odd parity bit in a
correct way.
After transmission of this MOSI(N)-frame and when the CSB signal is pulled high, the pre-driver will start to
write the data at the specific address. If CSB is kept high long enough the pre-driver will be able to complete
the write instruction.
In total three verification steps are possible in order to ensure successful writing of the EEPROM. On the
first MISO-frame after the write command, it can be checked if the write command is received correctly and
the correct address and data are used. In the next two MISO-frames the data written in EEPROM can be
read in order to guarantee the desired data has been written in EEPROM

Verification Step 1: Correct receive of the write instruction using the MISO(N+1)-frame
o COMM_ERR = 0 :
no communication error detected on MOSI(N)-write command
o EE_READY = 1 : the write delay was long enough to finish the write instruction
o MISO_PAR = correct : the MISO(N+1)-frame has a correct odd parity bit
o MISO_DATA(N+1) = MOSI_DATA(N) : the correct data was used for the write instruction

Verification Step2: EE_RDAW1 using the MISO(N+2)-frame

o COMM_ERR = 0 :
no communication error detected on MOSI(N+2)-RDAW1 command
o EE_READY = 1 : the read delay was long enough to finish the read instruction
o MISO_PAR = correct : the MISO(N+2)-frame has a correct odd parity bit
o MISO_DATA(N+2)
=
MOSI_DATA(N)
:
the
correct
data
is
written

Verification Step3: EE_RDAW2 using the MISO(N+3)-frame

o COMM_ERR = 0 :
no communication error detected on MOSI(N+3)-RDAW2 command
o EE_READY = 1 : the read delay was long enough to finish the read instruction
o MISO_PAR = correct : the MISO(N+3)-frame has a correct odd parity bit
o MISO_DATA(N+3) = MOSI_DATA(N) : the correct data is written

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Automotive 2-Phase DC Pre-Driver

11 ESD Protection
VBATF

VSUP

CP

VBOOST

VREG

VDD

55V

18.5V

8V

Supply ESD Connections

AGND

55V

DGND

DGND

DGND

DGND

Gate Driver ESD Connections

55V

DGND

DGND

Digital IO ESD Connections

CPx

VREG

GATETx

GATEBx

VDD

VDD

VDD

18.5V

FETTx

FETBx
MISO

PHASEx

ICOM

EN
18.5V

10V

DGND

DGND

DGND

DGND

VDD

VDD

DGND

DGND

DGND

Current Sense Amplifier ESD Connections

VDD
IBP

ISENSE

OPA

IBM

OCIN

VREF

9V

DGND

DGND

DGND

DGND

Figure 11-1. Principle Schematic highlighting ESD Connections

Note:
All pins are referenced to the driver ground DGND as depicted in the picture above, but only for the ESD
protection.

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Automotive 2-Phase DC Pre-Driver

12 Package Information
12.1 Package Marking
Product name :
Lot number:
Date code:

MLX83100
ZZZZZZZZ
YYWW

format free
year and week

MLX83100
ZZZZZZZZ
YYWW

Figure 12-1. MLX83100 Package Marking TSSOP28-EP (4.4x9.7 mm, 28 Leads)

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Automotive 2-Phase DC Pre-Driver

12.2 Package Data TSSOP28-EP (4.4x9.7mm, 28 Leads)

A
Min
Nom.
Max. 1.10

A1
0.05
0.15

A2
0.85
0.90
0.95

D
9.70
9.80
9.90

E
4.30
4.40
4.50

6.4
0.65
B.S.C. B.S.C.

L
0.50

b
0.19

c
0.09

0.75

0.30

0.20

P
5.4
5.5
5.6

P1
2.9
3.0
3.1

Table 12-1. Mechanical Dimensions: TSSOP28 4.4x9.7mm (All dimensions given in mm)

Figure 12-2. Package Drawing TSSOP28-EP (4.4x9.7mm, 28 Leads)

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Automotive 2-Phase DC Pre-Driver

13 Standard information regarding manufacturability of Melexis products with different

soldering processes
Our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity level according to
following test methods:

Reflow Soldering SMDs (Surface Mount Devices)

IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount
(classification reflow profiles according to table 5-2)
EIA/JEDEC JESD22-A113
Preconditioning
of
Nonhermetic
Surface
Mount
Devices Prior
to
Reliability
(reflow profiles according to table 2)

Devices

Testing

Wave Soldering SMDs (Surface Mount Devices) and THDs (Through Hole Devices)
EN60749-20
Resistance of plastic- encapsulated SMDs to combined effect of moisture and soldering heat
EIA/JEDEC JESD22-B106 and EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Iron Soldering THDs (Through Hole Devices)
EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Solderability SMDs (Surface Mount Devices) and THDs (Through Hole Devices)
EIA/JEDEC JESD22-B102 and EN60749-21
Solderability
For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature,
temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon
with Melexis.
The application of Wave Soldering for SMDs is allowed only after consulting Melexis regarding assurance of adhesive
strength between device and board.
Melexis recommends reviewing on our web site the General Guidelines soldering recommendation
(http://www.melexis.com/Quality_soldering.aspx) as well as trim&form recommendations (http://www.melexis.com/
Assets/Trim-and-form-recommendations-5565.aspx).
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information
on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of the use of certain
Hazardous Substances) please visit the quality page on our website: http://www.melexis.com/quality.aspx

14 ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.

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Automotive 2-Phase DC Pre-Driver

15 Disclaimer
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the
information set forth herein or regarding the freedom of the described devices from patent infringement.
Melexis reserves the right to change specifications and prices at any time and without notice. Therefore,
prior to designing this product into a system, it is necessary to check with Melexis for current information.
This product is intended for use in normal commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment are specifically not recommended without additional
processing by Melexis for each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be
liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential
damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
Melexis rendering of technical or other services.
2014 Melexis NV. All rights reserved.

16 Contact Information
For the latest version of this document, go to our website at
www.melexis.com
Or for additional information contact Melexis Direct:

Europe, Africa, Asia:

America:

Phone: +32 1367 0495

E-mail: sales_europe@melexis.com

Phone: +1 248 306 5400

E-mail: sales_usa@melexis.com

ISO/TS 16949 and ISO14001 Certified

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MLX83100
Automotive 2-Phase DC Pre-Driver

17 History of Changes
Revision
1.0
1.1
1.2
2.0
2.1
2.2

2.3

3.0
3.1
4.0
4.1

3901083100
Rev 4.1

Date
Description
21-12-12 First draft
21-12-12 Driver related parameters updated
Protection and diagnostic functions updated
15-01-13
Trickle Charge Pump included
26-02-13 First Release
06-05-13 Max voltage on phase pins updated
04-12-13 Entering SPI mode by disabling all 6x FET input signals
Abs. max. rating updated
Block diagram and application diagrams updated
01-03-14 Exposed pad size confirmed
Qualification for TA = 150C
Changed ICOM duty cycle for VDS_ERR from 5.5% to 82.5%
09-05-14 General update according to new template
Drain-source monitor blanking
Trickle charge pump current capability
24-07-14
Largest dead time value
ICOM pull-up current
31-07-14 Performance graphs added
12-11-14 Ordering information example corrected

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Data Sheet
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