ELEN 665 (Edgar Snchez-Sinencio)

Analog and Mixed-Signal Center

Frequency Synthesizers for

Communication Systems

Part of this material came from courtesy of Ari Valero

1

Outline

Introduction
Linear model
Charge Pump PLL
Performance Metrics
Design Methodology

What is a PLL?
From a communications point of view, a phase-locked
loop is an optimum phase estimator
For an input r(t)=Asin(t + ), the PLL provides an
estimate Asin(t + ML)

How does it work?

Inject sinusoidal signal into the reference input
- The internal oscillator locks to the reference
- Frequency and phase differences between the reference
and internal sinusoid = k or 0
- Internal sinusoid then represents a filtered version of the
reference sinusoid

Where is it used?
Frequency Synthesis
Reference frequency for modulation and
demodulation
Clock reference
Radio, Television

Clock Recovery
Serial interfaces (Computers, optical networks)

FM demodulation
Radio

What does it look like?

f

in

Phase
Detector

Loop
Filter

f
VCO

out

Phase Detector (PD). Nonlinear block that provides the phase

difference between the input and oscillating signal
Loop Filter (LPF). Eliminates high order harmonics of PD output
and helps to stabilize the loop
Voltage Controlled Oscillator (VCO). Nonlinear device that
generates a sinusoidal signal whose frequency is controlled by its
DC input.
Feedback interconnection. The output of the VCO is fed to the
Phase Detector to generate a phase error signal. This phase error
signal controls the oscillation frequency of the VCO.

How can we implement a

Frequency Synthesizer with a PLL?
If a frequency divider is introduced in the feedback
interconnection, the frequency of the reference input
is multiplied by the feedback factor at the output of
the PLL
fin

Phase
Detector

Loop
Filter

Frequency
Divider

fout
VCO

From a fixed reference frequency (fin) a

large set of output frequencies (fout)
can be generated

f out = N f in
N Integer
->
N Fractional ->

Integer-N Frequency Synthesizer

Fractional-N Frequency Synthesizer

Linear Model
A PLL depends on nonlinear
operations to work properly

To analyze its behavior we need to

limit the analysis to the locked state

The following phase domain model

provides a way to study the
characteristics of operation of the loop

in
div

Kpd(in-div)
+

Kpd

G(s)

KVCO
s

The loop is considered locked when

the phase and frequency of the
feedback (divided VCO output) is
exactly equal to the average phase
and frequency of the input
out

The output of the VCO is:

fVCO (t ) = KVCOVctrl (t )
Integrating both sides
t

1
N

The output of the phase detector is:

VPFD = K PD

VCO (t ) = KVCO Vctrl (t )dt

0

In s-domain the VCO transfer

function becomes:

GVCO ( s ) =

VCO ( s ) KVCO
=
Vctrl ( s )
s

Where the phase difference is:

The Loop Filter transfer function:

= in div

G (s )

PLL Transfer Function

The closed loop transfer function:

H out ( s ) =

out ( s )
K PD KVCO G ( s )
=N
in ( s )
Ns + K PD KVCO G ( s )

The transfer function from phase error to

output:

H ( s ) =

out ( s )
K VCO G ( s )
=N
( s )
Ns + K PD K VCO G ( s )

The order of a PLL is defined by

the number of poles in the open
and closed loop transfer functions
and the type of a PLL indicates the
number of perfect (lossless)
integrators in the loop

Hold Range: the frequency range over which the PLL is able to statically maintain phase
tracking: H = KPDKVCOG(0).
Lock Range: the frequency range within which the PLL locks within one single-beat note
between the reference frequency and output frequency: L KPDKVCOG().
The Pull-In and Pull-Out Range: The pull-in range, P, is defined as the frequency range
in which the PLL will always become locked. The pull-out range, PO, is defined as the
limit of dynamic stability for the PLL. No simple relationships for these.

Type I PLL
For a Type-I PLL with different Loop Filters G(s) we have the following responses
H out1 ( s ) =

G ( s ) = G1 ( s ) = 1

K PD KVCO
out ( s )
=N
in ( s )
Ns + K PD KVCO

n =
G ( s) = G2 ( s) =

G ( s ) = G3 ( s ) =

1
s + 1

s 2 + 1
s ( 1 + 2 ) + 1

R1

Vin

Vout
R2

H out 2 ( s ) =

K PD KVCO /
s + s / + K PD KVCO / N
2

2n s + n2
H out 3 ( s ) = 2
s + 2n s + n2

K PD KVCO
N

1
N
2 K PD KVCO

n =

K PD K VCO
N ( 1 + 2 )

1
2

K PD K VCO
N
+ 2 +
N ( 1 + 2 )
K PD K VCO

1=R1C1
2=R2C1

C1

Type I PLL
Magnitude (dB)

10
0

|Hout3(s)|

-10

|Hout1(s)|

-20

|Hout2(s)|

-30
-40
-2
10

10

-1

0
10

Phase (Degree)

0
Hout3(s)

-50
-100

Hout1(s)

-150

Hout2(s)

-200
-2
10

-1
10
Frequency [Hz]

A drawback of type-I phaselocked loops is that it is not

possible to set
independently the loop
bandwidth n, the damping
factor and the loop gain
KPDKVCO

0
10

Comparison of the closed loop transfer function of

the PLL for the three previous loop filters

10

Charge Pump PLL (Type-II)

A type-II PLL is the most commonly used
for frequency synthesizer applications, it is
also known as charge-pump PLL
VDD

Loop Filter

UP

fin
PFD

Iin

Vvco

DWN

fout
VCO

R1

fdiv

Advantages:
Increased locking range
Speed up in capture process
Phase Frequency Detector (PFD)
Charge Pump (CP) combination
creates extra pole at zero
frequency
This pole provides infinite gain at
DC, which results in zero phase
error in ideal locked state

C2
C1
Charge Pump

1
N

Note: This PLL is also known as Digital PLL since the phase comparison and
frequency division are performed digitally

Disadvantages:
Sampled operation introduces
spurious tones at the VCO output
Loop bandwidth limited by stability
considerations
11

Phase-Frequency Detector
VDD

"1"
D
In

UP
CLR

Out
DWN

CLR

Div
"1" D

Conceptual PFD-CP
fREF

UP

Compares edges of reference

and divided clocks.
If reference clock leads the
divided clock, the UP signal is
asserted.
If the divided clock leads the
reference clock , the DWN
signal is asserted.
In an ideal PFD no pulses are
present at the output in the
locked state.
Duty cycle of inputs is not
relevant to the circuit
operation.
The width of the UP/DWN
pulses is proportional to the
phase difference between the
clock inputs.

DWN

fDIV

Typical PFD implementation

12

 In practical PFD the delay of the gates creates non-idealities in the

phase input/output characteristic.
The PFD can no longer resolve very small phase errors, and a
dead zone is created.
To solve this problem, extra delay is introduced in the feedback
path of reset signal.

Average Charge Pump Current (A)

up=0
dn=0
ref

ref
div

up=0
dn=1

div

up=1
dn=0

ref

div

-1
-0.1

State machine of PFD

-0.05

0
Phase error (2rad)

0.05

0.1

Phase response of PFD with dead zone

13

 In locked state, narrow pulses are generated in

both UP/DWN outputs.
The width of these pulses determines the amount of
noise introduced to the VCO output by the chargepump.
Timing mismatch between the UP/DWN pulses is a
source of spurious tones.

UP

DWN

ton
tref

Output of PFD for locked state

14

Charge Pump

VDD

"1" D
In

The Charge-Pump converts

the phase error information
provided by the PFD into a
voltage that controls the
VCO frequency.

Icp

Q
UP

S1

CLR

DWN

CLR

S2
C1

Div
"1" D

Vout

Icp

If the UP input is asserted,

S1 is closed and charge is
injected into capacitor C1,
increasing voltage Vout

UP

DWN

Icp
Total
CP
current

Vout
t

If the DWN input is asserted,

S2 is closed and charge is
extracted from capacitor
C1,decreasing voltage Vout
15

Charge Pump
Calculating the Detector Gain:
The time the UP/DWN signals are
asserted is:
t up =

T
2

Where T is the reference period and

is the phase difference
measured by the PFD.

Capacitor C1 is the main

integrating capacitor; it generates
the pole at zero frequency.
Resistor R1 introduces a stabilizing
zero. Capacitor C2 is added to the
loop filter to reduce the glitches on
the VCO control voltage

The average current provided by the

charge pump for a given is:
t up I cp
=

I pd = I cp
2
T
Which gives an overall phase
detector gain Kpd of:
I cp
K pd =
2

16

Non-ideal effects of charge pumps

Current mismatch
Mismatch between source and sink
currents in the charge pump introduces
a finite phase error.

Current leakage
When the source/sink currents are off,
leakage currents can flow and modify
the VCO control voltage of the VCO by
charging/discharging the loop filter.
Spurs are introduced.

Charge sharing
Parasitic capacitances from the switches
share charge with the loop filter when
the nodes they are connected to have a
large change in their voltage.

icp
ileak

ton

Charge injection
Occurs when switches are turned off
and the charge in their channels is
injected/extracted to the loop filter.
Spurs are introduced

17

Loop Filter Characteristics

The PFD-CP and C1 combination introduces a pole at

zero frequency.

This pole, along with the zero generated by the VCO

generates -40dB/decade loop gain at low frequency.

V
in

R1

C2

If the loop gain crosses 0dB with a slope of

-40dB, then the circuit is unstable.

In order to stabilize the circuit, resistor R1 is introduced in

series with C1 to create a zero.

The zero at z reduces the slope of the loop gain to

-20dB/decade and stabilizes the circuit.

Capacitor C2 is added to reduce ripples in the VCO control

voltage. Adds a second pole p2 to the loop filter.

C1

z =

p2 =

An extra (third) pole can be added to further eliminate

VCO ripple, at the expense of phase margin degradation
(stability)

vco

R1

1
R1C1

1
C1 C 2

1
R1C 2

C1 + C 2
18

Loop Filter
140

The transimpedance of loop filter is:

130

And the open loop transfer function of the

PLL

120

|Z(s)| [dBohm]

V
1 + sR1C1
Z ( s) = VCO = R1
I in
s[R1C1 R1C2 s + R1 (C1 + C2 )]

110
100
90
80
70

K K Z ( s)
H ol ( s) = div = PD VCO
in
N
=

KVCO I cp
2N

R1

60
50
2
10

1 + sR1C1
s[R1C1 R1C2 s + R1 (C1 + C2 )]

The crossover frequency (0dB gain in the Hol(s))

c = z p 2 = z

C1
+1
C2

3
10

4
5
10
10
Frequency [Hz]

7
10

6
10

Transimpedance of loop filter

The phase margin

c
1 c
m = tan tan

z
p2
1

19

The phase margin, zero and pole frequency

can be written as a function of the capacitor
ratio C1/C2

With these values, the crossover frequency

as a function of PLL parameters can be
obtained.

p2
1
m = tan
z

This form of the equation assumes the

crossover frequency is aligned with the
maximum of the phase margin

tan 1 z
p2

C1

1
1
m = tan
+ 1 tan 1

C
C
2
1

+
1
C

z =

1+

C1
C2

p 2 = c 1 +

C1
C2

c =

I cp K vco
N

I cp K vco R1
C1

R1
C1 + C2
N

This equation shows that the loop bandwidth

is not a function of C1, but a function of R1,
Kvco, Icp and N.
In general, the crossover frequency Wc is
equal to the loop bandwidth of the PLL.

20

PLL Open Loop Response

100

Magnitude
[dB]

50

The ratios between c/z and

margin and damping factor of the

z
p2

-50

10

10

10

10

10

-100

PLL.

PM

-120
Phase Degree

of the loop are set by them.

-100
2
10

p2/c determine the phase

Thus, the transient characteristics

-140
-160
-180
2
10

10

10

f
(Hz)

10

10

10

Plotting the open loop response of the PLL

helps to determine graphically the crossover
frequency and phase margin
21

Performance Metrics
The design of frequency synthesizers for RF
systems involves complying to a large set of
specifications, such as:

Tuning Range and Frequency Resolution

Phase Noise
Spurious Signals
Settling Time
Communication standards usually do not include particular block
specifications. It is up to the system/circuit designer to obtain the
proper circuit specifications for each building block

22

Frequency Resolution and

Accuracy
The frequency accuracy is related with
the maximum offset that the synthesized
frequency can have, with respect to the
desired center frequency

The frequency resolution of the

synthesizer is set by the required
channel spacing of the intended
application
Standard

Tuning range
(GHz)

Frequency Resolution

Frequency Accuracy

Bluetooth

2.400 2.479

1 MHz

75 kHz

IEEE 802.11a

5.150 5.350
5.750 5.850

20 MHz

60 kHz

IEEE 802.11b

2.400 2.479

5 MHz

60 kHz

IEEE 802.11g

2.400 2.479

20 MHz

60 kHz

DCS1800

1.710 1.785
1.805 1.880

200 kHz

5 kHz

The frequency resolution affects

the selection of synthesizer
architecture (Integer / Fractional)

The frequency accuracy defines a

boundary for settling time calculation
23

Phase Noise
Phase noise is a measure of the spectral purity of a signal and is one of the
most important parameters for characterization of the synthesizer
Phase noise degrades the quality of the data in a communication system
Assume the PLL output is a sinusoidal tone at

Power

v(t ) = (1 + a (t ) ) sin (0t + (t ) )

0
carrier

dBc/Hz

with amplitude and phase variation a(t) and (t)

respectively

(t) has a random part and a deterministic part

spur
[dBc]

0m

(t)= r(t)+ dsin(dt)

()

0+m

The random part, r(t), accounts for phase

noise and the deterministic part, dsin(dt),
for spurious tones
24

Phase Noise (continued..)

Assuming the phase variations are a single tone in the phase, (t)=
msin(mt), and the root mean square (rms) value of (t) is much smaller than
1 radian, the output of the oscillator becomes:

[sin ((0 + m )t ) + sin ((0 m )t )]

2
the output spectrum of the oscillator contains a narrowband FM signal
with a modulation index m and a strong component at the
fundamental frequency 0
vosc (t ) A sin(0t ) + A

The oscillator output voltage power spectral density (PSD) is related to the
phase noise PSD

A2
SV ( ) =
2

1
1

)
+
(

)
+
(

)
0

2
2

S ( ) =

m2
2

( m )

The phase noise skirt is directly

translated to noise side lobes
at both sides of the carrier
frequency
25

Phase Noise (continued..)

Phase noise {} is defined as the ratio of the noise power, in a
bandwidth of 1 Hz at a certain offset frequency from 0, to the
carrier power Pcarrier
{} = 10 log

Pnoise (1Hz band at )

Pcarrier

The actual phase noise at an offset m is:

S (m )
SV (0 + m )
{} = 10 log
10
log
=

[dBc]
2

2
2

The units dBc/Hz refer to the ratio between the noise and the carrier
in dB in a bandwidth of 1 Hz.
26

Phase Noise (continued..)

The phase noise at the output of the VCO comes from
Reference clock
Phase-Frequency Detector
Charge Pump
Loop Filter
Frequency Divider
VCO Active Devices Noise
Due to this noise, the output of the VCO is no longer a
single frequency tone, but a smeared version
Sometimes the energy is concentrated at frequencies other than
the desired frequency, appearing as a spike above the skirt.
This energy is due to a spurious tone.

27

Syn. Output

The unwanted channels may be

much larger than the desired
channel (as much as 40dB for
Bluetooth), setting stringent
requirements for phase noise and
spurious signals.

Desired
Channel

Unwanted Channels

fRF

Desired Tone
Spurious tone
Phase Noise
fLO

Receiver Output

Phase Noise and Spurious Tones

are mixed with adjacent channels
and degrade the desired
downconverted signal.

Received Signal

Effect of Phase Noise in Received

Signal

Noise
Desired signal
fIF = fRF - fLO

28

Phase Noise Specification

The total noise, Pnoise, in a channel with
bandwidth fBW, blocker power Pblk at an
offset frequency from the desired
channel and a phase noise {} is

The equation assumes that the phase

noise is constant (white) in the
channel bandwidth

Pnoise (dBm) = Pblk (dBm) + f BW (dBHz) + {}(dBc/Hz)

The signal-to-noise ratio (SNR) of the downconverted signal is:

SNR(dB) = PIF (dBm) Pnoise (dBm)

SNR(dB) = Psig (dBm) [Pblk (dBm) + {}(dBc/Hz) + f BW (dBHz)]
For a minimum received signal Psig_min, maximum blocker signal Pblk_max and
minimum required SNR, the phase noise specification can be determined as:

{}(dBc/Hz) < Psig _ min (dBm) Pblk _ max (dBm) f BW (dBHz) SNR (dB)

29

Phase Noise Numerical Example

For Bluetooth the carrier-to-interferer ratio at a 3MHz offset
is 40dB, the SNR is 16dB, the channel bandwidth is 1MHz.
With these values the phase noise can be calculated

{3MHz}(dBc/Hz ) < 40dB 10 log(1e6 Hz ) 16dB

{3MHz} < 116dBc / Hz

A margin has to be added to the obtained value since there are more
contributions to the degradation of the signal to noise ratio (SNR), generally
this margin is related to the overall noise figure of the system and can be as
large as 4dB

30

Close-in Phase Noise

The close-in phase noise is the portion
of the phase noise located very close to
the oscillator center frequency

It is usually dominated by the noise of

the reference signal and is typically
constant over the loop bandwidth (n)

-n

i (dBc/Hz) < 10 log(4 n )(dBHz) SNR (dB)

The term 4n accounts for the double sided noise around the
fundamental tone of the oscillator and the contribution to the phase
noise of the reference at frequencies higher than the loop bandwidth
31

Spurious Signals
The periodic phase variation at the output of the oscillator
generates spurious tones (also named spurs)
Spurs are generated due to the sampled nature of the
charge-pump PLL.
The spur specification is calculated in a similar fashion as the phase noise,
but now the noise is concentrated in a single frequency, instead of being
smeared in the channel bandwidth.

spur ( )(dBc) < Psig _ min (dBm ) Pblk _ max (dBm ) SNR (dB)
For Bluetooth the carrier-to-interferer ratio at a 2MHz offset
is 30dB, the SNR is 16dB and the spur results in:

spur (2 MHz )(dBc) < 30(dBm ) 16(dB)

spur (2 MHz ) < 46 dBc
32

Effect of non-idealities on spurious

signals
Recall that the oscillator output modulated by a sinewave of baseband
frequency fm generates a pair of frequency components the spurious
signals, at a distance fm from the carrier frequency f0

vosc (t ) A sin(0t ) + Asp

m
2

[sin ((0 + m )t ) + sin ((0 m )t )]

The previous equation also shows that the amplitude of the spurious signals
Asp is related to the amplitude of the carrier signal A and to the peak phase
deviation m by

Asp = A

m
2

To calculate the magnitude of the spurious tones we need to determine

the maximum phase variation as a function of the amplitude at the
tuning line of the VCO, Am
33

spurious signals continued . .

m = K vco Am cos(ref )d
0

=
max

K vco Am

ref

The amplitude of the undesired spurious tone in decibel with respect

to the magnitude of the carrier can be obtained

Asp
m
20
log
=

A
2
dBc
K A
= 20 log vco m
2
ref

The maximum tuning line ripple Am for a given spurious

specification [Asp/A] dBc is:

Am =

2 ref
K vco

10

Asp

A dBc
20

34

There are two main effects which can generate reference spurious:
1. Leakage current in loop filter and charge-pump
If the charge-pump current Iout is considered as a periodic pulse train, the Fourier
series representation is

The amplitude of the ripple signal

I out (t ) = I leak + 2 I leak cos( 2nf ref t )
generated by the leakage current at the
n =1
reference frequency Am is

Am = 2 I leak Z ( jref )

I leak Z ( j 2f ref ) K vco

Asp

A = 20 log

2f ref
dBc

The relative amplitude of the spurious

signals does not depend on the absolute
bandwidth of the loop filter or on the chargepump current Icp.

It is only a function of the

transimpedance of the loop filter Z(s),
the VCO gain Kvco and the absolute
magnitude of the leakage current Ileak.
35

2. Mismatch in the charge-pump Up and Down current sources

Similar calculations can be performed to obtain the magnitude of the
spurious tone as a function of the mismatch of charge-pump currents
The Fourier series of the current waveform must be obtained and the
fundamental tone of Iout obtained.

I out Z ( j 2f ref ) K vco

Asp

A = 20 log

4f ref
dBc

The previous results are very important, since they allow the designer
to estimate the spurious tone magnitude during the initial design of
the charge-pump and without the need of close loop simulations
36

Phase Noise in a PLL

IPD(s)

VCO(s)

VLF(s)

IN(s)

OUT(s)
Kpd

Z(s)

Kvco/s

1/N
DIV(s)

N K pd K vco Z (s )
( s)
H LP ( s ) = OUT
=
IN ( s) N s + K pd K vco Z (s )
H VCO ( s ) =

H LF ( s ) =

OUT ( s)
N s
=
VCO ( s) N s + K pd K vco Z (s )
OUT ( s)
VLF ( s )

N K vco
N s + K pd K vco Z (s )

At very low frequencies Ns << KpdKvcoZ(s)

and HLP(s) N
For frequencies above the loop
bandwidth, Ns << KpdKvcoZ(s) and lim
s HVCO(s) = N
bandpass characteristic and presents
peaking at frequencies around the loop
bandwidth

37

 VCO highpass
REF lowpass

38

Settling time
DEFINITION: The time required for the
PLL to change its output frequency from
fout(0) to fout() within a frequency error
smaller or equal to

Applying a change in the reference

frequency from fref to and leaving
the divider ratio N unchanged also
provides the same VCO output
frequency (N+N)fref

f out (t ) f out ()
The closed loop transfer
function is:

The output frequency of the VCO

N
f out = ( N + N ) f ref = N 1 +
f ref
N

The filter used for

the analysis
contains one pole at
the origin and one
zero that stabilizes
the loop

Iin
R1

G ( s) = K f

1 + s
s

Vout

N (2 n s + n2 )
H (s) = 2
s + 2 n s + n2

C1

39

Settling time (continued . . . )

where

K pd K f K vco

n =

K pd K f K vco
N

sin (m )
=
2 cos(m )
= c cos(m )

The PLL responds to the input

frequency step as

f out ( s ) = f out ( s) f ref =

f out ( s ) = Nf ref

Nf ref
N s

H ( s)

(2 s + )
n

2
n

The steady state frequency can be found

using the final value theorem

f out () = f out () f ref

Nf ref

= lim s0 s
H ( s ) = Nf ref

N
s

and the lock time can be calculated as:

tlock = L1 {f out ( s )} f out () <

Nf ref

tlock = L1
H ( s ) f out () <
N s

s ( s 2 + 2 n s + n2 )
40

Settling time (continued . . . )

Depending on the value of the
damping factor , there are
three different cases

0 < <1
=1
>1

Underdamped
Critically Damped
Overdamped

Decomposing the
transfer function of
fout(s) in partial
fractions we obtain
the general form

The poles of the transfer function for

each case are

n j 1 2

= n

n j n 2 1

1, 2

Nf ref 1
Nf ref 2

2
j2 1 2 n
Nf ref + j 2 1 n
+
s
s 1
s 2

Nf ref Nf ref Nf ref n

f out ( s ) =
+
+
2
+
s
s

(
)

n
n

Nf ref 1
Nf ref 2

2
Nf ref
j 2 1 n
j 2 2 1 n
+
+

s 1
s 2
s

<1
=1
>1

<1

=0

>1
41

Settling time (continued . . . )

Applying the inverse Laplace transformation

e 1t e 2t
2

Nf ref 1 + 1

j 2 1 2 n

f out (t ) = Nf ref 1 - e nt (1 n t )

e 1t + e 2t

1
2

Nf ref 1 +
2 2 1 n

<1

=0

>1

Substituting in the equation for tlock (page40), the frequency error becomes:
2

1
e nt

2
1

Nf ref
sin n 1 t tan
2

= Nf ref e nt (1 n t )

-
nt
2
2
cosh( n 1t ) +
sinh ( n 1t )
Nf ref e

2 1

<1

=0
>1
42

Settling time (concluded . . . )

Solving for tlock we obtain expresions for the settling
time for a given frequency step and error

tlock

Nf

ref

ln
2
1

= Solved numerically

Nf ref 2 1 +
1

ln

2
2

1
2
1

<1

=0
>1

43

Plot of the normalized lock-time n as a function of

Nf r

the damping factor for several values of

45

Normalized lock-time n

40
35

E=

Nfr

E=105

30
E=104

25
20

E=103

15
E=102
10
5
0.4

0.6

0.8

1
1.2
1.4
Damping Factor

1.6

1.8

44

Design Procedure

Choose a phase margin

Calculate the damping factor required to obtain the desired phase margin (Fig. 2.19a)
Based on the damping factor, settling time and settling accuracy determine the minimum loop bandwidth c,min
Determine C1/C2 ratio based on the phase margin
Calculate C2,min based on leakage current Ileak (1nA), charge pump mismatch Iout (2nA) and spurious
suppression
Calculate C1,min
Compute the position of the zero z
Calculate the value of resistor R1
Determine the charge pump current

45

Examples of circuit implementations

Cascode current mirrors
minimize the current mismatch.

Charge Pump
Vdd
UP

But reduce linear range of

output voltage.
Design Considerations:

35 A
VbiasP
Iout

VbiasN

Vdd

DWN

Source and sink current

matching.
Source and sink speed
matching.
Leakage current minimization.
Reference Spurs.
Compliance voltage.
46

Loop Filter

Icp

+
R1
Vo
C2
C1

Trade offs

Settling Time
Close-in Phase Noise
Total Capacitance (area)
Charge Pump Current
Phase Noise Contribution of
R1
47

Voltage Controlled Oscillator

Vc

Trade offs

Ib
Vb

Phase Noise
Tuning Range
Power Consumption

48

Programmable Divider

Program
Counter

Prescaler
fIN

fOUT
%(N+1)/N

%P

%S

Reset
Swallow
Counter

Channel
Selection

Popular scheme for integer-N FS

Program Counter can be also
programmed
Fast response of Swallow
Counter

( N + 1) S + ( P S ) N
f out = ( NP + S ) f in
P>S
49

Prescaler

Critical block in design of FS along with VCO (High frequency of

operation)
Usually consumes a lot of power
Two main architectures
Synchronous
Asynchronous
Frequency dividers
Digital
Pure digital (TSPC logic)
Quasi digital (Current Mode Flip - Flops)
Analog
Injection locked frequency dividers

50

Synchronous Prescaler
fin

3/4

Input Flip Flops run

at maximum speed

MCi

Feedback gates need

minimum delay
Feedback reduces
speed by aprox. 30%

fout

MC

MCi

SET

CLR

Q
Q

SET

Vout
CLR

Q
Q

CLK

51

CMOS Flip - Flop

Vdd

Q
Q
A

CLK

Vb

CLK

CLK

CLK

Vbias

Current Mode Logic (CML). Low voltage swing

Input differential pair followed by latch
Speed limited by RC product of output nodes 52

Phase Switching Prescaler

To Mixers
Architecture

Mux

LO Port
f in /2

fin
/

2
5
GHz

I
Q
I
Q

2
/

2
2.5
GHz

Modulus
Control

Phase
Selection

fin /4
I /
I 2
Q
Q /
2

1.25
GHz

I
Q
I
Q

p0
p2
p4
p6

I
Q
I
Q

p1
p3
p5
p7

f in /8

625
MHz

Phase
Selection

Phase switching prescaler for

reduced power consumption
compared with traditional
architectures.

fout

Modulus
Control

15/16 Dual Modulus

53

Phase Switching Prescaler

Modulus
Control

Phase
Selection
Mux

Phase switching principle

Every rising edge of fout the multiplexer
selects a phase that lags 45 the current
phase, effectively swallowing an input pulse
(dividing by N+1)

fin /4

I
Q
I
Q

p0
p2
p4
p6

I
Q
I
Q

p1
p3
p5
p7

2
/

2
1.25
GHz

f in /8

625
MHz

Phase
Selection

Modulus
Control

p5
p6
p7

1 2 3 4 1 2 3 4

Mux
1 2 3

fout

1 2 3 4 5 6 7 1 2 3 4 5 6 7 8

fout

54

Implementation: High
Frequency
D Flip-flop in bipolar
technology

I
Q
I
Q

CLK
Q

Vdd

R
Q
Q

CLK

CLK

Vbias

Ibias

55

Recent Advances in Frequency

Synthesizers Design
The research focuses in:

a)

New Architectures
Linearization techniques (spur reduction)
Digital PLL
Fast Settling
New and improved VCO
Reduced power frequency dividers
Low voltage low power PLLs
56

Dual Loop Architectures

VDD

VDD

Loop Filter
BW2

Loop Filter
BW1
UP

fref1
100MHz

PFD

LPF

DWN

UP

fout

LPF

VCO1

DWN

fref2
PFD
800kHz

VCO2

Charge Pump

Charge Pump

1
X

1
N
SSB
Mixer

N=16

1
N

X=4
Channel
Selection

T. Kan and H. C. Luong, A 2-V 1.8-GHz Fully Integrated CMOS Frequency Synthesizer for DCS-1800 Wireless Systems, VLSI Circuits, pp: 234 - 237, 2000.
VDD

VDD

Loop Filter
BW1
UP

fref1
1.6MHz

PFD

LPF

DWN

VCO1

Charge Pump

11.3 - 17.45 MHz

fref2
1
PFD
X
X=32

Loop Filter
BW2

865.2 - 889.9 MHz

UP
DWN

fout
LPF
VCO2

Charge Pump

1
N
Channel
Selection

1
N
fref2 = 205MHz

57

W. Yan and H. C. Luong, A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM wireless receivers, IEEE JSSC, vol. 36, pp: 204-216, February 2001.

Nested Loop PLL and Stabilization

Technique
VDD

VDD

Loop Filter
BW1

Loop Filter
BW2

UP

fref1
PFD

DWN

UP

LPF

PFD

fout
LPF

DWN

IF
VCO

RF
VCO

Charge Pump

A.N. Hafez and M.I. Elmasry, A FullyIntegrated Low Phase-Noise NestedLoop PLL for Frequency Synthesis,
CICC, pp: 589 592, 2000.

Charge Pump

1
N1
1
N2
Channel
Selection
fref

Ip1

Vcont

UP

PFD

DWN

Ip2
T. C. Lee and B. Razavi, A Stabilization Technique
for Phase-Locked Frequency Synthesizers, VLSI
Symposium, pp: 39 - 42, 2001

fout

CP1

C1

VCO

CP1

1
N

58