HCF4510B

PRESETTABLE BCD UP/DOWN COUNTER

MEDIUM SPEED OPERATION :

8 MHz (Typ.) at 10V
SYNCHRONOUS INTERNAL CARRY
PROPAGATION
RESET AND PRESET CAPABILITY
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIF. UP TO 20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"

DESCRIPTION
HCF4510B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP package.
It is a PRESETTABLE BCD UP/DOWN
COUNTER consists of four synchronously
clocked D-type flip-flops (with a gating structure to
provide T-type flip-flop capability) connected as a
counter. This counter can be cleared by a high
level on the RESET line, and can be preset to any
binary number present on the jam inputs by a high
level on the PRESET ENABLE line. This device
will count out of non-BCD counter states in a
maximum of two clock pulses in the up mode and

DIP

ORDER CODES
PACKAGE

TUBE

DIP

HCF4510BEY

T&R

a maximum of four clock pulses in the down mode.

If the CARRY IN input is held low, the counter
advances up or down on each positive going clock
transition.
Synchronous
cascading
is
accomplished by connecting all clock inputs in
parallel and connecting the CARRY OUT of a less
significant stage to the CARRY IN of a more
significant stage. HCF4510B can be cascaded in
the ripple mode by connecting all clock inputs in
parallel and connecting the CARRY OUT to the
clock of the next stage. If the UP/DOWN input
changes during a terminal count, the CARRY OUT
must be gated with the clock, and the UP/DOWN
input must change while the clock is high. This
method provides a clean clock signal to the
subsequent counting stage.

PIN CONNECTION

September 2002

1/11

HCF4510B
IINPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION
PIN No

SYMBOL

NAME AND FUNCTION

Inputs
Outputs
Clock Input
Up/Down Control Input
Carry Input
Carry Output
Reset Input

PRESET
ENABLE
P1 to P4
Q1 to Q4
CLOCK
UP/DOWN
CARRY-IN
CARRY-OUT
RESET
VSS

16

VDD

Positive Supply Voltage

1
4, 12, 13, 3
6, 11, 14, 2
15
10
5
7
9

Preset Enable Input

Negative Supply Voltage

FUNCTIONAL DIAGRAM

TRUTH TABLE
CL
X

X
X
X : Dont Care

2/11

CARRY-IN

UP/DOWN

PRESET
ENABLE

RESET

ACTION

NO COUNT

COUNT UP

COUNT DOWN

X
X

X
X

H
X

L
H

PRESET
RESET

(Cl)

HCF4510B
LOGIC DIAGRAM

TIMING CHART

3/11

HCF4510B
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD

Parameter
Supply Voltage

VI

DC Input Voltage

II

DC Input Current

PD

Value

Unit

-0.5 to +22

-0.5 to VDD + 0.5

10

V
mA

200
100

mW
mW

Top

Power Dissipation per Package

Power Dissipation per Output Transistor
Operating Temperature

-55 to +125

Tstg

Storage Temperature

-65 to +150

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.

RECOMMENDED OPERATING CONDITIONS

Symbol
VDD

4/11

Parameter
Supply Voltage

VI

Input Voltage

Top

Operating Temperature

Value

Unit

3 to 20

0 to VDD

-55 to 125

HCF4510B
DC SPECIFICATIONS
Test Condition
Symbol

IL

VOH

VOL

VIH

VIL

IOH

IOL

II

CI

Parameter

Quiescent Current

High Level Output

Voltage
Low Level Output
Voltage

VI
(V)
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0

High Level Input

Voltage
Low Level Input
Voltage
Output Drive
Current

Output Sink
Current
Input Leakage
Current
Input Capacitance

VO
(V)

0/5
0/5
0/10
0/15
0/5
0/10
0/15
0/18

0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5

Value

|IO| VDD
(A) (V)

<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1

Any Input
Any Input

5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
18

TA = 25C
Min.

Typ.

Max.

0.04
0.04
0.04
0.08

5
10
20
100

4.95
9.95
14.95

-40 to 85C

-55 to 125C

Min.

Min.

150
300
600
3000
4.95
9.95
14.95

0.05
0.05
0.05

4.95
9.95
14.95

3.5
7
11
1.5
3
4
-3.2
-1
-2.6
-6.8
1
2.6
6.8

0.1

7.5

0.05
0.05
0.05

1.5
3
4

V
1.5
3
4

-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4

3.5
7
11

-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4

10-5

Max.
150
300
600
3000

0.05
0.05
0.05

3.5
7
11

-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0

Max.

Unit

mA

mA

A
pF

The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V

5/11

HCF4510B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition
Symbol

Parameter

tPHL tPLH Propagation Delay Time

Clock to Q Output
tPHL tPLH Propagation Delay Time
Preset or Reset to Q
Output
tPHL tPLH Propagation Delay Time
Clock to Carry Out
tPHL tPLH Propagation Delay Time
Carry in to Carry Out
tPHL tPLH Propagation Delay Time
Preset or Reset to Carry
Out
tTHL tTLH Transition Time

fMAX

tW

tREM (1)

tr , tf (2)

tsetup

tsetup

tW

Maximum Clock
Frequency
Clock Pulse Width

Preset Enable or Reset

Removal Time
Clock Rise or Fall Time

Carry in Setup Time

Up/Down Setup Time

Preset Enable or Reset

Pulse Width

VDD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15

Value (*)
Min.

2
4
5.5
150
75
60
150
80
60

Unit

Typ.

Max.

200
100
75
210
105
80
240
120
90
125
60
50
320
160
125
100
50
40
4
8
11

400
200
150
420
210
160
480
240
180
250
120
100
640
320
250
200
100
80

ns

ns

ns

ns

ns

MHz

ns

ns
15
5
5

130
60
45
360
160
110
220
100
75

ns

ns

ns

ns

(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
(1) Time required after the falling edge of the reset or preset enable inputs before the rising edge of the clock will trigger the counter (similar
to setup time)
(2) If more than unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of the fixed propagation
delay at 15pF and the transition time of the carry output driving stage for the estimated capacitive load.

6/11

HCF4510B
TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)

RL = 200K
RT = ZOUT of pulse generator (typically 50)

WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)

7/11

HCF4510B
WAVEFORM 2 : MINIMUM SETUP TIME (CI TO CLOCK) (f=1MHz; 50% duty cycle)

WAVEFORM 3 : PROPAGATION DELAY TIMES, MINIMUM RESET PULSE WIDTH (f=1MHz; 50%
duty cycle)

8/11

HCF4510B
TIPICAL APPLICATIONS TYPICAL 16-CHANNEL, 10 BIT DATA ACQUISITION SYSTEM

TIPICAL APPLICATIONS CASCADING COUNTER PACKAGES

9/11

HCF4510B

Plastic DIP-16 (0.25) MECHANICAL DATA

mm.

inch

DIM.
MIN.
a1

0.51

0.77

TYP

MAX.

MIN.

TYP.

MAX.

0.020
1.65

0.030

0.065

0.5

0.020

b1

0.25

0.010

20

0.787

8.5

0.335

2.54

0.100

e3

17.78

0.700

7.1

0.280

5.1

0.201

L
Z

3.3

0.130
1.27

0.050

P001C
10/11

HCF4510B

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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
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11/11