Sheet 6

Problem 1:

Problem 2:

Problem 3: Given the following logic expression, answer the following questions:

= (A.B) + (A.C.E)

I.

Implement the above logic expression using static CMOS logic. You
should use the minimum number of transistors. What is the number of
transistors you have used in your design?

II.

Size the NMOS and PMOS devices such that the output resistance is the
same as that of an inverter with an NMOS W/L = 2 and PMOS W/L =3 .

III.

What are the input patterns that results in the worst case LOW-to-HIGH
and HIGH-to-LOW propagation delay times?

IV.

Calculate the worst case LOW-to-HIGH and HIGH-to-LOW propagation

delay times.

V.

What are the input patterns that results in the best case LOW-to-HIGH
and HIGH-to-LOW propagation delay times?

VI.

Calculate the best case LOW-to-HIGH and HIGH-to-LOW propagation

delay times.

VII.

Draw a stick diagram for the above CMOS transistor network and
estimate the layout area.

Hint: Calculate the delays in terms of the output capacitance CL, and the equivalent inverter
resistances RN and RP.

Problem 4: Consider the following circuit driving a capacitive load of 1pF. Given that Vtn = |Vtp| = 0.6V,
kn' = 3kp' = 115A/V2.

I.

Assume that the input In swings from rail to rail (i.e., 0 to 2.5V), what is
the swing on the output node out?

II.

At the switching threshold VM = 1.75V, what is the mode of operation of

M1 and M2? Justify your answer.

III.

Assuming (W/L)M1 = 4, find (W/L)M2 such that VM = 1.75V.

IV.

Using the sizing in part III. above, find the LOW-to-HIGH and the
HIGH-to-LOW propagation delays.

V.

Assume that the input switches at a clock frequency of 10MHz with a

swing from 0 to VDD and zero rise/fall times, Calculate the average static
and dynamic power dissipation.

VI.

What is the maximum switching frequency allowed for the input signal?

VII.

Calculate the static and dynamic power dissipation at this maximum

frequency.

VIII. What are the advantages/disadvantages of adding the Vlow = 1V between

the source of the NMOS transistor and the ground? Justify your answers.

Problem 5:
The inputs to a Domino Logic gate are always LOW during the precharge phase (CLK = LOW) and many
undergo a LOW-to-HIGH transition during the evaluation phase (CLK = HIGH). Consider the Domino 3input AND gate shown, if during the evaluation phase A=HIGH, B=C=LOW, charge sharing will cause the
voltage at the inverter input to drop. The supply voltage is given as VDD = 2.5V.

I.
II.
III.
IV.

Given that the switching threshold of the inverter is 1.25V, Calculate the
maximum ratio CP/CL necessary to ensure that charge sharing does not corrupt
the value of F for the given case.
What is the inputs pattern that results in the worst case charge sharing?
With the aid of drawing, explain TWO circuit techniques used in Domino
CMOS circuits for solving the charge sharing problem. What drawbacks might be
associated with those two circuit techniques?
Draw a stick diagram for the above circuit and estimate the layout area.

Problem 6:
Consider the following cross-coupled complementary pass-gate logic,

I.

What is the logic function Y implemented by the above gate?

II.

?
What is the voltage swing on nodes Y and Y

III.

, B, B
are from ideal voltage sources and have a rail-to-rail
Assume that A, A
swing (0 to VDD). Also assume that there is no body effect ( = 0). Is this a
ratioed circuit? Explain.
Draw a stick diagram for the above circuit and estimate the layout area.

V.