15ELEC17H

VLSI Technology
Fall 2015
Lecture 09-10: Semiconductor Memories
&
ASIC/FPGA Flow
Dr. Hassan Mostafa
.
Hassan.mostafa@bue.edu.eg
[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

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Semiconductor Memory Classification

Read-Write Memory

Random
Access

Non-Random
Access

SRAM

FIFO

DRAM

LIFO

Non-Volatile
Read-Write
Memory

Read-Only Memory

EPROM

Mask-Programmed

E2PROM

Programmable (PROM)

FLASH

Shift Register
CAM

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Memory Architecture: Decoders

m bits

m bits

S0

Word 0

S0

Word 0

S1

Word 1

S1

Word 1

S2

Word 2

A0

S2

Word 2

A1

S3

S3

Storage
Cell

Storage
Cell

Ak-1
Sn-2

Word n-2

Sn-2

Word n-2

Sn-1

Word n-1

Sn-1

Word n-1

Input/Output

Input/Output

n words n select signals

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Decoder reduces # of inputs

k = log2 n
3

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Array-Structured Memory Architecture

bit line

2k-j

word line

Aj
Aj+1

storage
(RAM) cell

Ak-1

m2j
A0
A1
Aj-1

Column Decoder
Sense Amplifiers

selects appropriate
word from memory row
amplifies bit line swing

Read/Write Circuits

Input/Output (m bits)
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Hierarchical Memory Architecture

Input/Output (m bits)

Advantages:
1. Shorter word and/or bit lines
2. Block addr activates only 1 block saving power
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MOS NOR ROM

All word lines LOW by default with exception of selected row
V DD
Pull-up devices

WL [0]
GND
WL [1]

WL [2]
GND
WL [3]

BL [0]

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BL [1]

BL [2]

BL [3]

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MOS NAND ROM

V DD
Pull-up devices
BL [0]

BL [1]

BL [2]

BL [3]

WL [0]

WL [1]

WL [2]

WL [3]

All word lines high by default with exception of selected row

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Precharged MOS NOR ROM

f

V DD

pre

Precharge devices
WL [0]

GND
WL [1]

WL [2]
GND
WL [3]

BL [0]

BL [1]

BL [2]

BL [3]

PMOS precharge device can be made as large as necessary,

but clock driver becomes harder to design.
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Read-Write Memories (RAM)

STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential

DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
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6-transistor CMOS SRAM Cell

WL

V DD
M2
M5

M4
Q

Q
M1

M3

BL

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M6

BL

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CMOS SRAM Analysis (Read)

WL

V DD
M4

BL
Q= 0

M5
V DD

M1

Q= 1

V DD

M6
V DD

Cbit

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BL

Cbit

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CMOS SRAM Analysis (Read)

1.2

Voltage Rise (V)

1
0.8
0.6
0.4
0.2 rise [V]
Voltage

0
0

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0.5

1 1.2 1.5 2
Cell Ratio (CR)

12

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CMOS SRAM Analysis (Write)

WL

V DD
M4

M5

M6

Q= 0
Q= 1
M1

V DD

BL = 1

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BL = 0

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CMOS SRAM Analysis (Write)

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6T-SRAM Layout

M2

VDD

M4

Q
M1

M3

GND
M5

BL

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M6

WL

BL

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3-Transistor DRAM Cell

WWL
WWL

RWL

write
Vdd

M3
M1

BL1
Vdd-Vt

M2

Cs

RWL
BL2

read
Vdd

BL2

BL1

No constraints on device sizes (ratioless)

Reads are non-destructive <Leakage>
Value stored at node X when writing a 1 is VWWL - Vtn
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1-Transistor DRAM Cell

WL
WL
M1
Cs

CBL

BL

write
1

read
1

X
X

Vdd-Vt

Vdd

BL
Vdd/2

sensing

Write: Cs is charged (or discharged) by asserting WL and BL

Read: Charge redistribution occurs between CBL and Cs
Read is destructive, so must refresh after read
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DRAM Cell Observations

1T DRAM requires a sense amplifier for each bit line, due to charge redistribution
read-out.
DRAM memory cells are single ended in contrast to SRAM cells.
The read-out of the 1T DRAM cell is destructive; read and refresh operations are
necessary for correct operation.
Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be
explicitly included in the design.
When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss
can be circumvented by bootstrapping the word lines to a higher value than VDD

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ASIC/FPGA Design Flows

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ASIC Design Flow

ASIC tools are generally

driven by scripts

Post-synthesis static timing

analysis and equivalency
checking are musts for
sign off to foundry

Verification of deep submicron effects (secondand third-order effects) is

required for ASICs

Internal, deep sub-micron

effects are already verified
for Xilinx FPGAs

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FPGA Design Flow

FPGA tools are generally

GUI-driven, pushbutton flows

FPGA tools also have scripting

capabilities

After the design passes

behavioral simulation and static
timing analysis, verification is
completed most efficiently by
verifying in circuit

Static timing analysis is used to

verify timing of the design

Timing simulation is supported

This is a simplified/typical design

flow

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ASIC Implementation

Create HDL

Synthesis

Optimized for ASIC

technology and area

Primarily driven by scripts

Synopsys design compile
Design for test logic insertion
(BIST, Scan, and JTAG)

Place & route

Foundry tools, Cadence,

AVANT

BIST: Built-In Self Test

JTAG: Joint Test Action Group
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FPGA Implementation

Create HDL

Synthesis

Optimized for Xilinx FPGAs and

performance

Synopsys, Mentor
Pushbutton flow with
scripting capabilities

Place & route

Completed by the user
Xilinx implementation tools
ISE software
Pushbutton flow, scripting capabilities

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ASIC Verification

Key ASIC verification points

Behavioral simulation*

Post-synthesis static timing analysis

Post-synthesis equivalency checking

Post-place & route static timing analysis*

Post-place & route equivalency checking

Post-place & route timing simulation*

Verification of second- and third-order

effects

Verify in circuit*

* Applies to both FPGA and ASIC design flows

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FPGA Verification

Three key verification points for

FPGA implementation

Behavioral simulation
Post-place & route static timing
analysis
Download and verify in circuit

Post-synthesis gate-level
simulation
and post-place & route timing
simulations can be done for
production sign off

Post-place & route timing

simulations are also often done
to verify board- and system-level
timing

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Deep Sub-Micron Effects

Second- and third-order effects

Silicon-induced design flaws due to

the small wire delays and narrow
silicon of deep sub-micron processes
They include cross talk, interconnect
delays, and Process variations

Xilinx FPGAs inherently have

fewer deep sub-micron silicon
issues

Pre-engineered standard product

alleviates complex deep sub-micron
design issues
Recovers design innovation time and
facilitates time-to-market

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Design for Test Logic

ASIC test-generation logic is not required

in a Xilinx FPGA

Because of the capability to test in-circuit,

automatic test pattern generation logic is
normally not included
- This reduces the time spent on creating and
inserting test logic, and allows more time to be
spent on the bench testing the design

Xilinx FPGAs already contain JTAG (boundary scan)

logic

Xilinx FPGAs have readback capability that is similar to

scan logic

Readback can verify the configuration as well as the internal

status of registers and memory

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Firmware Development
ASIC Design Flow

Firmware development begins

much earlier in the design cycle
for FPGAs

No waiting time for prototypes

Hardware and software can develop
in tandem

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Design Flow Comparison

ASIC

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FPGA

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