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1.
Introduction
A = Cai.2-n+i
i=O
n- 1
B = Cbi.2-n+i
i=O
388
2n- 1
p = Cpi.2-2n+i
i=O
map-I
PZn-1
n"-l,n-l
m-19-2
P2,.2
Ph.3
----- - - - - -P,
nn-i,l b - 1 . 0
P,.I
- - - - - -PI
RI
389
addition, the correction constant is allowed to take arbitrary values. For practical
implementations, however, the correction constant should be limited to the n+k
most significant columns, as shown in Figure 2.
This paper presents a method for truncated multiplication in which the correction
constant compensates for both the rounding error and the reduction error. The value
of the correction constant is restricted so that it can be added to the truncated partial
products with only a small amount of additional hardware. Section 2 gives a
method for selecting the correction constant so that the average and mean square
error are minimized. In Section 3, estimates are derived for the average, mean
square and maximum error of truncated multipliers. Hardware savings for truncated
array [2] and Dadda [3] multipliers are discussed in Section 4. Section 5 examines
two's complement truncated multiplication.
2.
To compensate for the reduction and rounding errors, a correction constant is added
to the truncated partial products. The value of the computed product P is
Since all partial product bits in column q have indices i+j = q, and there are q+l
partial product bits in column q, the expected value of the reduction error (i.e., the
additive inverse of the expected value of columns 0 to n-k-1) is
n-k-1
390
To estimate the expected value of the rounding error, it is assumed that the
probability of any product bit pi being one is 0.5. If the product bits Pn-k to Pn-1
are truncated, the expected value of the rounding error is
q=n-k
The expected value of the total error is the sum of expected reduction error and the
expected rounding error
n-k-1
Etotal =
C(q+1).2-2W - 2"-1.(1 - 2-9
-4'
*
q= 0
ro~nd(2~+~-E,,,1)
2n+k
3.
If the correction constant is the additive inverse of the expected value of the error,
then the average error of the truncated multiplication is zero. However, since the
correction constant is restricted to the n+k most significant columns, the average
error is equal to the sum of the correction constant and the expected value of the
error.
Because the correction constant is computed by rounding the expected value of the
error to n+k bits, the magnitude of Eavg is always less than or equal to 2-n-k-1.
The reduction error and the rounding error are assumed to be independent.
Therefore, the total mean square error of the truncated multiplication is the sum of
the mean square value of each of these errors. To calculate the two errors
separately, a partial correction constant is assigned to each error term.The sum of
the two partial correction constants is equal to the total correction constant C. The
partial correction constants for the reduction and rounding error are chosen as
Creduct = -beduct
cround =
391
beduct
The mean square reduction error (i.e., the sum of the variance of the partial product
bits in columns 0 through n-k-1) is
n-k-1
q=o
The mean square rounding error is the mean square difference between the rounding
correction constant and the value of the truncated bits and is equal to
2k- 1
02round = 2-k' z(Cround - q*2-n-k)2
q=o
The total mean square error is the sum of the mean square reduction and rounding
enor
n-k-1
02totd
= 3 c(q+1)'22(-2n+9)
2k- 1
2-k. z ( C r o u n d - q'2-n-k)2
q=o
q=o
To compute the maximum absolute error, the observation is made that the
maximum absolute error occurs either when all of the partial products bits in
columns 0 to n-k- 1 and all the product bits in columns n-k to n- 1 are ones or when
they are all zeros. If they are all ones, the maximum absolute error is
n-k-1
I c - c(q+1).2'2n+q -
2-"( 1-2-k) I = I
c + 4.Er,duct + 2.EroundI
q=o
If they are all zeros, the maximum absolute error is C. Thus, the maximum
absolute error is
E,
= max(C,
I c + 4.Ereduct+ 2*ErOundI)
Table 1 shows the average, mean square and maximum absolute error, and the
correction constant for several truncated multipliers. The following values are used
in the table
C'=C.2"
E'avg = Eavg.2n
oq2totd
=~
~ ~ t ~ Elmax
t ~ l =.Emax.2"
2 ~ ~
392
Eave = 2-n-1
C'=5
oV2total=
12
E'max =
For the multipliers listed, o'2total is less than 0.09 and E',,
is less than 1.0, for
k greater than rlog2(n)l. The average error varies greatly because it depends on the
how close the expected value of the error is to a fixed point number which can be
represented using n+k bits.
i1
8
8
16
16
16
16
16
16
16
24
24
24
24
E'avg
12total
o.:5
4
5
1 I
C'
8
1
2
3
4
5
6
16
1
2
3
4
-9.766~10-~0.1667
+6.152.10-2 0.1040
0.625 +6.152*10-2 0.0903
0.5
-1.660-10-2 0.0842
0.5
-9.766-10-4 0.0834
0.5
1.953.10-3 0.0833
2
-3.815*10-6
1.25 +6.250-10-2
0.875 +6.250.10-2
0.625 -1.563-10-4
0.5625 -3.815-10-6
0.53125 +3.902.10-3
0.5
+7.629*10-6
3
-1.490-10-8
I 1.75 I +6.250.10-2
1.25 +6.250*10-2
0.75
-1.563-10-2
0.625 -1.490-10-8
0.5625 +3.906*10-3
0.5
%Savings %Savings
Anay
Ddda
2.5039
35.4
41.8
1.2539
23.9
28.8
0.7539
15.2
18.6
0.6289
9.28
11.9
0.5352
4.36
6.14
0.5000
0.00
0.00
E'max
+2.980*10-*
4.
Hardware Savings
393
gates, n2 - 2n full adders, and n half adders. If the least significant t columns are
not used in the computation, where t = n-k, the hardware saved (for t 2 2) is
ANDGates
jt-l).(t-2)
Full Adders
2
To add the correction constant to the truncated partial products, m half adders are
changed to full adders, where m is the number of ones in the correction constant.
Dad& introduced an efficient method for implementing multiplier trees in [3]. A
conventional n by n Dadda multipliers requires n2 AND gates, n2 - 4.n + 3 full
adders and n - 1 half adders (for n 2 3). In addition, a (2n-21-bit carry look-ahead
adder (CLA) is required lo sum the final two rows. The hardware saved with a
truncated Dadda multiplier (for t 2 2) is
o.(2t-l)Full Adders
The reduction in the number of half adders is between 1 and t, depending on the
values of n and k. The word-length of the CLA is reduced by t-1 bits. An
additional m full adders are required to add the correction constant to the truncated
partial products.
Table 1 shows the hardware savings for various sizes of truncated multipliers. The
values given correspond to the hardware savings of truncated multipliers compared
with conventional multipliers which implement round to nearest by adding a one
to column n-1. For this table, the relative sizes of the AND gates, half adders and
full adders are 1.4 and 9, respectively. The relative size of each full adder in the
CLA is 9 and a 4-bit CLA logic block has a relative size of 20.
5.
The analysis presented in the previous sections will now be extended for two's
complement multiplication. A two's complement n+ 1 by n+ 1 multiplication
matrix [7]is shown in Figure 3. This matrix is similar to the matrix for unsigned
multiplication. However, the most significant bit (msb) of partial products 0
through n-1 and all the bits except the msb of partial product n are complemented,
and a one is added to column n+l. The values of the multiplicand, multiplier and
product are
394
6.
Conclusion
395
References
Y .C. Lin. Single precision multiplier with reduced circuit complexity for
signal processing application. IEEE Transactions on Electronic Computers,
(41):1333-1336, 1992.
S.D. Peraris. A 40 ns 17-bit array multiplier. IEEE Transactions on
Computers, (20):442-447, 1971.
L. Dadda. Some schemes for parallel multipliers. Aha Frequenza, (34):349356, 1965.
396