Layout Design of Inverter

VLSI Design
06-88-531-01
Assignment- 01
Golam Md. Zubaer Kaiser Khan

[ID: 103061528]
Layout Design of Inverter
The size of PMOS: Width/ Length= 1.3 micron/ 0.18 micron

The size of NMOS: Width/ Length= 0.78 micron/ 0.18 micron
The ratio of PMOS to NMOS= 1.68:1.
The width of the PMOS is 1.68 times greater than the NMOS. As it was made to give higher speed,
less delay times and switching times, that is why the width of PMOS is about to double of the NMOS
width. In this type of design there may be higher power consumption due to the size of the PMOS.
For reducing the power consumption, in the PMOS active layer, two contacts were used instead of
one so that the total area of the active layer of PMOS would be reduced. It is good to say here that,
the design is not an ideal one, and the measurements I have got from the simulation, has some
distortions from the ideal measurements.
Some screenshots, Tables and calculations from the inverter without Parasitic Capacitance:
Layout View
Extracted View
The overall area of the Transistor: 2.65 X 7.6 = 20.14 Pico SqM.

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Input
Output
The Output Graph: (Normal mode and Strip Mode)

The delay time, rise time and fall time for the Simulation: 200ps each of them
Pulse Width used: 3.6n
Period: 8ns

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Calculation of Rise/Fall, Delay times:

Total 3 inverters were used after the shown inverter to measure the delay. The input was in and the
output was out2.
Diagram for testing the Inverter and measuring delay afterwards
The graphs used for measuring the delay are given below:

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10% rise time for IN and OUT2 are respectively: 4.122ns and 4.214ns, delay= (91.28ps/2) = 45.64ps
90% rise time for IN and OUT2 are respectively: 4.213ns and 4.27ns, delay= (57.122ps/2) = 28.56ps
10% fall time for IN and OUT2 are respectively: 8.295ns and 8.382ns, delay= (86.80ps/2) = 43.4ps
90% fall time for IN and OUT2 are respectively: 8.365ns and 8.42ns, delay= (57.41ps/2) = 28.7ps
Total Delay = Sum of all delay/4 = 36.57ps

Rise time = 90% rise time 10% rise time= 4.270n 4.214n = 56ps
Fall time = 90% fall time 10% fall time= 8.423n- 8.382n = 41ps
Calculation of Power Consumption:
The output waveform of the Power Circuit:

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Final Calculation of Power:

The joule got from the calculator* 1.8V/ The period (here 8.049ns) = 3.72W.
Effect of Fan Out for the Inverter without Parasitic Capacitance:
Circuit Diagram:
The output graph:

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Delays with Effect of Fan Out:
10% rise time: 12.257ns and 12.117ns,
Delay= (140.398ps/2) = 70.199ps
Delay= (130.153ps/2) = 65.07ps
10% fall time: 16.4341ns and 16.307ns,
Delay= (127.072ps/2) = 63.536ps
Delay= (125.705ps/2) = 62.8525ps

Fall time = 90% fall time 10% fall time= 16.520n 16.434n = 86ps

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DC Analysis of the Inverter:
Graph with the marker in the 10% and 90% value

Comparing the two graphs, it is seen that, as I have increase the width of my PMOS than NMOS, so
the switching point also increases. If the width of the PMOS and NMOS would same, then the
switching point would me most likely in the range of 10% to 90%. But in this case, the switching
point and the range increases. The range starts from less than 10% and goes beyond 90%, this will
consume more power to operate. As the design is for the consideration of both speed and power, so
the inverter will not be high speedy as well as it will not consume more power.

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Parametric Analysis of the Inverter:
(DC Mode)
Normal Mode
Strip mode

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From the above two graph, it is seen that the inverter will be fully optimized if the width of the
PMOS would have 0.7 micron. The red color strip shows the most optimized ones. But if the PMOS
width changed to 0.7 micron, then the NMOS width will be the same as PMOS width. That design
will be more power efficient but the speed of the transistor will not be so high.
The Parametric Analysis is shown in Transient mode below:

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Measurements with Parasitic Capacitance:
Extracted View:
It is seen that as capacitor is placed in front of each of the transistors. The values of the capacitors
are shown in the extracted view.
The same circuit diagram has to be used in the test of measuring delays, power consumption etc.
Just in the place of normal Inverter, one same size and same area Inverter extracted with Parasitic
Capacitance have to use. And all other circuit diagram and the simulation values will remain same.

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Delay Measurement:
Total 3 inverters were used after the shown inverter to measure the delay. The input was in and the
output was out2.
10% rise time 12.121ns and 12.207ns,
Delay= (85.941ps/2) = 42.970ps
Delay= (62.46ps/2) = 31.23ps
Delay= (90.017ps/2) = 45ps
Delay= (60.476ps/2) = 30.238ps


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Calculation of Power Consumption:
The output graph after the Simulation comes like this:

Here the period for the selected wave output is 8nS.
After calculating the power by the calculator, I got the value like this:
The consumed power by the Inverter with Parasitic capacitance is = 3.9W.

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DC Analysis of the Inverter with Parasitic Capacitance:
From the graph it is seen that, the switching point increases as it is connected with a capacitor. The
previous result was: M0(693mV, 1.622V) where as the recent value is M0(704.8mV, 1.622V). The M1
point did not change much as that increases from 854mV to 856mV. But the M0 increased more for
the capacitor connection.
Summarize Table of the Inverter:
Comparison
Difference in Rise
Time
Difference in Fall
Time
Total Delay
Power
Consumption
Without
Parasitic
56ps
41ps
36.57ps
3.77W
With Parasitic
70ps
44ps
37.36ps
3.90 W

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Layout Design of 2-Input NAND Gate

Overall Area of NAND Transistors: 4.12 X 7.7 = 31.724 Pico SqM.
Some screenshots, Tables and calculations from the NAND without Parasitic Capacitance:
Layout View
Schematic View
Layout View

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Extracted View
The Output Graph:

Period: 8ns

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For logic 11 and 00:
Output Line
Calculation of Rise/Fall, Delay times without Parasitic Capacitance:

Total 3 NAND were used after the shown NAND to measure the delay. The input was in and the
output was out2.

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Delay= (89.857ps/2) = 44.9285ps
90% rise time: 12.1745s and 12.2763ns,
Delay= (101.848ps/2) = 50.924ps
Delay= (105.133ps/2) = 52.5665ps
Delay= (89.56ps/2) = 44.78ps

Rise time = 90% rise time 10% rise time= 12.2763n 12.1965n = 79.8ps
Fall time = 90% fall time 10% fall time= 16.4982n 16.4283n = 69.9ps

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Calculation of Power Consumption without Parasitic Capacitance:

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Final Calculation of Power without Parasitic Capacitance:


Circuit Diagram:
The output graph:

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Delays with Effect of Fan Out without Parasitic Capacitance:
Delay= (129.07ps/2) = 64.535ps
90% rise time: 12.207ns and 12.373ns
Delay= (165.23ps/2) = 82.615ps
10% fall time: 16.314ns and 16.478ns
Delay= (163.549ps/2) = 81.77ps
Delay= (154.402ps/2) = 77.201ps


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Extracted View:
Delay Measurement with Parasitic Capacitance:

Total 3 NAND were used after the shown inverter to measure the delay. The input was in and the
output was out2.

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Delay= (93.98ps/2) = 46.99ps
Delay= (107.125ps/2) = 53.56ps
Delay= (107.171ps/2) = 53.58ps
Delay= (94.72ps/2) = 47.368ps


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Calculation of Power Consumption with Parasitic Capacitance:

Here the period for the selected wave output is 8.028nS.

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Effect of Fan Out for the NAND with Parasitic Capacitance:

Delays with Effect of Fan Out with Parasitic Capacitance:
Delay= (138.23ps/2) = 69.115ps
Delay= (192.41ps/2) = 96.205ps
Delay= (164.58ps/2) = 82.29ps
Delay= (166.5ps/2) = 83.25ps


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Summarize Table of the 2-Input NAND:
Comparison
Difference in Rise
Time
Difference in Fall
Time
Total Delay
Power
Consumption
Without
Parasitic
79.8ps
69.9ps
48.29ps
4.33W
With Parasitic
83.4ps
74.5ps
50.374ps
1.710 W
Fan Out
Difference in Rise
Time
Difference in Fall
Time
Total Delay
Without
Parasitic
128.7ps
123ps
76.53ps
With Parasitic
147ps
130ps
82.715ps

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Layout Design of 2-Input NOR Gate

Overall Area of NAND Transistors: 4 X 7.6 = 30.4 Pico SqM.
Layout View
Schematic View
Layout View

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Extracted View
The Output Graph:

Period: 8ns

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Output Line

Total 3 NOR were used after the shown NAND to measure the delay. The input was in and the
output was out2.

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Delay= (133.67ps/2) = 66.835ps
Delay= (118.12ps/2) = 59.06ps
Delay= (133.64ps/2) = 66.82ps
Delay= (119.23ps/2) = 59.615ps


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Circuit Diagram:

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Delay= (213.71ps/2) = 106.855ps
Delay= (208.11ps/2) = 104.055ps
Delay= (198.08ps/2) = 99.04ps
Delay= (213.75ps/2) = 106.875ps

Extracted View:

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Total 3 NOR were used after the shown inverter to measure the delay. The input was in and the
output was out2.
Delay= (135.23ps/2) = 67.615ps
Delay= (122.34ps/2) = 61.17ps
Delay= (139.62ps/2) = 69.81ps
Delay= (129.99ps/2) = 64.995ps


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Effect of Fan Out for the Inverter with Parasitic Capacitance:

Delay= (227.99ps/2) = 113.99ps
Delay= (223.97ps/2) = 111.98ps
Delay= (216.6ps/2) = 108.3ps
Delay= (229.45ps/2) = 114.725ps


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Summarize Table of the 2-Input NOR:
Comparison
Difference in Rise
Time
Difference in Fall
Time
Total Delay
Power
Consumption
Without
Parasitic
134ps
62.4ps
63.08ps
4.996W
With Parasitic
143ps
75ps
65.89ps
1.67 W
Fan Out
Difference in Rise
Time
Difference in Fall
Time
Total Delay
Without
Parasitic
250ps
120ps
104.21ps
With Parasitic
256ps
127ps
112.24ps

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Layout Design of 2-Input XOR Gate

Layout View
Output
Output
Schematic View and Logic Table

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Extracted View
The Output Graph:

Period: 8ns

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Total 3 XOR were used after the shown NAND to measure the delay. The input was in and the output
was out2.

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Delay= (215.62ps/2) = 107.81ps
Delay= (215.82ps/2) = 107.91ps
Delay= (167.33ps/2) = 83.665ps
Delay= (229.48ps/2) = 114.74ps


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The joule got from the calculator* 1.8V/ The period (here 8.007ns) = 11W.

Circuit Diagram:

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Delay= (412.28ps/2) = 206.14ps
Delay= (420.15ps/2) = 210.075ps
Delay= (317.04ps/2) = 158.57ps
Delay= (438.59ps/2) = 219.295ps


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Extracted View:

Total 3 XOR were used after the shown inverter to measure the delay. The input was in and the
output was out2.

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Delay= (279.57ps/2) = 139.785ps
Delay= (281.48ps/2) = 140.74ps
Delay= (214.352ps/2) = 107.176ps
Delay= (290.697ps/2) = 145.35ps

Fall time = 90% fall time 10% fall time= 12.59n-12.40n = 190ps

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Delay= (538.74ps/2) = 269.37ps
Delay= (547.42ps/2) = 273.71ps
Delay= (417.94ps/2) = 208.97ps
Delay= (571.22ps/2) = 285.61ps


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Summarize Table of the 2-Input XOR:
Comparison
Difference in Rise
Time
Difference in Fall
Time
Total Delay
Power
Consumption
Without
Parasitic
230ps
158ps
103.53ps
11 W
With Parasitic
295ps
190ps
133.2ps
1.42 W
Fan Out
Difference in Rise
Time
Difference in Fall
Time
Total Delay
Without
Parasitic
460ps
320ps
198.52ps
With Parasitic
600ps
500ps
259.415ps

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Layout Design of a FULL-ADDER

Some screenshots, Tables and calculations from the Full-Adder without Parasitic Capacitance:
Layout View

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Cin
Sum
Cout
Schematic View and Logic Table
In the diagram, there are two AND gates, and one OR gate. But as O implement NAND and NOR gate,
so I have used them instead of AND and OR gate, with the Inverter. So that, it can work as AND and
OR gate. So in this modified diagram, total 3 inverters are used.

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Extracted View
The Output Graph:
Period: 8ns
Cout
Sum
Cin

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Sum
Cout
Cin
For Logic 001 and 100:
Cout
Sum
Cin

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Total 3 Adder were used after the shown NAND to measure the delay. The input was in and the
output was out2.
Delay= (636.36ps/2) = 318.18ps
Delay= (636.67ps/2) = 318.335ps

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Delay= (444.80ps/2) = 222.4ps
Delay= (447.76ps/2) = 223.88ps


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Circuit Diagram:

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Delay= (933.88ps/2) = 466.94ps
Delay= (936.18ps/2) = 468.09ps
Delay= (587.74ps/2) = 293.87ps
Delay= (584.20ps/2) = 292.1ps


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Total 3 Adder were used after the shown inverter to measure the delay. The input was in and the
output was out2.
Delay= (829.05ps/2) = 414.525ps
90% rise time: 8.91ns and 9.75ns ,
Delay= (832.90s/2) = 416.45ps
Delay= (574.29ps/2) = 287.145ps
Delay= (572.56ps/2) = 286.28ps


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Circuit Diagram:

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The output graph after the Simulation comes like the above:

Delay= (1.22ns/2) = 610ps
Delay= (1.21ns/2) = 605ps
Delay= (785.33ps/2) = 392.66ps
Delay= (784.57ps/2) = 392.285ps

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Fall time = 90% fall time 10% fall time= 13.43n-13.13n = 300ps
Summarize Table of the FULL-ADDER:
Comparison
Difference in Rise
Time
Difference in Fall
Time
Total Delay
Power
Consumption
Without
Parasitic
250ps
100ps
270.70ps
30.72 W
With Parasitic
350ps
140ps
351.10ps
1.4999 W
Fan Out
Difference in Rise
Time
Difference in Fall
Time
Total Delay
Without
Parasitic
490ps
220ps
380.25ps
With Parasitic
680ps
300ps
499.98ps

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Layout Design of Inverter

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Layout Design of Inverter

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VLSI Design

Golam Md. Zubaer Kaiser Khan