A Novel Multilevel Inverter With Reduced Count of

Power Switches

Mohd Wajahatullah Naseem

AmitMohod

Department of Electrical & Electronics Engineering

Prof Ram Meghe College of Engineering & Management,
Badnera-Amravati, India
mw.nasim@gmail.com

Department of Electrical & Electronics Engineering

Prof Ram Meghe College of Engineering & Management,
Badnera-Amravati, India
amitmohodl @gmail.com

Abstract-In this paper, a novel cascaded multilevel inverter

different amplitude of the voltage sources and symmetric

cascaded multilevel inverter having same magnitude of all the
dc voltage sources which are connected at the input side. The
main advantage offered by the asymmetric type of cascaded
multilevel inverter is that, it is able to generate more number
of outputs level when compared to the symmetric one. This is
because of the different amplitude of dc voltage sources that
are connected at the input side. Because of this feature of the
asymmetric cascaded multilevel inverter, the installation
space and total cost decreases of the asymmetric one than the
symmetric type of inverter [6, 12, 13].

topology is proposed for a single phase inverter. The inverter is

composed of a series connection of the suggested basic unit and
it generates only positive levels at its output. Hence an H-bridge
is further added to the proposed basic unit. The proposed
topology has the main advantage of reduction in the count of
power switches and driver circuits required to drive them that
helps to lower the cost and ultimately the overall installation
space. The proposed structure also has less dc voltage sources
and driver circuits, when it is compared to the other inverter
topologies. At the output voltage, the final inverter structure is
able to produce all the voltage levels (positive as well as
negative).

The

simulation

is

performed

for

verifying

the

Different multilevel topologies are proposed in the

literature for reducing the total device count. In [6, 14-19],
different topologies are introduced for the symmetric
cascaded multilevel inverters. Because of the equal magnitude
of the input dc voltage sources, the symmetric cascaded
multilevel inverter suffers from the requirement of more
number of power electronic switches, power diodes, and
insulated gate bipolar transistors (lGBTs) and driver circuits.
It is required to use the IGBTs in place of the power switches.
So if the basic unit need bidirectional switch, in that case these
drawbacks will be even more as two IGBTs are needed to be
connected in anti-parallel fashion along with two anti-parallel
diodes. Nevertheless the unidirectional and bidirectional
switches conduct current in any direction. For increasing the
number of levels, a number of asymmetric cascaded
multilevel inverter topologies have been presented in [6, 13,
15, 20, 21]. The demand for the magnitude of dc voltage
sources is high as the number of voltage levels is increased
that is the major drawback of these inverters.

operation of the inverter for a three cascaded stages of the basic

unit that generates 37-levels at its output.

Keywords-Inverter; multilevel inverter; power switches; 37levels; H-bridge; Cascaded inverter.

1.

INTRODUCTION

PRESENTLY the multilevel inverters are becoming

popular because of their numerous applications in high-power
and high voltage application. In case of multilevel inverters,
the preferred output voltage is produced by appropriate
combination of several low voltage dc sources connected at
the supply side. With the increase of the dc sources, the output
voltage waveform befits to a pure sinusoidal waveform
reducing the value of the total harmonic distortion (nID) and
the overall power quality increases. Moreover multilevel
inverters offers lower switching losses, good electromagnetic
compatibility and high efficiency. Other than batteries, it is
possible to connect the fuel cells and photovoltaic cells as an
input to the multilevel inverters [1-6]. The multilevel inverters
are classified into three categories; cascaded multilevel, flying
capacitor (FC), neutral point clamped (NPC) [6-10]. In case
of cascaded multilevel inverters, diodes and flying capacitors
are not used. These inverters require less number of power
switches to generate a particular level, making the control of
the switches simple and reliable [1, 6, 11, 12]. As a result,
reducing the total cost and losses of these inverters and
increasing the efficiency [6, 13]. Thus the cascaded multilevel
inverters have received more attention. These inverters are
comprised of series connection of basic units, which consist
of different array of power switches and dc voltage sources.
In general, these inverters are classified into two main
categories; asymmetric cascaded multilevel inverter having

978-1-4799-8371-1/15/$31.00 2015 IEEE

A new basic unit is proposed in this paper for increasing

the number of levels at the output voltage and reducing the
count of the power electronic switches. More number of levels
is achieved by connecting the proposed basic unit in a series
connection to the several proposed basic unit and hence a new
cascaded multilevel inverter is introduced which generates a
single phase output voltage. The inverter is referred as
advanced proposed multilevel inverter. The proposed basic
unit generates only the positive levels at the output. For
generating both positive as well as negative levels an H-bridge
should be added to the series connection of the basic proposed
unit. A new switching schemes is also suggested to generate
more number of levels with the same basic proposed unit. A
number of comparisons have been done between the

64

introduced multilevel inverter and the conventional multilevel

inverters. Finally, the functioning and the proper operation of
the advanced multilevel inverter is reconfirmed by the
simulation of a 37-level inverter that is based on the proposed
basic unit.

TABLE I
SWITCHING SCHEME FOR THE PROPOSED BASIC UNIT
Switches states

state

The proposed basic unit is as shown in Fig. 1. The

proposed basic unit consists of three power switches and two
dc voltage sources. Isolated dc voltage sources are used
which are supplied by the renewable sources such as,
photovoltaic, fuel cell etc. To prevent the short circuit of dc
voltage sources, the power switches (SI.S3), (S2.S3) and (SI.S2)
should not be turned on at the same time. The switching
scheme for the proposed basic unit is shown in Table I. It is
clear from the Table I that the proposed basic unit is able to
produce three different voltage levels at its output which are
0, Va and Va+Vb. It may also be note that the basic proposed
unit is only able to produce the positive voltages at its output.
For increasing the number of voltage levels at the output,
the proposed basic unit is connected in series. The output
voltage level of each of the basic unit is denoted by VOUlI, Voul2,
...., Voutn. The level of the output voltage VOUI of the proposed
cascaded multilevel inverter is given by the equation:

S2

S3

on

off

off

off

off

on

Va

off

on

off

Va+Vb

equal to the output voltage of the cascaded connection of the

proposed basic units which is VOUI. For generating the negative
levels across the load, switches T3 and T4 are turned on
simultaneously making load voltage Vload equals to -VOUI.
For the proposed multilevel inverter structure,
respectively, the number of power switches required (Ns) and
the number of dc voltage sources (Nvs) required are given by
the following equations:

(2)

Ns= 3n+4
Nvs = 2n (3)

where n is the number of series connected basic units. The

number of power switches used in the proposed inverter is

(1)
All the voltage levels that can be generated by the
proposed cascaded multilevel inverter depending upon the on
and off states of the power switches are shown in Table II. As
aforementioned and also according to the Table II, the
proposed inverter which is shown in Fig. 2 is able to produce
only positive levels at the output of the cascaded series
connection of the proposed basic unit. Hence, for generating
both the positive as well as negative levels, an H-bridge is
added at the output of the proposed topology with four
switches TI to T4. This inverter is named as advanced
cascaded multilevel inverter which is shown in Fig. 3. For
generating the positive voltage levels at the output of the
proposed inverter, switches TI and T2 are turned on
simultaneously and in this case the load voltage Vload will be

VB

/.. .. .. .\...

\ S3)

VOlit

S,

II. PROPOSED TOPOLOGY

tI
I
I
II
I
I
I
I
I
I
,
I
I
I
I

Unit 1

VOIl/I

... .... ...... ... ... ................................

..... ...... .. ..............
....................
i+

V2B

Unit 2

tJ
21 f--J
S22

V2A

it

:1
; I
11
S23: 1

!VOU/2

Vow

:1
; I

..................... .............................. ,i

Vaut

\"('.:
\

Fig. I. Proposed basic unit

2015

y,:.i

.
.

Fig. 2. The proposed cascaded multilevel inverter topology

International Conference on Power and Advanced Control Engineering (ICPACE)

65

!+

i+

Sl1

Unitt

II

Vi~

S13!

I Voutl

!ilI

SI2

!! II

iI
, I

VIA

............................._..................1r_ _-1 t

TI

il

V2B~

r&!i~

l__:_Jl

UnY,I th,

used at the input. In order to generate all the possible voltage

levels at the output, the switching scheme is shown in Table
II. The proposed multilevel inverter is considered as an
asymmetric inverter as the magnitude of the dc voltage
sources are different. By considering the equation of the
highest voltage level that can be generated at the output when
compared to the case of symmetric multilevel inverter, in
which the amplitude of the dc sources are same, is less than
the asymmetric one, in which the magnitude is different with
the equal number of switches and the dc voltage sources.

In this paper, a new method is proposed to define the

magnitudes of dc voltage sources in order to increase the
maximum amplitude of generated voltage and number of
produced levels at the output of the advanced multilevel
inverter. The method to choose the magnitudes of dc voltage
sources is as follows:

Vout

VnA

r-.. . . . _.. . . . . _. . . _1 t
;

Vn;r

Unit n!1, ..,.1

"

In this advanced cascaded multilevel inverter, the

maximum number of voltage levels that can be generated at
the output of the inverter is:

r~2 sJ! II

Vou,"

Nlevel

i
ii
!
1..................-.-..:.:...................1

(4)

VnB = (2n-l)Vdc

=4

X (Li~l

2i-l) + 1

(5)

The highest voltage level that can be produced by the

multilevel inverter at its output is given by

(6)

Fig. 3. Advanced proposed cascaded inverter

III. COMPARISON WITH THE OTHER PROPOSED TOPOLOGIES

equal to the number ofIGBTs, power diodes, because of the

unidirectional power switches. It may be also noted that, the
other main factor in calculating the total cost of an inverter is
the blocking voltage of switches. The overall cost of the
inverter can be decreased by decreasing the value of blocking
voltage ofthe power switches [12].

The main reason to propose the advanced multilevel

inverter is to decrease the count of power switches that are
used in the cascaded multilevel inverter topologies. Hence,
comparison is carried out with the other proposed topologies
on the basis of number of IGBTs, dc voltage sources and
driver circuits used. In [6], a new inverter has been presented
which is considered as RQ here and four different algorithms
are suggested for the same inverter which are considered as
PI to P4. Fig. 4 shows the above mentioned inverter.

In the advanced inverter, the number of levels produced

at the output of the inverter and maximum amplitude of
voltage are based on the magnitude of the dc voltage sources
TABLE II

SWITCHING SCHEME OF THE SWITlCHES FOR THE DIFFERENT OUTPUT VOLTAGE LEVELS GENERATED AT THE OUTPUT
Vout

Sl1

S12

S13

S21

S22

S23

S31

S32

S33

on
off
off
on
off
on
off
off
on

off
off
on
off
off
off
off
on
off

off
on
off
off
on
off
on
off
off

on
off
off
off
off
on
on
on
off

off
off
on
off
off
off
off
off
off

off
on
off
on
on
off
off
off
on

on
off
off
on
off
off
off
off
off

off
off
on
off
off
off
off
off
off

off
on
off
off
off
on
on
on
on

off

on

off

on

off

off

off

on

off

VIA
VIA+VIB
V2A
VIA +V2A
V3A
VIA +V3A
VIA + VIB +V3A
V2A+V3A

...
...
...
...
...
...
...
...
...
...

Sil

Si2

Si3

on
off
off
on
on
on
on
on
on

off
off
on
off
off
off
off
off
off

off
on
off
off
off
off
off
off
off

off

on

off

(V;AH'iB)

i=1

66

2015 International Conference on Power and Advanced Control Engineering (ICPACE)

40
30

20
Ndriver

Proposed

10

L0
0

10

Nlevel

20

40

30

Fig. 6. Comparison Nd""" versus Mml

cost of the inverter can be decreased significantly that can be

used for different applications.
IV.

SIMULATION RESULTS

The simulation results in MATLAB/Simulink is used to

prove the correct operation of the proposed cascaded
multilevel inverter topology in desired output voltage
waveform generation. The simulation results for a 37-level
advanced multilevel inverter is presented. Fig. 7 shows the
simulated cascaded multilevel inverter. The value of used dc
voltage sources are VIA=VIB=]OV, V2A =V2B=30V and
V3A=V3B=50V.
The MATLAB/Simulink model for this inverter is
shown in Fig. 8. This inverter is able to generate 37 levels at
Fig. 4. Proposed inverter topology in [6]

,+

Fig. 5 shows the comparison of the number of IGBTs

used in the proposed topology with the topology mentioned
in [6]. It is evident from the comparison that the proposed
multilevel structure demands a smaller amount of IGBTs to
produce more number of levels. Fig. 6 shows the comparison
of the required number of driver circuits for generating the
maximum levels at the output. In the proposed structure, the
switch Tl and T2 requires the same driver circuit, same is the
case for T3 and T4. Thus total requirement of the driver circuit
is also smaller than the topology which is proposed in [6].
As the requirement of the number of power switches as
well as the driver circuit is decreased and hence the overall

Unit

lovT

'2

I! s" r
j

SI3

! I
I

1! vOUlI
!: II

,I
: I

! 1i

I1;

t......
....................
.. ............ .............................
........................... ;

Unit

2!

20vT

S21

!'II

r22

sii
2:

20V

j,II

3 1I1Volt12
: I
,I
: I
,I

VOIII

--:--+
lIoad

t.................... ............................ J-

40
30

20

NIGHT

Umt 3

10

IOV

:t

r;{
lH
r i!
S 31

32

30V

30

Fig. 5. Comparison NIGHT versus Mewl

2015

40

T;

S33 Vo,,'"
: I
,, 11
. 1

1!
1

Fig. 7. 37-level cascaded multilevel inverter

International Conference on Power and Advanced Control Engineering (ICPACE)

67

0.01

0.02

0.03

0.04

0.05

Time!s]

0.06

0.07

0.06

0.09

O. I

(c)
FFTanalysis

Fig. 8. 37-level cascaded multilevel inverter

its output with a maximum voltage of 180 V and requires

Nsw=13 and Nvs=6 which is less when compared to [6].
Compared to the methods presented in [6], the proposed
inverter is able to generate more number of levels with less
number of switches. The load connected to the inverter is a
R-L load with R= son and L=30mH
Fig. 9(a) shows the output voltage waveform of the
proposed inverter topology. It is obvious from the figure that
this inverter produces only positive levels at its output. Hence
it is required to add an H-bridge to make it able to generate
all the voltage levels (positive and negative) at the output of
the inverter. The maximum amplitude of output voltage is
l80Vwhich is also shown in Fig. 9(a).

0.7

Fundamental (50Hz) = 179 . 1

THO=

57'/.

0.6
19 0.5

0.4

'00.3

.:.

0.2
o. 1

100

200

300

400 SOO 600

Frequency (Hz)

700

800

900

1000

900

1000

(d)
FFTanalysil
Fundamental (50Hz) = 3.519, THO= 1.99%

Fig. 9(b) and 9(c) shows the voltage and current

waveforms, respectively. As shown in Fig. 9(b), the
advanced multilevel inverter structure is able to generate step
waveform at its output with 37 levels and a maximum voltage
of l80V. The current waveform shown in Fig. 9(c) is very
much closer to an ideal sinusoidal waveform because of the
resistive-inductive load used, which acts as a low-pass filter.
It is also clear that, there is some phase difference between
100

200

300

400 SOO 600

frequency (Hz)

700

800

(e)
Fig. 9. Simulation results; (a) output voltage wavefonn of the basic unit;
(b) output voltage wavefonn of the 37-level cascaded multilevel inverter;
(c) load current wavefonn with an RL load (R=50n and L=30mH) (d)
Hannonic spectrum of the load voltage; (e) Hannonic spectrum of the load
current.

the voltage and current waveform because of the inductive

load used.
5

The harmonic spectrum of the output voltage waveform

is as shown in Fig. 9(d), which shows a THD of 2.57% and
harmonic spectrum for the load current waveform is shown
in Fig. 9(e), the THD value for this waveform is l.99%,
which is very less and fosters better power quality.
V.

6

68

2015

CONCLUSION

In this paper, a new basic unit is proposed for cascaded

multilevel inverter. A cascaded multilevel inverter is also
proposed with the series connection of several basic units.
The proposed inverter is only able to generate the positive
levels at its output. Therefore an additional H-bridge is

International Conference on Power and Advanced Control Engineering (ICPACE)

connected to the proposed multilevel inverter that makes it

able to generate positive as well as negative voltage levels at
its output. The inverter is called as advanced cascaded
multilevel inverter. A new method is proposed to decide the
magnitude of dc voltage sources. Then comparisons are done
between the advanced cascaded multilevel inverter to the
other inverter. On the basis of the comparison it is found that
the advanced cascaded multilevel topology required lower
number of IGBTs, driver circuits, dc voltage sources and
power diodes than the topology proposed in [6]. For instance
by using 16 number of IGBTs, the advanced cascaded
multilevel inverter is able to generate 65 levels at its output,
requires 14 number of driver circuits and 8 dc voltage
sources. On the other hand, the cascaded multilevel inverter
proposed in [6] with the same number of IGBTs requires 14
driver circuits, 7 dc voltage sources and generates 15, 21, 19
and 27 levels, respectively, if the algorithm PI, P2, P3 and P4
is used.
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2015

International Conference on Power and Advanced Control Engineering (ICPACE)

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